Commit | Line | Data |
---|---|---|
f566e19b SL |
1 | /* |
2 | * Copyright (c) 1984 Regents of the University of California. | |
3 | * All rights reserved. The Berkeley software License Agreement | |
4 | * specifies the terms and conditions for redistribution. | |
5 | */ | |
6 | ||
7 | #ifndef lint | |
bd1e6d2e SL |
8 | static char sccsid[] = "@(#)langpats.c 1.2 (Berkeley) %G%"; |
9 | #endif | |
f566e19b SL |
10 | |
11 | #include "inline.h" | |
12 | ||
13 | /* | |
14 | * Pattern table for kernel specific routines. | |
15 | * These patterns are based on the old asm.sed script. | |
16 | */ | |
17 | struct pats language_ptab[] = { | |
18 | ||
bd1e6d2e | 19 | #if defined(vax) |
f566e19b SL |
20 | { "0,_spl0\n", |
21 | " mfpr $18,r0\n\ | |
22 | mtpr $0,$18\n" }, | |
23 | ||
24 | { "0,_spl1\n", | |
25 | " mfpr $18,r0\n\ | |
26 | mtpr $1,$18\n" }, | |
27 | ||
28 | { "0,_splsoftclock\n", | |
29 | " mfpr $18,r0\n\ | |
30 | mtpr $0x8,$18\n" }, | |
31 | ||
32 | { "0,_splnet\n", | |
33 | " mfpr $18,r0\n\ | |
34 | mtpr $0xc,$18\n" }, | |
35 | ||
36 | { "0,_splimp\n", | |
37 | " mfpr $18,r0\n\ | |
38 | mtpr $0x16,$18\n" }, | |
39 | ||
40 | { "0,_spl4\n", | |
41 | " mfpr $18,r0\n\ | |
42 | mtpr $0x14,$18\n" }, | |
43 | ||
44 | { "0,_splbio\n", | |
45 | " mfpr $18,r0\n\ | |
46 | mtpr $0x15,$18\n" }, | |
47 | ||
48 | { "0,_spltty\n", | |
49 | " mfpr $18,r0\n\ | |
50 | mtpr $0x15,$18\n" }, | |
51 | ||
52 | { "0,_spl5\n", | |
53 | " mfpr $18,r0\n\ | |
54 | mtpr $0x15,$18\n" }, | |
55 | ||
56 | { "0,_splclock\n", | |
57 | " mfpr $18,r0\n\ | |
58 | mtpr $0x18,$18\n" }, | |
59 | ||
60 | { "0,_spl6\n", | |
61 | " mfpr $18,r0\n\ | |
62 | mtpr $0x18,$18\n" }, | |
63 | ||
64 | { "0,_splhigh\n", | |
65 | " mfpr $18,r0\n\ | |
66 | mtpr $0x1f,$18\n" }, | |
67 | ||
68 | { "0,_spl7\n", | |
69 | " mfpr $18,r0\n\ | |
70 | mtpr $0x1f,$18\n" }, | |
71 | ||
72 | { "1,_splx\n", | |
73 | " movl (sp)+,r1\n\ | |
74 | mfpr $18,r0\n\ | |
75 | mtpr r1,$18\n" }, | |
76 | ||
77 | { "1,_mfpr\n", | |
78 | " movl (sp)+,r5\n\ | |
79 | mfpr r5,r0\n" }, | |
80 | ||
81 | { "2,_mtpr\n", | |
82 | " movl (sp)+,r4\n\ | |
83 | movl (sp)+,r5\n\ | |
84 | mtpr r5,r4\n" }, | |
85 | ||
86 | { "0,_setsoftclock\n", | |
87 | " mtpr $0x8,$0x14\n" }, | |
88 | ||
89 | { "1,_resume\n", | |
90 | " movl (sp)+,r5\n\ | |
91 | ashl $9,r5,r0\n\ | |
92 | movpsl -(sp)\n\ | |
93 | jsb _Resume\n" }, | |
94 | ||
95 | { "3,_copyin\n", | |
96 | " movl (sp)+,r1\n\ | |
97 | movl (sp)+,r3\n\ | |
98 | movl (sp)+,r5\n\ | |
99 | jsb _Copyin\n" }, | |
100 | ||
101 | { "3,_copyout\n", | |
102 | " movl (sp)+,r1\n\ | |
103 | movl (sp)+,r3\n\ | |
104 | movl (sp)+,r5\n\ | |
105 | jsb _Copyout\n" }, | |
106 | ||
107 | { "1,_fubyte\n", | |
108 | " movl (sp)+,r0\n\ | |
109 | jsb _Fubyte\n" }, | |
110 | ||
111 | { "1,_fuibyte\n", | |
112 | " movl (sp)+,r0\n\ | |
113 | jsb _Fubyte\n" }, | |
114 | ||
115 | { "1,_fuword\n", | |
116 | " movl (sp)+,r0\n\ | |
117 | jsb _Fuword\n" }, | |
118 | ||
119 | { "1,_fuiword\n", | |
120 | " movl (sp)+,r0\n\ | |
121 | jsb _Fuword\n" }, | |
122 | ||
123 | { "2,_subyte\n", | |
124 | " movl (sp)+,r0\n\ | |
125 | movl (sp)+,r1\n\ | |
126 | jsb _Subyte\n" }, | |
127 | ||
128 | { "2,_suibyte\n", | |
129 | " movl (sp)+,r0\n\ | |
130 | movl (sp)+,r1\n\ | |
131 | jsb _Subyte\n" }, | |
132 | ||
133 | { "2,_suword\n", | |
134 | " movl (sp)+,r0\n\ | |
135 | movl (sp)+,r1\n\ | |
136 | jsb _Suword\n" }, | |
137 | ||
138 | { "2,_suiword\n", | |
139 | " movl (sp)+,r0\n\ | |
140 | movl (sp)+,r1\n\ | |
141 | jsb _Suword\n" }, | |
142 | ||
143 | { "1,_setrq\n", | |
144 | " movl (sp)+,r0\n\ | |
145 | jsb _Setrq\n" }, | |
146 | ||
147 | { "1,_remrq\n", | |
148 | " movl (sp)+,r0\n\ | |
149 | jsb _Remrq\n" }, | |
150 | ||
151 | { "0,_swtch\n", | |
152 | " movpsl -(sp)\n\ | |
153 | jsb _Swtch\n" }, | |
154 | ||
155 | { "1,_setjmp\n", | |
156 | " movl (sp)+,r1\n\ | |
157 | clrl r0\n\ | |
158 | movl fp,(r1)+\n\ | |
159 | moval 1(pc),(r1)\n" }, | |
160 | ||
161 | { "1,_longjmp\n", | |
162 | " movl (sp)+,r0\n\ | |
163 | jsb _Longjmp\n" }, | |
164 | ||
165 | { "1,_ffs\n", | |
166 | " movl (sp)+,r1\n\ | |
167 | ffs $0,$32,r1,r0\n\ | |
168 | bneq 1f\n\ | |
169 | mnegl $1,r0\n\ | |
170 | 1:\n\ | |
171 | incl r0\n" }, | |
172 | ||
173 | { "1,_htons\n", | |
174 | " movl (sp)+,r5\n\ | |
175 | rotl $8,r5,r0\n\ | |
176 | rotl $-8,r5,r1\n\ | |
177 | movb r1,r0\n\ | |
178 | movzwl r0,r0\n" }, | |
179 | ||
180 | { "1,_ntohs\n", | |
181 | " movl (sp)+,r5\n\ | |
182 | rotl $8,r5,r0\n\ | |
183 | rotl $-8,r5,r1\n\ | |
184 | movb r1,r0\n\ | |
185 | movzwl r0,r0\n" }, | |
186 | ||
187 | { "1,_htonl\n", | |
188 | " movl (sp)+,r5\n\ | |
189 | rotl $-8,r5,r0\n\ | |
190 | insv r0,$16,$8,r0\n\ | |
191 | rotl $8,r5,r1\n\ | |
192 | movb r1,r0\n" }, | |
193 | ||
194 | { "1,_ntohl\n", | |
195 | " movl (sp)+,r5\n\ | |
196 | rotl $-8,r5,r0\n\ | |
197 | insv r0,$16,$8,r0\n\ | |
198 | rotl $8,r5,r1\n\ | |
199 | movb r1,r0\n" }, | |
200 | ||
201 | { "2,__insque\n", | |
202 | " movl (sp)+,r4\n\ | |
203 | movl (sp)+,r5\n\ | |
204 | insque (r4),(r5)\n" }, | |
205 | ||
206 | { "1,__remque\n", | |
207 | " movl (sp)+,r5\n\ | |
208 | remque (r5),r0\n" }, | |
209 | ||
210 | { "2,__queue\n", | |
211 | " movl (sp)+,r0\n\ | |
212 | movl (sp)+,r1\n\ | |
213 | insque (r1),*4(r0)\n" }, | |
214 | ||
215 | { "1,__dequeue\n", | |
216 | " movl (sp)+,r0\n\ | |
217 | remque *(r0),r0\n" }, | |
218 | ||
219 | { "2,_imin\n", | |
220 | " movl (sp)+,r0\n\ | |
221 | movl (sp)+,r5\n\ | |
222 | cmpl r0,r5\n\ | |
223 | bleq 1f\n\ | |
224 | movl r5,r0\n\ | |
225 | 1:\n" }, | |
226 | ||
227 | { "2,_imax\n", | |
228 | " movl (sp)+,r0\n\ | |
229 | movl (sp)+,r5\n\ | |
230 | cmpl r0,r5\n\ | |
231 | bgeq 1f\n\ | |
232 | movl r5,r0\n\ | |
233 | 1:\n" }, | |
234 | ||
235 | { "2,_min\n", | |
236 | " movl (sp)+,r0\n\ | |
237 | movl (sp)+,r5\n\ | |
238 | cmpl r0,r5\n\ | |
239 | blequ 1f\n\ | |
240 | movl r5,r0\n\ | |
241 | 1:\n" }, | |
242 | ||
243 | { "2,_max\n", | |
244 | " movl (sp)+,r0\n\ | |
245 | movl (sp)+,r5\n\ | |
246 | cmpl r0,r5\n\ | |
247 | bgequ 1f\n\ | |
248 | movl r5,r0\n\ | |
249 | 1:\n" }, | |
bd1e6d2e | 250 | #endif |
f566e19b | 251 | |
bd1e6d2e SL |
252 | #if defined(tahoe) |
253 | { "4,_spl0\n", | |
254 | " mfpr $8,r0\n\ | |
255 | mtpr $0,$8\n" }, | |
256 | ||
257 | { "4,_spl1\n", | |
258 | " mfpr $8,r0\n\ | |
259 | mtpr $0x11,$8\n" }, | |
260 | ||
261 | { "4,_spl3\n", | |
262 | " mfpr $8,r0\n\ | |
263 | mtpr $0x13,$8\n" }, | |
264 | ||
265 | { "4,_spl7\n", | |
266 | " mfpr $8,r0\n\ | |
267 | mtpr $0x17,$8\n" }, | |
268 | ||
269 | { "4,_spl8\n", | |
270 | " mfpr $8,r0\n\ | |
271 | mtpr $0x18,$8\n" }, | |
272 | ||
273 | { "4,_splimp\n", | |
274 | " mfpr $8,r0\n\ | |
275 | mtpr $0x18,$8\n" }, | |
276 | ||
277 | { "4,_splsoftclock\n", | |
278 | " mfpr $18,r0\n\ | |
279 | mtpr $0x8,$8\n" }, | |
280 | ||
281 | { "4,_splnet\n", | |
282 | " mfpr $8,r0\n\ | |
283 | mtpr $0xc,$8\n" }, | |
284 | ||
285 | { "4,_splbio\n", | |
286 | " mfpr $8,r0\n\ | |
287 | mtpr $0x18,$8\n" }, | |
288 | ||
289 | { "4,_spltty\n", | |
290 | " mfpr $8,r0\n\ | |
291 | mtpr $0x18,$8\n" }, | |
292 | ||
293 | { "4,_splclock\n", | |
294 | " mfpr $8,r0\n\ | |
295 | mtpr $0x18,$8\n" }, | |
296 | ||
297 | { "4,_splhigh\n", | |
298 | " mfpr $8,r0\n\ | |
299 | mtpr $0x18,$8\n" }, | |
300 | ||
301 | { "8,_splx\n", | |
302 | " movl (sp)+,r1\n\ | |
303 | mfpr $8,r0\n\ | |
304 | mtpr r1,$8\n" }, | |
305 | ||
306 | { "8,_mfpr\n", | |
307 | " movl (sp)+,r1\n\ | |
308 | mfpr r1,r0\n" }, | |
309 | ||
310 | { "12,_mtpr\n", | |
311 | " movl (sp)+,r1\n\ | |
312 | movl (sp)+,r0\n\ | |
313 | mtpr r0,r1\n" }, | |
314 | ||
315 | #ifdef notdef | |
316 | { "8,_uncache\n", | |
317 | " movl (sp)+,r1\n\ | |
318 | mtpr r1,$0x1c\n" }, | |
319 | #endif | |
320 | ||
321 | { "4,_setsoftclock\n", | |
322 | " mtpr $0x8,$0x10\n" }, | |
323 | ||
324 | { "8,_fuibyte\n", | |
325 | " callf $8,_fubyte\n" }, | |
326 | ||
327 | { "8,_fuiword\n", | |
328 | " callf $8,_fuword\n" }, | |
329 | ||
330 | { "12,_suibyte\n", | |
331 | " callf $12,_subyte\n" }, | |
332 | ||
333 | { "12,_suiword\n", | |
334 | " callf $12,_suword\n" }, | |
335 | ||
336 | { "8,_setjmp\n", | |
337 | " movl (sp)+,r1\n\ | |
338 | clrl r0\n\ | |
339 | movab (fp),(r1)\n\ | |
340 | addl2 $4,r1\n\ | |
341 | movab 1(pc),(r1)\n" }, | |
342 | ||
343 | { "8,_ffs\n", | |
344 | " movl (sp)+,r1\n\ | |
345 | ffs r1,r0\n\ | |
346 | bgeq 1f\n\ | |
347 | mnegl $1,r0\n\ | |
348 | 1:\n\ | |
349 | incl r0\n" }, | |
350 | ||
351 | { "12,__insque\n", | |
352 | " movl (sp)+,r0\n\ | |
353 | movl (sp)+,r1\n\ | |
354 | insque (r0),(r1)\n" }, | |
355 | ||
356 | { "8,__remque\n", | |
357 | " movl (sp)+,r1\n\ | |
358 | remque (r1)\n" }, | |
359 | ||
360 | { "12,_imin\n", | |
361 | " movl (sp)+,r0\n\ | |
362 | movl (sp)+,r1\n\ | |
363 | cmpl r0,r1\n\ | |
364 | bleq 1f\n\ | |
365 | movl r1,r0\n\ | |
366 | 1:\n" }, | |
367 | ||
368 | { "12,_imax\n", | |
369 | " movl (sp)+,r0\n\ | |
370 | movl (sp)+,r1\n\ | |
371 | cmpl r0,r1\n\ | |
372 | bgeq 1f\n\ | |
373 | movl r1,r0\n\ | |
374 | 1:\n" }, | |
375 | ||
376 | { "12,_min\n", | |
377 | " movl (sp)+,r0\n\ | |
378 | movl (sp)+,r1\n\ | |
379 | cmpl r0,r1\n\ | |
380 | blequ 1f\n\ | |
381 | movl r1,r0\n\ | |
382 | 1:\n" }, | |
383 | ||
384 | { "12,_max\n", | |
385 | " movl (sp)+,r0\n\ | |
386 | movl (sp)+,r1\n\ | |
387 | cmpl r0,r1\n\ | |
388 | bgequ 1f\n\ | |
389 | movl r1,r0\n\ | |
390 | 1:\n" }, | |
391 | ||
392 | { "12,__movow\n", | |
393 | " movl (sp)+,r1\n\ | |
394 | movl (sp)+,r0\n\ | |
395 | movow r0,(r1)\n" }, | |
396 | ||
397 | { "12,__movob\n", | |
398 | " movl (sp)+,r1\n\ | |
399 | movl (sp)+,r0\n\ | |
400 | movob r0,(r1)\n" }, | |
401 | #endif | |
402 | ||
403 | #if defined(mc68000) | |
f566e19b | 404 | /* someday... */ |
bd1e6d2e | 405 | #endif |
f566e19b SL |
406 | |
407 | { "", "" } | |
408 | }; |