[unix-history] / usr / src / sys / vax / uba / ubavar.h

/*	ubavar.h	4.4	%G%	*/

/*
 * Unibus adapter
 */

#define	UBA0		0x80060000	/* sys virt i/o for UBA 0 */
#define	UBA0_DEV (UBA0+0x2000-0160000)	/* sys virt of device regs */
#define	UNIBASE 0760000	 		/* UNIBUS phys base of i/o reg's */

#if VAX==780
#define	PHYSUBA0	0x20006000
#define	PHYSUDEV0	0x20100000
#else
#define	PHYSUBA0	0xf30000
#define	PHYSUDEV0	0xfc0000
#endif
#define	PHYSUMEM0	(PHYSUDEV0+0x3e000)
#define	PHYSUMEM	PHYSUMEM0
#define	PHYSUDEVSZ	0x40000

#if VAX==780
/* UBA Configuration Register, CNFGR */
#define	PARFLT		0x80000000	/* SBI Parity Fault */
#define	WSQFLT		0x40000000	/* SBI Write Sequence Fault */
#define	URDFLT		0x20000000	/* SBI Unexpected Read Fault */
#define	ISQFLT		0x10000000	/* SBI Interlock Sequence Fault */
#define	MXTFLT		0x8000000	/* SBI Multiple Transmitter Fault */
#define	XMTFLT		0x4000000	/* UBA is transmit faulter */
#define	ADPDN		0x800000	/* Adapter Power Down */
#define	ADPUP		0x400000	/* Adapter Power Up */
#define	UBINIT		0x40000		/* UNIBUS INIT is asserted */
#define	UBPDN		0x20000		/* UNIBUS Power Down */
#define	UBIC		0x10000		/* UNIBUS Initialization */
					/* UNIBUS Ready */
#define	UBACOD		0xff		/* UBA Code bits */
 
/* UBA Control Register, UBACR */
 
#define	MRD16		0x40000000	/* Map Reg Disable Bit 4 */
#define	MRD8		0x20000000	/* Map Reg Disable Bit 3 */
#define	MRD4		0x10000000	/* Map Reg Disable Bit 2 */
#define	MRD2		0x8000000	/* Map Reg Disable Bit 1 */
#define	MRD1		0x4000000	/* Map Reg Disable Bit 0 */
#define	IFS		0x40	  	/* Interrupt Field Switch */
#define	BRIE		0x20	  	/* BR Interrupt Enable */
#define	USEFIE		0x10	  	/* UNIBUS to SBI Error Field IE */
#define	SUEFIE		0x8	  	/* SBI to UNIBUS Error Field IE */
#define	CNFIE		0x4	  	/* Configuration IE */
#define	UPF		0x2	  	/* UNIBUS Power Fail */
#define	ADINIT		0x1	  	/* Adapter Init */
 
/* UBA Status Register, UASR */
#define	BR7FULL		0x8000000	/* BR7 Receive Vector Rg Full */
#define	BR6FULL		0x4000000	/* BR6 Receive Vector Reg Full */
#define	BR5FULL		0x2000000	/* BR5 Receive Vector Reg Full */
#define	BR4FULL		0x1000000	/* BR4 Receive Vector Reg Full */
#define	RDTO		0x400		/* UNIBUS to SBI Read Data Timeout */
#define	RDS		0x200		/* Read Data Substitute */
#define	CRD		0x100		/* Corrected Read Data */
#define	CXTER		0x80		/* Command Transmit Error */
#define	CXTMO		0x40		/* Command Transmit Timeout */
#define	DPPE		0x20		/* Data Path Parity Error */
#define	IVMR		0x10		/* Invalid Map Register */
#define	MRPF		0x8		/* Map Register Parity Failure */
#define	LEB		0x4		/* Lost Error */
#define	UBSTO		0x2		/* UNIBUS Select Timeout */
#define	UBSSTO		0x1		/* UNIBUS Slave Sync Timeout */
 
/* Failed Map Entry Register, FMER */
 
#define	FMRN		0x1ff		/* Failed Map Reg. No. Field */
 
/* Failed UNIBUS Address Register, FUBAR */
#define	FUA		0xffff		/* Failed UNIBUS Address Field */
 
/* BR Receive Vector register, BRRVR */
#define	AIRI		0x80000000	/* Adapter Interrupt Request */
#define	DIV		0xffff		/* Device Interrupt Vector Field */
#endif
 
/* Data Path Register, DPR */
#define	BNE		0x80000000	/* Buffer Not Empty - Purge */
#define	BTE		0x40000000	/* Buffer Transfer Error */
#define	DPF		0x20000000	/* DP Function (RO) */
#define	BS		0x7f0000	/* Buffer State Field */
#define	BUBA		0xffff		/* Buffered UNIBUS Address */
 
/* Map Register, MR */
#define	MRV		0x80000000	/* Map Register Valid */
#define	BO		0x2000000	/* Byte Offset Bit */
#define	DPDB		0x1e00000	/* Data Path Designator Field */
#define	SBIPFN		0xfffff		/* SBI Page Address Field */

/*
 * Unibus maps
 */
#if VAX==780
#define	NUBABDP	15
#else
#define	NUBABDP	3
#endif

#ifdef	KERNEL
#define	UAMSIZ 50

struct	map ubamap[UAMSIZ];
char	bdpwant;		/* someone is waiting for buffered data path */ 
struct	map bdpmap[NUBABDP];
char	umrwant;		/* ... for unibus map registers */
#endif

/*
 * UBA registers
 */

struct uba_regs
{
	int	uba_cnfgr;
	int	uba_cr;
	int	uba_sr;
	int	uba_dcr;
	int	uba_fmer;
	int	uba_fubar;
	int	pad1[2];
	int	uba_brsvr[4];
	int	uba_brrvr[4];
	int	uba_dpr[16];
	int	pad2[480];
	struct	pte uba_map[496];
};

union	ub_info {
	struct ub_Info {
	unsigned int	Ub_off:18,
			Ub_npf:10,
			Ub_bdp:4;
	} ub_I;
	int	ub_word;
};

#define	ub_off	ub_I.Ub_off
#define	ub_npf	ub_I.Ub_npf
#define	ub_bdp	ub_I.Ub_bdp
Commit	Line	Data
defc826e	1	/* ubavar.h 4.4 %G% */
1cb3d36a BJ	2
	3	/*
	4	* Unibus adapter
	5	*/
	6
eee6d23b	7	#define UBA0 0x80060000 /* sys virt i/o for UBA 0 */
1cb3d36a	8	#define UBA0_DEV (UBA0+0x2000-0160000) /* sys virt of device regs */
1cb3d36a BJ	9	#define UNIBASE 0760000 /* UNIBUS phys base of i/o reg's */
1cb3d36a BJ	10
a386310c BJ	11	#if VAX==780
a386310c BJ	12	#define PHYSUBA0 0x20006000
defc826e	13	#define PHYSUDEV0 0x20100000
a386310c BJ	14	#else
a386310c BJ	15	#define PHYSUBA0 0xf30000
defc826e	16	#define PHYSUDEV0 0xfc0000
a386310c	17	#endif
defc826e BJ	18	#define PHYSUMEM0 (PHYSUDEV0+0x3e000)
	19	#define PHYSUMEM PHYSUMEM0
	20	#define PHYSUDEVSZ 0x40000
a386310c	21
a5523103	22	#if VAX==780
1cb3d36a BJ	23	/* UBA Configuration Register, CNFGR */
	24	#define PARFLT 0x80000000 /* SBI Parity Fault */
	25	#define WSQFLT 0x40000000 /* SBI Write Sequence Fault */
	26	#define URDFLT 0x20000000 /* SBI Unexpected Read Fault */
	27	#define ISQFLT 0x10000000 /* SBI Interlock Sequence Fault */
	28	#define MXTFLT 0x8000000 /* SBI Multiple Transmitter Fault */
	29	#define XMTFLT 0x4000000 /* UBA is transmit faulter */
	30	#define ADPDN 0x800000 /* Adapter Power Down */
	31	#define ADPUP 0x400000 /* Adapter Power Up */
	32	#define UBINIT 0x40000 /* UNIBUS INIT is asserted */
	33	#define UBPDN 0x20000 /* UNIBUS Power Down */
	34	#define UBIC 0x10000 /* UNIBUS Initialization */
	35	/* UNIBUS Ready */
	36	#define UBACOD 0xff /* UBA Code bits */
	37
	38	/* UBA Control Register, UBACR */
	39
	40	#define MRD16 0x40000000 /* Map Reg Disable Bit 4 */
	41	#define MRD8 0x20000000 /* Map Reg Disable Bit 3 */
	42	#define MRD4 0x10000000 /* Map Reg Disable Bit 2 */
	43	#define MRD2 0x8000000 /* Map Reg Disable Bit 1 */
	44	#define MRD1 0x4000000 /* Map Reg Disable Bit 0 */
	45	#define IFS 0x40 /* Interrupt Field Switch */
	46	#define BRIE 0x20 /* BR Interrupt Enable */
	47	#define USEFIE 0x10 /* UNIBUS to SBI Error Field IE */
	48	#define SUEFIE 0x8 /* SBI to UNIBUS Error Field IE */
	49	#define CNFIE 0x4 /* Configuration IE */
	50	#define UPF 0x2 /* UNIBUS Power Fail */
	51	#define ADINIT 0x1 /* Adapter Init */
	52
	53	/* UBA Status Register, UASR */
	54	#define BR7FULL 0x8000000 /* BR7 Receive Vector Rg Full */
	55	#define BR6FULL 0x4000000 /* BR6 Receive Vector Reg Full */
	56	#define BR5FULL 0x2000000 /* BR5 Receive Vector Reg Full */
	57	#define BR4FULL 0x1000000 /* BR4 Receive Vector Reg Full */
	58	#define RDTO 0x400 /* UNIBUS to SBI Read Data Timeout */
	59	#define RDS 0x200 /* Read Data Substitute */
	60	#define CRD 0x100 /* Corrected Read Data */
	61	#define CXTER 0x80 /* Command Transmit Error */
	62	#define CXTMO 0x40 /* Command Transmit Timeout */
	63	#define DPPE 0x20 /* Data Path Parity Error */
	64	#define IVMR 0x10 /* Invalid Map Register */
	65	#define MRPF 0x8 /* Map Register Parity Failure */
	66	#define LEB 0x4 /* Lost Error */
	67	#define UBSTO 0x2 /* UNIBUS Select Timeout */
	68	#define UBSSTO 0x1 /* UNIBUS Slave Sync Timeout */
	69
	70	/* Failed Map Entry Register, FMER */
	71
	72	#define FMRN 0x1ff /* Failed Map Reg. No. Field */
	73
	74	/* Failed UNIBUS Address Register, FUBAR */
	75	#define FUA 0xffff /* Failed UNIBUS Address Field */
	76
	77	/* BR Receive Vector register, BRRVR */
	78	#define AIRI 0x80000000 /* Adapter Interrupt Request */
	79	#define DIV 0xffff /* Device Interrupt Vector Field */
a5523103	80	#endif
1cb3d36a BJ	81
	82	/* Data Path Register, DPR */
	83	#define BNE 0x80000000 /* Buffer Not Empty - Purge */
	84	#define BTE 0x40000000 /* Buffer Transfer Error */
	85	#define DPF 0x20000000 /* DP Function (RO) */
	86	#define BS 0x7f0000 /* Buffer State Field */
	87	#define BUBA 0xffff /* Buffered UNIBUS Address */
	88
	89	/* Map Register, MR */
	90	#define MRV 0x80000000 /* Map Register Valid */
1e28ba7e BJ	91	#define BO 0x2000000 /* Byte Offset Bit */
	92	#define DPDB 0x1e00000 /* Data Path Designator Field */
	93	#define SBIPFN 0xfffff /* SBI Page Address Field */
1cb3d36a BJ	94
	95	/*
	96	* Unibus maps
	97	*/
a5523103 BJ	98	#if VAX==780
	99	#define NUBABDP 15
	100	#else
	101	#define NUBABDP 3
	102	#endif
	103
defc826e BJ	104	#ifdef KERNEL
	105	#define UAMSIZ 50
	106
	107	struct map ubamap[UAMSIZ];
	108	char bdpwant; /* someone is waiting for buffered data path */
a5523103	109	struct map bdpmap[NUBABDP];
1cb3d36a BJ	110	char umrwant; /* ... for unibus map registers */
	111	#endif
	112
	113	/*
	114	* UBA registers
	115	*/
	116
	117	struct uba_regs
	118	{
	119	int uba_cnfgr;
	120	int uba_cr;
	121	int uba_sr;
	122	int uba_dcr;
	123	int uba_fmer;
	124	int uba_fubar;
	125	int pad1[2];
	126	int uba_brsvr[4];
	127	int uba_brrvr[4];
	128	int uba_dpr[16];
	129	int pad2[480];
	130	struct pte uba_map[496];
	131	};
466a1b4c BJ	132
	133	union ub_info {
	134	struct ub_Info {
	135	unsigned int Ub_off:18,
	136	Ub_npf:10,
	137	Ub_bdp:4;
	138	} ub_I;
	139	int ub_word;
	140	};
	141
	142	#define ub_off ub_I.Ub_off
	143	#define ub_npf ub_I.Ub_npf
	144	#define ub_bdp ub_I.Ub_bdp