Commit | Line | Data |
---|---|---|
1383b055 CT |
1 | /* |
2 | * Copyright (c) 1992 The Regents of the University of California. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This software was developed by the Computer Systems Engineering group | |
6 | * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and | |
7 | * contributed to Berkeley. | |
8 | * | |
9 | * %sccs.include.redist.c% | |
10 | * | |
11 | * @(#)bwtworeg.h 7.1 (Berkeley) %G% | |
12 | * | |
13 | * from: $Header: bwtworeg.h,v 1.3 92/06/17 06:59:30 torek Exp $ | |
14 | */ | |
15 | ||
16 | /* | |
17 | * bwtwo display registers. | |
18 | * | |
19 | * The registers start at offset 0x400000 and repeat every 32 bytes | |
20 | * (presumably only the low order address lines are decoded). Video RAM | |
21 | * starts at offset 0x800000. We use separate pointers to each so that | |
22 | * the sparc addressing modes work well. | |
23 | */ | |
24 | struct bwtworeg { | |
25 | /* | |
26 | * The xxx0 range is all 0xff on my IPC but causes a screen glitch | |
27 | * on my SS1+, so it must do *some*thing... the xxx1 range is full | |
28 | * of values but I do not know what they are. bw_ctl changes for | |
29 | * a blanked screen. | |
30 | */ | |
31 | char bw_xxx0[16]; | |
32 | u_char bw_ctl; /* contains video enable */ | |
33 | char bw_xxx1[15]; | |
34 | }; | |
35 | ||
36 | /* bits in bw_ctl */ | |
37 | #define CTL_VE 0x40 /* video enable */ | |
38 | ||
39 | /* offsets */ | |
40 | #define BWREG_ID 0 | |
41 | #define BWREG_REG 0x400000 | |
42 | #define BWREG_MEM 0x800000 | |
43 | ||
44 | /* same, but for gdb */ | |
45 | struct bwtwo_all { | |
46 | long ba_id; /* ID = 0xfe010104 on my IPC */ | |
47 | char ba_xxx0[0x400000-4]; | |
48 | struct bwtworeg ba_reg; /* control registers */ | |
49 | char ba_xxx1[0x400000-32]; | |
50 | char ba_ram[4096]; /* actually larger */ | |
51 | }; |