Commit | Line | Data |
---|---|---|
385caced C |
1 | /* if_ecreg.h 4.3 82/07/21 */ |
2 | ||
3 | /* | |
4 | * 3Com Ethernet controller registers. | |
5 | */ | |
6 | struct ecdevice { | |
7 | short ec_rcr; /* Receive Control Register */ | |
8 | short ec_xcr; /* Transmit Control Register */ | |
9 | }; | |
10 | ||
11 | /* | |
12 | * Control and status bits -- rcr | |
13 | */ | |
14 | #define EC_SPIE 0x8000 /* set parity interrupt enable */ | |
15 | #define EC_ASTEP 0x4000 /* increment address counter */ | |
16 | #define EC_AROM 0x2000 /* 1: Use address ROM, 0: use RAM */ | |
17 | #define EC_PE 0x2000 /* Parity error */ | |
18 | #define EC_AWCLK 0x1000 /* address write clock bit */ | |
19 | #define EC_PIE 0x1000 /* Parity interrupt enable (read) */ | |
20 | #define EC_ADATA 0x0f00 /* address/filtering */ | |
21 | #define EC_RDONE 0x0080 /* receive done */ | |
22 | #define EC_MDISAB 0x0080 /* memory disable */ | |
23 | #define EC_RINTEN 0x0040 /* receive interrupt enable */ | |
24 | #define EC_RCLR 0x0020 /* clear RDONE bit */ | |
25 | #define EC_RWBN 0x0010 /* submit buffer for receive */ | |
26 | #define EC_RBN 0x000f /* buffer number */ | |
27 | ||
28 | #define EC_RBITS "\10\16PE\15PIE\10RDONE\7RINTEN" | |
29 | ||
30 | /* | |
31 | * Control and status bits -- xcr | |
32 | */ | |
33 | #define EC_JAM 0x8000 /* collision dectected */ | |
34 | #define EC_JINTEN 0x4000 /* collision interrupt enable */ | |
35 | #define EC_JCLR 0x2000 /* clear collision detect */ | |
36 | #define EC_UECLR 0x0100 /* reset controller */ | |
37 | #define EC_XDONE 0x0080 /* transmit done */ | |
38 | #define EC_XINTEN 0x0040 /* transmit interrupt enable */ | |
39 | #define EC_XCLR 0x0020 /* clear XDONE bit */ | |
40 | #define EC_XWBN 0x0010 /* submit buffer for transmit */ | |
41 | #define EC_XBN 0x000f /* buffer number */ | |
42 | ||
43 | #define EC_XBITS "\10\20JAM\17JINTEN\10XDONE\7XINTEN" | |
44 | ||
45 | /* | |
46 | * Useful combinations | |
47 | */ | |
48 | #define EC_READ (EC_AROM|0x600|EC_RINTEN|EC_RWBN) | |
49 | #define EC_WRITE (EC_JINTEN|EC_XINTEN|EC_XWBN) | |
50 | #define EC_CLEAR (EC_JINTEN|EC_XINTEN|EC_JCLR) | |
51 | ||
52 | /* | |
53 | * Buffer number definitions | |
54 | */ | |
55 | #define ECTBF 0 /* Buffer for transmit */ | |
56 | #define ECRLBF 1 /* First buffer for receive */ | |
57 | #define ECRHBF 15 /* Last buffer for receive */ | |
58 | ||
59 | #define ECRDOFF 528 /* Packet offset in read buffer */ |