Commit | Line | Data |
---|---|---|
c3e410c8 C |
1 | /* upreg.h 4.5 81/04/02 */ |
2 | ||
3 | /* | |
4 | * Unibus rm emulation via sc21: | |
5 | * registers and bits. | |
6 | */ | |
7 | ||
8 | struct updevice | |
9 | { | |
10 | u_short upcs1; /* control and status register 1 */ | |
11 | short upwc; /* word count register */ | |
12 | u_short upba; /* UNIBUS address register */ | |
13 | u_short upda; /* desired address register */ | |
14 | u_short upcs2; /* control and status register 2 */ | |
15 | u_short upds; /* drive Status */ | |
16 | u_short uper1; /* error register 1 */ | |
17 | u_short upas; /* attention summary */ | |
18 | u_short upla; /* look ahead */ | |
19 | u_short updb; /* data buffer */ | |
20 | u_short upmr; /* maintenance */ | |
21 | u_short updt; /* drive type */ | |
22 | u_short upsn; /* serial number */ | |
23 | u_short upof; /* offset register */ | |
24 | u_short updc; /* desired cylinder address register */ | |
25 | u_short uphr; /* holding register */ | |
26 | u_short upmr2; /* maintenance register 2 */ | |
27 | u_short uper2; /* error register 2 */ | |
28 | u_short upec1; /* burst error bit position */ | |
29 | u_short upec2; /* burst error bit pattern */ | |
30 | }; | |
31 | ||
32 | /* Other bits of upcs1 */ | |
33 | #define UP_SC 0100000 /* special condition */ | |
34 | #define UP_TRE 0040000 /* transfer error */ | |
35 | #define UP_PSEL 0010000 /* port select */ | |
36 | #define UP_DVA 0004000 /* drive available */ | |
37 | /* bits 8 and 9 are the extended address bits */ | |
38 | #define UP_RDY 0000200 /* controller ready */ | |
39 | #define UP_IE 0000100 /* interrupt enable */ | |
40 | /* bits 5-1 are the command */ | |
41 | #define UP_GO 0000001 | |
42 | ||
43 | /* commands */ | |
44 | #define UP_NOP 000 | |
45 | #define UP_SEEK 004 /* seek */ | |
46 | #define UP_RECAL 006 /* recalibrate */ | |
47 | #define UP_DCLR 010 /* drive clear */ | |
48 | #define UP_RELEASE 012 /* release */ | |
49 | #define UP_OFFSET 014 /* offset */ | |
50 | #define UP_RTC 016 /* return to center-line */ | |
51 | #define UP_PRESET 020 /* read-in preset */ | |
52 | #define UP_PACK 022 /* pack acknowledge */ | |
53 | #define UP_DMABAND 024 /* dma bandwidth set */ | |
54 | #define UP_SEARCH 030 /* search */ | |
55 | #define UP_WCDATA 050 /* write check data */ | |
56 | #define UP_WCHDR 052 /* write check header and data */ | |
57 | #define UP_WCOM 060 /* write */ | |
58 | #define UP_WHDR 062 /* write header and data */ | |
59 | #define UP_RCOM 070 /* read data */ | |
60 | #define UP_RHDR 072 /* read header and data */ | |
61 | #define UP_BOOT 074 /* boot */ | |
62 | #define UP_FORMAT 076 /* format */ | |
63 | ||
64 | /* upcs2 */ | |
65 | #define UPCS2_DLT 0100000 /* data late */ | |
66 | #define UPCS2_WCE 0040000 /* write check error */ | |
67 | #define UPCS2_UPE 0020000 /* UNIBUS parity error */ | |
68 | #define UPCS2_NED 0010000 /* nonexistent drive */ | |
69 | #define UPCS2_NEM 0004000 /* nonexistent memory */ | |
70 | #define UPCS2_PGE 0002000 /* programming error */ | |
71 | #define UPCS2_MXF 0001000 /* missed transfer */ | |
72 | #define UPCS2_MDPE 0000400 /* massbus data parity error (0) */ | |
73 | #define UPCS2_OR 0000200 /* output ready */ | |
74 | #define UPCS2_IR 0000100 /* input ready */ | |
75 | #define UPCS2_CLR 0000040 /* controller clear */ | |
76 | #define UPCS2_PAT 0000020 /* parity test */ | |
77 | #define UPCS2_BAI 0000010 /* address increment inhibit */ | |
78 | /* bits 0-2 are drive select */ | |
79 | ||
80 | #define UPCS2_BITS \ | |
81 | "\10\20DLT\17WCE\16UPE\15NED\14NEM\13PGE\12MXF\11MDPE\ | |
82 | \10OR\7IR\6CLR\5PAT\4BAI" | |
83 | ||
84 | /* upds */ | |
85 | #define UPDS_ATA 0100000 /* attention active */ | |
86 | #define UPDS_ERR 0040000 /* composite drive error */ | |
87 | #define UPDS_PIP 0020000 /* positioning in progress */ | |
88 | #define UPDS_MOL 0010000 /* medium on line */ | |
89 | #define UPDS_WRL 0004000 /* write locked */ | |
90 | #define UPDS_LST 0002000 /* last sector transferred */ | |
91 | #define UPDS_PGM 0001000 /* programmable */ | |
92 | #define UPDS_DPR 0000400 /* drive present */ | |
93 | #define UPDS_DRY 0000200 /* drive ready */ | |
94 | #define UPDS_VV 0000100 /* volume valid */ | |
95 | /* bits 1-5 are spare */ | |
96 | #define UPDS_OM 0000001 /* offset mode */ | |
97 | ||
98 | #define UPDS_DREADY (UPDS_DPR|UPDS_DRY|UPDS_MOL|UPDS_VV) | |
99 | ||
100 | #define UPDS_BITS \ | |
101 | "\10\20ATA\17ERR\16PIP\15MOL\14WRL\13LST\12PGM\11DPR\10DRY\7VV\1OM" | |
102 | ||
103 | /* uper1 */ | |
104 | #define UPER1_DCK 0100000 /* data check */ | |
105 | #define UPER1_UNS 0040000 /* drive unsafe */ | |
106 | #define UPER1_OPI 0020000 /* operation incomplete */ | |
107 | #define UPER1_DTE 0010000 /* drive timing error */ | |
108 | #define UPER1_WLE 0004000 /* write lock error */ | |
109 | #define UPER1_IAE 0002000 /* invalid address error */ | |
110 | #define UPER1_AOE 0001000 /* address overflow error */ | |
111 | #define UPER1_HCRC 0000400 /* header crc error */ | |
112 | #define UPER1_HCE 0000200 /* header compare error */ | |
113 | #define UPER1_ECH 0000100 /* ecc hard error */ | |
114 | #define UPER1_WCF 0000040 /* write clock fail (0) */ | |
115 | #define UPER1_FER 0000020 /* format error */ | |
116 | #define UPER1_PAR 0000010 /* parity error */ | |
117 | #define UPER1_RMR 0000004 /* register modification refused */ | |
118 | #define UPER1_ILR 0000002 /* illegal register */ | |
119 | #define UPER1_ILF 0000001 /* illegal function */ | |
120 | ||
121 | #define UPER1_BITS \ | |
122 | "\10\20DCK\17UNS\16OPI\15DTE\14WLE\13IAE\12AOE\11HCRC\10HCE\ | |
123 | \7ECH\6WCF\5FER\4PAR\3RMR\2ILR\1ILF" | |
124 | ||
125 | /* uphr */ | |
126 | /* write these int uphr and then read back values */ | |
127 | #define UPHR_MAXCYL 0100027 /* max cyl address */ | |
128 | #define UPHR_MAXTRAK 0100030 /* max track address */ | |
129 | #define UPHR_MAXSECT 0100031 /* max sector address */ | |
130 | ||
131 | /* uper2 */ | |
132 | #define UPER2_BSE 0100000 /* bad sector error */ | |
133 | #define UPER2_SKI 0040000 /* seek incomplete */ | |
134 | #define UPER2_OPE 0020000 /* operator plug error */ | |
135 | #define UPER2_IVC 0010000 /* invalid command */ | |
136 | #define UPER2_LSC 0004000 /* loss of sector clock */ | |
137 | #define UPER2_LBC 0002000 /* loss of bit clock */ | |
138 | #define UPER2_MDS 0001000 /* multiple drive select */ | |
139 | #define UPER2_DCU 0000400 /* dc power unsafe */ | |
140 | #define UPER2_DVC 0000200 /* device check */ | |
141 | #define UPER2_ACU 0000100 /* ac power unsafe */ | |
142 | /* bits 5 and 4 are spare */ | |
143 | #define UPER2_DPE 0000010 /* data parity error (0) */ | |
144 | /* bits 2-0 are spare */ | |
145 | ||
146 | #define UPER2_BITS \ | |
147 | "\10\20BSE\17SKI\16OPE\15IVC\14LSC\13LBC\12MDS\11DCU\10DVC\7ACU\4DPE" | |
148 | ||
149 | /* upof */ | |
150 | #define UPOF_FMT22 0010000 /* 16 bit format */ | |
151 | #define UPOF_ECI 0004000 /* ecc inhibit */ | |
152 | #define UPOF_HCI 0002000 /* header compare inhibit */ | |
153 | ||
154 | /* THE SC21 ACTUALLY JUST IMPLEMENTS ADVANCE/RETARD... */ | |
155 | #define UPOF_P400 0020 /* +400 uinches */ | |
156 | #define UPOF_M400 0220 /* -400 uinches */ | |
157 | #define UPOF_P800 0040 /* +800 uinches */ | |
158 | #define UPOF_M800 0240 /* -800 uinches */ | |
159 | #define UPOF_P1200 0060 /* +1200 uinches */ | |
160 | #define UPOF_M1200 0260 /* -1200 uinches */ |