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d7136515 RG |
1 | /* |
2 | * Isolan AT 4141-0 Ethernet driver header file | |
3 | * Isolink 4110 | |
4 | * | |
5 | * By Paul Richards | |
6 | * | |
7 | * Copyright (C) 1993, Paul Richards. This software may be used, modified, | |
8 | * copied, distributed, and sold, in both source and binary form provided | |
9 | * that the above copyright and these terms are retained. Under no | |
10 | * circumstances is the author responsible for the proper functioning | |
11 | * of this software, nor does the author assume any responsibility | |
12 | * for damages incurred with its use. | |
13 | * | |
c8685ddd | 14 | * $Id: if_isreg.h,v 1.3 1993/10/24 04:27:00 paul Exp $ |
d7136515 RG |
15 | */ |
16 | ||
6b96e31f PR |
17 | /* |
18 | * Initialize multicast address hashing registers to accept | |
19 | * all multicasts (only used when in promiscuous mode) | |
20 | */ | |
21 | #if NBPFILTER > 0 | |
22 | #define MULTI_INIT_ADDR 0xff | |
23 | #else | |
24 | #define MULTI_INIT_ADDR 0 | |
25 | #endif | |
26 | ||
15637ed4 RG |
27 | /* Declarations specific to this driver */ |
28 | #define NTBUF 2 | |
29 | #define TLEN 1 | |
30 | #define NRBUF 8 | |
31 | #define RLEN 3 | |
32 | #define BUFSIZE 1518 | |
c8685ddd PR |
33 | #define BICC_RDP 0xc |
34 | #define BICC_RAP 0xe | |
35 | #define NE2100_RDP 0x10 | |
36 | #define NE2100_RAP 0x12 | |
37 | ||
38 | /* Board types */ | |
39 | #define BICC 1 | |
40 | #define NE2100 2 | |
41 | ||
42 | /* Am7990 or Am79960 */ | |
43 | #define LANCE 1 | |
44 | #define LANCE_MASK 0x07 | |
45 | #define PCnet_ISA 2 | |
46 | #define PCnet_ISA_MASK 0x0 | |
47 | ||
15637ed4 RG |
48 | |
49 | /* Control and status register 0 flags */ | |
50 | ||
51 | #define ERR 0x8000 | |
52 | #define BABL 0x4000 | |
53 | #define CERR 0x2000 | |
54 | #define MISS 0x1000 | |
55 | #define MERR 0x0800 | |
56 | #define RINT 0x0400 | |
57 | #define TINT 0x0200 | |
58 | #define IDON 0x0100 | |
59 | #define INTR 0x0080 | |
60 | #define INEA 0x0040 | |
61 | #define RXON 0x0020 | |
62 | #define TXON 0x0010 | |
63 | #define TDMD 0x0008 | |
64 | #define STOP 0x0004 | |
65 | #define STRT 0x0002 | |
66 | #define INIT 0x0001 | |
67 | ||
68 | /* Coontrol and status register 3 flags */ | |
69 | ||
70 | #define BSWP 0x0004 | |
71 | #define ACON 0x0002 | |
72 | #define BCON 0x0001 | |
73 | ||
74 | /* Initialisation block (must be on word boundary) */ | |
75 | ||
76 | struct init_block { | |
77 | u_short mode; /* Mode register */ | |
78 | u_char padr[6]; /* Ethernet address */ | |
79 | u_char ladrf[8]; /* Logical address filter (multicast) */ | |
80 | u_short rdra; /* Low order pointer to receive ring */ | |
81 | u_short rlen; /* High order pointer and no. rings */ | |
82 | u_short tdra; /* Low order pointer to transmit ring */ | |
83 | u_short tlen; /* High order pointer and no rings */ | |
84 | }; | |
85 | ||
86 | /* Mode settings */ | |
87 | ||
88 | #define PROM 0x8000 /* Promiscuous */ | |
89 | #define INTL 0x0040 /* Internal loopback */ | |
90 | #define DRTY 0x0020 /* Disable retry */ | |
91 | #define COLL 0x0010 /* Force collision */ | |
92 | #define DTCR 0x0008 /* Disable transmit crc */ | |
93 | #define LOOP 0x0004 /* Loop back */ | |
94 | #define DTX 0x0002 /* Disable transmitter */ | |
95 | #define DRX 0x0001 /* Disable receiver */ | |
96 | ||
97 | /* Message descriptor structure */ | |
98 | ||
99 | struct mds { | |
100 | u_short addr; | |
101 | u_short flags; | |
102 | u_short bcnt; | |
103 | u_short mcnt; | |
104 | }; | |
105 | ||
106 | /* Receive ring status flags */ | |
107 | ||
108 | #define OWN 0x8000 /* Owner bit, 0=host, 1=Lance */ | |
109 | #define MDERR 0x4000 /* Error */ | |
110 | #define FRAM 0x2000 /* Framing error error */ | |
111 | #define OFLO 0x1000 /* Silo overflow */ | |
112 | #define CRC 0x0800 /* CRC error */ | |
113 | #define RBUFF 0x0400 /* Buffer error */ | |
114 | #define STP 0x0200 /* Start of packet */ | |
115 | #define ENP 0x0100 /* End of packet */ | |
116 | ||
117 | /* Transmit ring flags */ | |
118 | ||
119 | #define MORE 0x1000 /* More than 1 retry */ | |
120 | #define ONE 0x0800 /* One retry */ | |
121 | #define DEF 0x0400 /* Deferred transmit */ | |
122 | ||
123 | /* Transmit errors */ | |
124 | ||
125 | #define TBUFF 0x8000 /* Buffer error */ | |
126 | #define UFLO 0x4000 /* Silo underflow */ | |
127 | #define LCOL 0x1000 /* Late collision */ | |
128 | #define LCAR 0x0800 /* Loss of carrier */ | |
129 | #define RTRY 0x0400 /* Tried 16 times */ |