projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| 60f56dfc KM |
1 | /* |
| 2 | * Copyright (c) 1988 University of Utah. | |
| 3 | * Copyright (c) 1990 The Regents of the University of California. | |
| 4 | * All rights reserved. | |
| 5 | * | |
| 6 | * This code is derived from software contributed to Berkeley by | |
| 7 | * the Systems Programming Group of the University of Utah Computer | |
| 8 | * Science Department. | |
| 9 | * | |
| 10 | * %sccs.include.redist.c% | |
| 11 | * | |
| 2f63f82e | 12 | * from: Utah $Hdr: grf_rbreg.h 1.1 90/07/09$ |
| 60f56dfc | 13 | * |
| 2f63f82e | 14 | * @(#)grf_rbreg.h 7.2 (Berkeley) %G% |
| 60f56dfc KM |
15 | */ |
| 16 | ||
| 17 | /* | |
| 18 | * Map of the Renaissance frame buffer controller chip in memory ... | |
| 19 | */ | |
| 20 | ||
| 21 | #define rb_waitbusy(regaddr) \ | |
| 22 | while (((struct rboxfb *)(regaddr))->wbusy & 0x01) DELAY(100) | |
| 23 | ||
| 24 | #define CM1RED ((struct rencm *)(ip->regbase + 0x6400)) | |
| 25 | #define CM1GRN ((struct rencm *)(ip->regbase + 0x6800)) | |
| 26 | #define CM1BLU ((struct rencm *)(ip->regbase + 0x6C00)) | |
| 27 | #define CM2RED ((struct rencm *)(ip->regbase + 0x7400)) | |
| 28 | #define CM2GRN ((struct rencm *)(ip->regbase + 0x7800)) | |
| 29 | #define CM2BLU ((struct rencm *)(ip->regbase + 0x7C00)) | |
| 30 | ||
| 31 | #define vu_char volatile u_char | |
| 32 | #define vu_short volatile u_short | |
| 33 | #define vu_int volatile u_int | |
| 34 | ||
| 35 | struct rencm { | |
| 36 | u_char :8, :8, :8; | |
| 37 | vu_char value; | |
| 38 | }; | |
| 39 | ||
| 40 | struct rboxfb { | |
| 41 | u_char filler1[1]; | |
| 42 | vu_char reset; /* reset register 0x01 */ | |
| 43 | vu_char fb_address; /* frame buffer address 0x02 */ | |
| 44 | vu_char interrupt; /* interrupt register 0x03 */ | |
| 45 | u_char filler1a; | |
| 46 | vu_char fbwmsb; /* frame buffer width MSB 0x05 */ | |
| 47 | u_char filler1b; | |
| 48 | vu_char fbwlsb; /* frame buffer width MSB 0x07 */ | |
| 49 | u_char filler1c; | |
| 50 | vu_char fbhmsb; /* frame buffer height MSB 0x09 */ | |
| 51 | u_char filler1d; | |
| 52 | vu_char fbhlsb; /* frame buffer height MSB 0x0b */ | |
| 53 | u_char filler1e; | |
| 54 | vu_char dwmsb; /* display width MSB 0x0d */ | |
| 55 | u_char filler1f; | |
| 56 | vu_char dwlsb; /* display width MSB 0x0f */ | |
| 57 | u_char filler1g; | |
| 58 | vu_char dhmsb; /* display height MSB 0x11 */ | |
| 59 | u_char filler1h; | |
| 60 | vu_char dhlsb; /* display height MSB 0x13 */ | |
| 61 | u_char filler1i; | |
| 62 | vu_char fbid; /* frame buffer id 0x15 */ | |
| 63 | u_char filler1j[0x47]; | |
| 64 | vu_char fbomsb; /* frame buffer offset MSB 0x5d */ | |
| 65 | u_char filler1k; | |
| 66 | vu_char fbolsb; /* frame buffer offset LSB 0x5f */ | |
| 67 | u_char filler2[16359]; | |
| 68 | vu_char wbusy; /* window mover is active 0x4047 */ | |
| 69 | u_char filler3[0x405b - 0x4048]; | |
| 70 | vu_char scanbusy; /* scan converteris active 0x405B */ | |
| 71 | u_char filler3b[0x4083 - 0x405c]; | |
| 72 | vu_char video_enable; /* drive vid. refresh bus 0x4083 */ | |
| 73 | u_char filler4[3]; | |
| 74 | vu_char display_enable; /* enable the display 0x4087 */ | |
| 75 | u_char filler5[8]; | |
| 76 | vu_int write_enable; /* write enable register 0x4090 */ | |
| 77 | u_char filler6[11]; | |
| 78 | vu_char wmove; /* start window mover 0x409f */ | |
| 79 | u_char filler7[3]; | |
| 80 | vu_char blink; /* blink register 0x40a3 */ | |
| 81 | u_char filler8[15]; | |
| 82 | vu_char fold; /* fold register 0x40b3 */ | |
| 83 | vu_int opwen; /* overlay plane write enable 0x40b4 */ | |
| 84 | u_char filler9[3]; | |
| 85 | vu_char tmode; /* Tile mode size 0x40bb */ | |
| 86 | u_char filler9a[3]; | |
| 87 | vu_char drive; /* drive register 0x40bf */ | |
| 88 | u_char filler10[3]; | |
| 89 | vu_char vdrive; /* vdrive register 0x40c3 */ | |
| 90 | u_char filler10a[0x40cb-0x40c4]; | |
| 91 | vu_char zconfig; /* Z-buffer mode 0x40cb */ | |
| 92 | u_char filler11a[2]; | |
| 93 | vu_short tpatt; /* Transparency pattern 0x40ce */ | |
| 94 | u_char filler11b[3]; | |
| 95 | vu_char dmode; /* dither mode 0x40d3 */ | |
| 96 | u_char filler11c[3]; | |
| 97 | vu_char en_scan; /* enable scan board to DTACK 0x40d7 */ | |
| 98 | u_char filler11d[0x40ef-0x40d8]; | |
| 99 | vu_char rep_rule; /* replacement rule 0x40ef */ | |
| 100 | u_char filler12[2]; | |
| 101 | vu_short source_x; /* source x 0x40f2 */ | |
| 102 | u_char filler13[2]; | |
| 103 | vu_short source_y; /* source y 0x40f6 */ | |
| 104 | u_char filler14[2]; | |
| 105 | vu_short dest_x; /* dest x 0x40fa */ | |
| 106 | u_char filler15[2]; | |
| 107 | vu_short dest_y; /* dest y 0x40fe */ | |
| 108 | u_char filler16[2]; | |
| 109 | vu_short wwidth; /* window width 0x4102 */ | |
| 110 | u_char filler17[2]; | |
| 111 | vu_short wheight; /* window height 0x4106 */ | |
| 112 | u_char filler18[18]; | |
| 113 | vu_short patt_x; /* pattern x 0x411a */ | |
| 114 | u_char filler19[2]; | |
| 115 | vu_short patt_y; /* pattern y 0x411e */ | |
| 116 | u_char filler20[0x8012 - 0x4120]; | |
| 117 | vu_short te_status; /* transform engine status 0x8012 */ | |
| 118 | u_char filler21[0x1ffff-0x8014]; | |
| 119 | }; |