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ba9f5487 WJ |
1 | /* Compute register class preferences for pseudo-registers. |
2 | Copyright (C) 1987, 1988 Free Software Foundation, Inc. | |
3 | ||
4 | This file is part of GNU CC. | |
5 | ||
6 | GNU CC is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 1, or (at your option) | |
9 | any later version. | |
10 | ||
11 | GNU CC is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with GNU CC; see the file COPYING. If not, write to | |
18 | the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ | |
19 | ||
20 | ||
21 | /* This file contains two passes of the compiler: reg_scan and reg_class. | |
22 | It also defines some tables of information about the hardware registers | |
23 | and a function init_reg_sets to initialize the tables. */ | |
24 | ||
25 | #include "config.h" | |
26 | #include "rtl.h" | |
27 | #include "hard-reg-set.h" | |
28 | #include "flags.h" | |
29 | #include "basic-block.h" | |
30 | #include "regs.h" | |
31 | #include "insn-config.h" | |
32 | #include "recog.h" | |
33 | ||
34 | #define max(A,B) ((A) > (B) ? (A) : (B)) | |
35 | #define min(A,B) ((A) < (B) ? (A) : (B)) | |
36 | \f | |
37 | /* Register tables used by many passes. */ | |
38 | ||
39 | /* Indexed by hard register number, contains 1 for registers | |
40 | that are fixed use (stack pointer, pc, frame pointer, etc.). | |
41 | These are the registers that cannot be used to allocate | |
42 | a pseudo reg whose life does not cross calls. */ | |
43 | ||
44 | char fixed_regs[FIRST_PSEUDO_REGISTER]; | |
45 | ||
46 | /* Same info as a HARD_REG_SET. */ | |
47 | ||
48 | HARD_REG_SET fixed_reg_set; | |
49 | ||
50 | /* Data for initializing the above. */ | |
51 | ||
52 | static char initial_fixed_regs[] = FIXED_REGISTERS; | |
53 | ||
54 | /* Indexed by hard register number, contains 1 for registers | |
55 | that are fixed use or are clobbered by function calls. | |
56 | These are the registers that cannot be used to allocate | |
57 | a pseudo reg whose life crosses calls. */ | |
58 | ||
59 | char call_used_regs[FIRST_PSEUDO_REGISTER]; | |
60 | ||
61 | /* Same info as a HARD_REG_SET. */ | |
62 | ||
63 | HARD_REG_SET call_used_reg_set; | |
64 | ||
65 | /* Data for initializing the above. */ | |
66 | ||
67 | static char initial_call_used_regs[] = CALL_USED_REGISTERS; | |
68 | ||
69 | /* Indexed by hard register number, contains 1 for registers that are | |
70 | fixed use -- i.e. in fixed_regs -- or a function value return register | |
71 | or STRUCT_VALUE_REGNUM or STATIC_CHAIN_REGNUM. These are the | |
72 | registers that cannot hold quantities across calls even if we are | |
73 | willing to save and restore them. */ | |
74 | ||
75 | char call_fixed_regs[FIRST_PSEUDO_REGISTER]; | |
76 | ||
77 | /* The same info as a HARD_REG_SET. */ | |
78 | ||
79 | HARD_REG_SET call_fixed_reg_set; | |
80 | ||
81 | /* Indexed by hard register number, contains 1 for registers | |
82 | that are being used for global register decls. | |
83 | These must be exempt from ordinary flow analysis | |
84 | and are also considered fixed. */ | |
85 | ||
86 | char global_regs[FIRST_PSEUDO_REGISTER]; | |
87 | ||
88 | /* Table of register numbers in the order in which to try to use them. */ | |
89 | #ifdef REG_ALLOC_ORDER | |
90 | int reg_alloc_order[FIRST_PSEUDO_REGISTER] = REG_ALLOC_ORDER; | |
91 | #endif | |
92 | ||
93 | /* For each reg class, a HARD_REG_SET saying which registers are in it. */ | |
94 | ||
95 | HARD_REG_SET reg_class_contents[] = REG_CLASS_CONTENTS; | |
96 | ||
97 | /* For each reg class, number of regs it contains. */ | |
98 | ||
99 | int reg_class_size[N_REG_CLASSES]; | |
100 | ||
101 | /* For each reg class, table listing all the containing classes. */ | |
102 | ||
103 | enum reg_class reg_class_superclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
104 | ||
105 | /* For each reg class, table listing all the classes contained in it. */ | |
106 | ||
107 | enum reg_class reg_class_subclasses[N_REG_CLASSES][N_REG_CLASSES]; | |
108 | ||
109 | /* For each pair of reg classes, | |
110 | a largest reg class contained in their union. */ | |
111 | ||
112 | enum reg_class reg_class_subunion[N_REG_CLASSES][N_REG_CLASSES]; | |
113 | ||
114 | /* Array containing all of the register names */ | |
115 | ||
116 | char *reg_names[] = REGISTER_NAMES; | |
117 | ||
118 | ||
119 | /* Function called only once to initialize the above data on reg usage. | |
120 | Once this is done, various switches may override. */ | |
121 | ||
122 | void | |
123 | init_reg_sets () | |
124 | { | |
125 | register int i, j; | |
126 | ||
127 | bcopy (initial_fixed_regs, fixed_regs, sizeof fixed_regs); | |
128 | bcopy (initial_call_used_regs, call_used_regs, sizeof call_used_regs); | |
129 | bzero (global_regs, sizeof global_regs); | |
130 | ||
131 | /* Compute number of hard regs in each class. */ | |
132 | ||
133 | bzero (reg_class_size, sizeof reg_class_size); | |
134 | for (i = 0; i < N_REG_CLASSES; i++) | |
135 | for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) | |
136 | if (TEST_HARD_REG_BIT (reg_class_contents[i], j)) | |
137 | reg_class_size[i]++; | |
138 | ||
139 | /* Initialize the table of subunions. | |
140 | reg_class_subunion[I][J] gets the largest-numbered reg-class | |
141 | that is contained in the union of classes I and J. */ | |
142 | ||
143 | for (i = 0; i < N_REG_CLASSES; i++) | |
144 | { | |
145 | for (j = 0; j < N_REG_CLASSES; j++) | |
146 | { | |
147 | #ifdef HARD_REG_SET | |
148 | register /* Declare it register if it's a scalar. */ | |
149 | #endif | |
150 | HARD_REG_SET c; | |
151 | register int k; | |
152 | ||
153 | COPY_HARD_REG_SET (c, reg_class_contents[i]); | |
154 | IOR_HARD_REG_SET (c, reg_class_contents[j]); | |
155 | for (k = 0; k < N_REG_CLASSES; k++) | |
156 | { | |
157 | GO_IF_HARD_REG_SUBSET (reg_class_contents[k], c, | |
158 | subclass1); | |
159 | continue; | |
160 | ||
161 | subclass1: | |
162 | reg_class_subunion[i][j] = (enum reg_class) k; | |
163 | } | |
164 | } | |
165 | } | |
166 | ||
167 | /* Initialize the tables of subclasses and superclasses of each reg class. | |
168 | First clear the whole table, then add the elements as they are found. */ | |
169 | ||
170 | for (i = 0; i < N_REG_CLASSES; i++) | |
171 | { | |
172 | for (j = 0; j < N_REG_CLASSES; j++) | |
173 | { | |
174 | reg_class_superclasses[i][j] = LIM_REG_CLASSES; | |
175 | reg_class_subclasses[i][j] = LIM_REG_CLASSES; | |
176 | } | |
177 | } | |
178 | ||
179 | for (i = 0; i < N_REG_CLASSES; i++) | |
180 | { | |
181 | if (i == (int) NO_REGS) | |
182 | continue; | |
183 | ||
184 | for (j = i + 1; j < N_REG_CLASSES; j++) | |
185 | { | |
186 | enum reg_class *p; | |
187 | ||
188 | GO_IF_HARD_REG_SUBSET (reg_class_contents[i], reg_class_contents[j], | |
189 | subclass); | |
190 | continue; | |
191 | subclass: | |
192 | /* Reg class I is a subclass of J. | |
193 | Add J to the table of superclasses of I. */ | |
194 | p = ®_class_superclasses[i][0]; | |
195 | while (*p != LIM_REG_CLASSES) p++; | |
196 | *p = (enum reg_class) j; | |
197 | /* Add I to the table of superclasses of J. */ | |
198 | p = ®_class_subclasses[j][0]; | |
199 | while (*p != LIM_REG_CLASSES) p++; | |
200 | *p = (enum reg_class) i; | |
201 | } | |
202 | } | |
203 | ||
204 | } | |
205 | ||
206 | /* After switches have been processed, which perhaps alter | |
207 | `fixed_regs' and `call_used_regs', convert them to HARD_REG_SETs. */ | |
208 | ||
209 | void | |
210 | init_reg_sets_1 () | |
211 | { | |
212 | register int i; | |
213 | ||
214 | /* This macro allows the fixed or call-used registers | |
215 | to depend on target flags. */ | |
216 | ||
217 | #ifdef CONDITIONAL_REGISTER_USAGE | |
218 | CONDITIONAL_REGISTER_USAGE; | |
219 | #endif | |
220 | ||
221 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
222 | if (global_regs[i]) | |
223 | { | |
224 | if (call_used_regs[i] && ! fixed_regs[i]) | |
225 | warning ("call-clobbered register used for global register variable"); | |
226 | fixed_regs[i] = 1; | |
227 | /* Prevent saving/restoring of this reg. */ | |
228 | call_used_regs[i] = 1; | |
229 | } | |
230 | ||
231 | /* Initialize "constant" tables. */ | |
232 | ||
233 | CLEAR_HARD_REG_SET (fixed_reg_set); | |
234 | CLEAR_HARD_REG_SET (call_used_reg_set); | |
235 | CLEAR_HARD_REG_SET (call_fixed_reg_set); | |
236 | ||
237 | bcopy (fixed_regs, call_fixed_regs, sizeof call_fixed_regs); | |
238 | #ifdef STRUCT_VALUE_REGNUM | |
239 | call_fixed_regs[STRUCT_VALUE_REGNUM] = 1; | |
240 | #endif | |
241 | #ifdef STATIC_CHAIN_REGNUM | |
242 | call_fixed_regs[STATIC_CHAIN_REGNUM] = 1; | |
243 | #endif | |
244 | ||
245 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
246 | { | |
247 | if (FUNCTION_VALUE_REGNO_P (i)) | |
248 | call_fixed_regs[i] = 1; | |
249 | if (fixed_regs[i]) | |
250 | SET_HARD_REG_BIT (fixed_reg_set, i); | |
251 | if (call_used_regs[i]) | |
252 | SET_HARD_REG_BIT (call_used_reg_set, i); | |
253 | if (call_fixed_regs[i]) | |
254 | SET_HARD_REG_BIT (call_fixed_reg_set, i); | |
255 | } | |
256 | } | |
257 | ||
258 | /* Specify the usage characteristics of the register named NAME. | |
259 | It should be a fixed register if FIXED and a | |
260 | call-used register if CALL_USED. */ | |
261 | ||
262 | void | |
263 | fix_register (name, fixed, call_used) | |
264 | char *name; | |
265 | int fixed, call_used; | |
266 | { | |
267 | int i; | |
268 | ||
269 | /* Decode the name and update the primary form of | |
270 | the register info. */ | |
271 | ||
272 | for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) | |
273 | if (!strcmp (reg_names[i], name)) | |
274 | { | |
275 | fixed_regs[i] = fixed; | |
276 | call_used_regs[i] = call_used; | |
277 | break; | |
278 | } | |
279 | ||
280 | if (i == FIRST_PSEUDO_REGISTER) | |
281 | { | |
282 | warning ("unknown register name: %s", name); | |
283 | return; | |
284 | } | |
285 | } | |
286 | \f | |
287 | /* Now the data and code for the `regclass' pass, which happens | |
288 | just before local-alloc. */ | |
289 | ||
290 | /* savings[R].savings[CL] is twice the amount saved by putting register R | |
291 | in class CL. This data is used within `regclass' and freed | |
292 | when it is finished. */ | |
293 | ||
294 | struct savings | |
295 | { | |
296 | short savings[N_REG_CLASSES]; | |
297 | short memcost; | |
298 | short nrefs; | |
299 | }; | |
300 | ||
301 | static struct savings *savings; | |
302 | ||
303 | /* (enum reg_class) prefclass[R] is the preferred class for pseudo number R. | |
304 | This is available after `regclass' is run. */ | |
305 | ||
306 | static char *prefclass; | |
307 | ||
308 | /* preferred_or_nothing[R] is nonzero if we should put pseudo number R | |
309 | in memory if we can't get its perferred class. | |
310 | This is available after `regclass' is run. */ | |
311 | ||
312 | static char *preferred_or_nothing; | |
313 | ||
314 | void reg_class_record (); | |
315 | void record_address_regs (); | |
316 | ||
317 | ||
318 | /* Return the reg_class in which pseudo reg number REGNO is best allocated. | |
319 | This function is sometimes called before the info has been computed. | |
320 | When that happens, just return GENERAL_REGS, which is innocuous. */ | |
321 | ||
322 | enum reg_class | |
323 | reg_preferred_class (regno) | |
324 | int regno; | |
325 | { | |
326 | if (prefclass == 0) | |
327 | return GENERAL_REGS; | |
328 | return (enum reg_class) prefclass[regno]; | |
329 | } | |
330 | ||
331 | int | |
332 | reg_preferred_or_nothing (regno) | |
333 | { | |
334 | if (prefclass == 0) | |
335 | return 0; | |
336 | return preferred_or_nothing[regno]; | |
337 | } | |
338 | ||
339 | /* This prevents dump_flow_info from losing if called | |
340 | before regclass is run. */ | |
341 | ||
342 | int | |
343 | regclass_init () | |
344 | { | |
345 | prefclass = 0; | |
346 | } | |
347 | \f | |
348 | /* This is a pass of the compiler that scans all instructions | |
349 | and calculates the preferred class for each pseudo-register. | |
350 | This information can be accessed later by calling `reg_preferred_class'. | |
351 | This pass comes just before local register allocation. */ | |
352 | ||
353 | void | |
354 | regclass (f, nregs) | |
355 | rtx f; | |
356 | int nregs; | |
357 | { | |
358 | #ifdef REGISTER_CONSTRAINTS | |
359 | register rtx insn; | |
360 | register int i; | |
361 | ||
362 | init_recog (); | |
363 | ||
364 | /* Zero out our accumulation of the cost of each class for each reg. */ | |
365 | ||
366 | savings = (struct savings *) alloca (nregs * sizeof (struct savings)); | |
367 | bzero (savings, nregs * sizeof (struct savings)); | |
368 | ||
369 | /* Scan the instructions and record each time it would | |
370 | save code to put a certain register in a certain class. */ | |
371 | ||
372 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
373 | if ((GET_CODE (insn) == INSN | |
374 | && GET_CODE (PATTERN (insn)) != USE | |
375 | && GET_CODE (PATTERN (insn)) != CLOBBER | |
376 | && GET_CODE (PATTERN (insn)) != ASM_INPUT) | |
377 | || (GET_CODE (insn) == JUMP_INSN | |
378 | && GET_CODE (PATTERN (insn)) != ADDR_VEC | |
379 | && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC) | |
380 | || GET_CODE (insn) == CALL_INSN) | |
381 | { | |
382 | if (GET_CODE (insn) == INSN && asm_noperands (PATTERN (insn)) >= 0) | |
383 | { | |
384 | int noperands = asm_noperands (PATTERN (insn)); | |
385 | /* We don't use alloca because alloca would not free | |
386 | any of the space until this function returns. */ | |
387 | rtx *operands = (rtx *) oballoc (noperands * sizeof (rtx)); | |
388 | char **constraints | |
389 | = (char **) oballoc (noperands * sizeof (char *)); | |
390 | ||
391 | decode_asm_operands (PATTERN (insn), operands, 0, constraints, 0); | |
392 | ||
393 | for (i = noperands - 1; i >= 0; i--) | |
394 | reg_class_record (operands[i], i, constraints); | |
395 | ||
396 | obfree (operands); | |
397 | } | |
398 | else | |
399 | { | |
400 | int insn_code_number = recog_memoized (insn); | |
401 | ||
402 | insn_extract (insn); | |
403 | ||
404 | for (i = insn_n_operands[insn_code_number] - 1; i >= 0; i--) | |
405 | reg_class_record (recog_operand[i], i, | |
406 | insn_operand_constraint[insn_code_number]); | |
407 | ||
408 | /* Improve handling of two-address insns such as | |
409 | (set X (ashift CONST Y)) where CONST must be made to match X. | |
410 | Change it into two insns: (set X CONST) (set X (ashift X Y)). | |
411 | If we left this for reloading, it would probably get three insns | |
412 | because X and Y might go in the same place. | |
413 | This prevents X and Y from receiving the same hard reg. */ | |
414 | ||
415 | if (optimize | |
416 | && insn_n_operands[insn_code_number] >= 3 | |
417 | && insn_operand_constraint[insn_code_number][1][0] == '0' | |
418 | && insn_operand_constraint[insn_code_number][1][1] == 0 | |
419 | && CONSTANT_P (recog_operand[1]) | |
420 | && ! rtx_equal_p (recog_operand[0], recog_operand[1]) | |
421 | && ! rtx_equal_p (recog_operand[0], recog_operand[2]) | |
422 | && GET_CODE (recog_operand[0]) == REG) | |
423 | { | |
424 | rtx previnsn = prev_real_insn (insn); | |
425 | rtx newinsn | |
426 | = emit_insn_before (gen_move_insn (recog_operand[0], | |
427 | recog_operand[1]), | |
428 | insn); | |
429 | ||
430 | /* If this insn was the start of a basic block, | |
431 | include the new insn in that block. */ | |
432 | if (previnsn == 0 || GET_CODE (previnsn) == JUMP_INSN) | |
433 | { | |
434 | int b; | |
435 | for (b = 0; b < n_basic_blocks; b++) | |
436 | if (insn == basic_block_head[b]) | |
437 | basic_block_head[b] = newinsn; | |
438 | } | |
439 | ||
440 | /* This makes one more setting of new insns's destination. */ | |
441 | reg_n_sets[REGNO (recog_operand[0])]++; | |
442 | ||
443 | *recog_operand_loc[1] = recog_operand[0]; | |
444 | for (i = insn_n_dups[insn_code_number] - 1; i >= 0; i--) | |
445 | if (recog_dup_num[i] == 1) | |
446 | *recog_dup_loc[i] = recog_operand[0]; | |
447 | ||
448 | ||
449 | } | |
450 | } | |
451 | } | |
452 | ||
453 | /* Now for each register look at how desirable each class is | |
454 | and find which class is preferred. Store that in `prefclass[REGNO]'. */ | |
455 | ||
456 | prefclass = (char *) oballoc (nregs); | |
457 | ||
458 | preferred_or_nothing = (char *) oballoc (nregs); | |
459 | ||
460 | for (i = FIRST_PSEUDO_REGISTER; i < nregs; i++) | |
461 | { | |
462 | register int best_savings = 0; | |
463 | enum reg_class best = ALL_REGS; | |
464 | ||
465 | /* This is an enum reg_class, but we call it an int | |
466 | to save lots of casts. */ | |
467 | register int class; | |
468 | register struct savings *p = &savings[i]; | |
469 | ||
470 | for (class = (int) ALL_REGS - 1; class > 0; class--) | |
471 | { | |
472 | if (p->savings[class] > best_savings) | |
473 | { | |
474 | best_savings = p->savings[class]; | |
475 | best = (enum reg_class) class; | |
476 | } | |
477 | else if (p->savings[class] == best_savings) | |
478 | { | |
479 | best = reg_class_subunion[(int)best][class]; | |
480 | } | |
481 | } | |
482 | ||
483 | #if 0 | |
484 | /* Note that best_savings is twice number of places something | |
485 | is saved. */ | |
486 | if ((best_savings - p->savings[(int) GENERAL_REGS]) * 5 < reg_n_refs[i]) | |
487 | prefclass[i] = (int) GENERAL_REGS; | |
488 | else | |
489 | prefclass[i] = (int) best; | |
490 | #else | |
491 | /* We cast to (int) because (char) hits bugs in some compilers. */ | |
492 | prefclass[i] = (int) best; | |
493 | #endif | |
494 | ||
495 | /* reg_n_refs + p->memcost measures the cost of putting in memory. | |
496 | If a GENERAL_REG is no better, don't even try for one. | |
497 | Since savings and memcost are 2 * number of refs, | |
498 | this effectively counts each memory operand not needing reloading | |
499 | as costing 1/2 of a reload insn. */ | |
500 | if (reg_n_refs != 0) | |
501 | preferred_or_nothing[i] | |
502 | = ((best_savings - p->savings[(int) GENERAL_REGS]) | |
503 | >= p->nrefs + p->memcost); | |
504 | } | |
505 | #endif /* REGISTER_CONSTRAINTS */ | |
506 | } | |
507 | \f | |
508 | #ifdef REGISTER_CONSTRAINTS | |
509 | ||
510 | /* Scan an operand OP for register class preferences. | |
511 | OPNO is the operand number, and CONSTRAINTS is the constraint | |
512 | vector for the insn. | |
513 | ||
514 | Record the preferred register classes from the constraint for OP | |
515 | if OP is a register. If OP is a memory reference, record suitable | |
516 | preferences for registers used in the address. */ | |
517 | ||
518 | void | |
519 | reg_class_record (op, opno, constraints) | |
520 | rtx op; | |
521 | int opno; | |
522 | char **constraints; | |
523 | { | |
524 | char *constraint = constraints[opno]; | |
525 | register char *p; | |
526 | register enum reg_class class = NO_REGS; | |
527 | char *next = 0; | |
528 | int memok = 0; | |
529 | int double_cost = 0; | |
530 | ||
531 | while (1) | |
532 | { | |
533 | if (GET_CODE (op) == SUBREG) | |
534 | op = SUBREG_REG (op); | |
535 | else break; | |
536 | } | |
537 | ||
538 | /* Memory reference: scan the address. */ | |
539 | ||
540 | if (GET_CODE (op) == MEM) | |
541 | record_address_regs (XEXP (op, 0), 2, 0); | |
542 | ||
543 | if (GET_CODE (op) != REG) | |
544 | { | |
545 | /* If the constraint says the operand is supposed to BE an address, | |
546 | scan it as one. */ | |
547 | ||
548 | if (constraint != 0 && constraint[0] == 'p') | |
549 | record_address_regs (op, 2, 0); | |
550 | return; | |
551 | } | |
552 | ||
553 | /* Operand is a register: examine the constraint for specified classes. */ | |
554 | ||
555 | for (p = constraint; *p || next; p++) | |
556 | { | |
557 | if (*p == 0) | |
558 | { | |
559 | p = next; | |
560 | next = 0; | |
561 | } | |
562 | switch (*p) | |
563 | { | |
564 | case '=': | |
565 | case '?': | |
566 | case '#': | |
567 | case '&': | |
568 | case '!': | |
569 | case '%': | |
570 | case 'F': | |
571 | case 'G': | |
572 | case 'H': | |
573 | case 'i': | |
574 | case 'n': | |
575 | case 's': | |
576 | case 'p': | |
577 | case ',': | |
578 | break; | |
579 | ||
580 | case '+': | |
581 | /* An input-output operand is twice as costly if it loses. */ | |
582 | double_cost = 1; | |
583 | break; | |
584 | ||
585 | case 'm': | |
586 | case 'o': | |
587 | memok = 1; | |
588 | break; | |
589 | ||
590 | /* * means ignore following letter | |
591 | when choosing register preferences. */ | |
592 | case '*': | |
593 | p++; | |
594 | break; | |
595 | ||
596 | case 'g': | |
597 | case 'r': | |
598 | class | |
599 | = reg_class_subunion[(int) class][(int) GENERAL_REGS]; | |
600 | break; | |
601 | ||
602 | case '0': | |
603 | case '1': | |
604 | case '2': | |
605 | case '3': | |
606 | case '4': | |
607 | /* If constraint says "match another operand", | |
608 | use that operand's constraint to choose preferences. */ | |
609 | next = constraints[*p - '0']; | |
610 | break; | |
611 | ||
612 | default: | |
613 | class | |
614 | = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER (*p)]; | |
615 | } | |
616 | } | |
617 | ||
618 | { | |
619 | register int i; | |
620 | register struct savings *pp; | |
621 | register enum reg_class class1; | |
622 | int cost = 2 * (1 + double_cost); | |
623 | pp = &savings[REGNO (op)]; | |
624 | ||
625 | /* Increment the savings for this reg | |
626 | for each class contained in the one the constraint asks for. */ | |
627 | ||
628 | if (class != NO_REGS && class != ALL_REGS) | |
629 | { | |
630 | pp->savings[(int) class] += cost; | |
631 | for (i = 0; ; i++) | |
632 | { | |
633 | class1 = reg_class_subclasses[(int)class][i]; | |
634 | if (class1 == LIM_REG_CLASSES) | |
635 | break; | |
636 | pp->savings[(int) class1] += cost; | |
637 | } | |
638 | } | |
639 | ||
640 | if (! memok) | |
641 | pp->memcost += 1 + 2 * double_cost; | |
642 | pp->nrefs++; | |
643 | } | |
644 | } | |
645 | ||
646 | /* Record the pseudo registers we must reload into hard registers | |
647 | in a subexpression of a memory address, X. | |
648 | BCOST is the cost if X is a register and it fails to be in BASE_REG_CLASS. | |
649 | ICOST is the cost if it fails to be in INDEX_REG_CLASS. */ | |
650 | ||
651 | void | |
652 | record_address_regs (x, bcost, icost) | |
653 | rtx x; | |
654 | int bcost, icost; | |
655 | { | |
656 | register enum rtx_code code = GET_CODE (x); | |
657 | ||
658 | switch (code) | |
659 | { | |
660 | case CONST_INT: | |
661 | case CONST: | |
662 | case CC0: | |
663 | case PC: | |
664 | case SYMBOL_REF: | |
665 | case LABEL_REF: | |
666 | return; | |
667 | ||
668 | case PLUS: | |
669 | /* When we have an address that is a sum, | |
670 | we must determine whether registers are "base" or "index" regs. | |
671 | If there is a sum of two registers, we must choose one to be | |
672 | the "base". Luckily, we can use the REGNO_POINTER_FLAG | |
673 | to make a good choice most of the time. */ | |
674 | { | |
675 | rtx arg0 = XEXP (x, 0); | |
676 | rtx arg1 = XEXP (x, 1); | |
677 | register enum rtx_code code0 = GET_CODE (arg0); | |
678 | register enum rtx_code code1 = GET_CODE (arg1); | |
679 | int icost0 = 0; | |
680 | int icost1 = 0; | |
681 | int suppress1 = 0; | |
682 | int suppress0 = 0; | |
683 | ||
684 | /* Look inside subregs. */ | |
685 | while (code0 == SUBREG) | |
686 | arg0 = SUBREG_REG (arg0), code0 = GET_CODE (arg0); | |
687 | while (code1 == SUBREG) | |
688 | arg1 = SUBREG_REG (arg1), code1 = GET_CODE (arg1); | |
689 | ||
690 | if (code0 == MULT || code1 == MEM) | |
691 | icost0 = 2; | |
692 | else if (code1 == MULT || code0 == MEM) | |
693 | icost1 = 2; | |
694 | else if (code0 == CONST_INT) | |
695 | suppress0 = 1; | |
696 | else if (code1 == CONST_INT) | |
697 | suppress1 = 1; | |
698 | else if (code0 == REG && code1 == REG) | |
699 | { | |
700 | if (REGNO_POINTER_FLAG (REGNO (arg0))) | |
701 | icost1 = 2; | |
702 | else if (REGNO_POINTER_FLAG (REGNO (arg1))) | |
703 | icost0 = 2; | |
704 | else | |
705 | icost0 = icost1 = 1; | |
706 | } | |
707 | else if (code0 == REG) | |
708 | { | |
709 | if (code1 == PLUS | |
710 | && ! REGNO_POINTER_FLAG (REGNO (arg0))) | |
711 | icost0 = 2; | |
712 | else | |
713 | REGNO_POINTER_FLAG (REGNO (arg0)) = 1; | |
714 | } | |
715 | else if (code1 == REG) | |
716 | { | |
717 | if (code0 == PLUS | |
718 | && ! REGNO_POINTER_FLAG (REGNO (arg1))) | |
719 | icost1 = 2; | |
720 | else | |
721 | REGNO_POINTER_FLAG (REGNO (arg1)) = 1; | |
722 | } | |
723 | ||
724 | /* ICOST0 determines whether we are treating operand 0 | |
725 | as a base register or as an index register. | |
726 | SUPPRESS0 nonzero means it isn't a register at all. | |
727 | ICOST1 and SUPPRESS1 are likewise for operand 1. */ | |
728 | ||
729 | if (! suppress0) | |
730 | record_address_regs (arg0, 2 - icost0, icost0); | |
731 | if (! suppress1) | |
732 | record_address_regs (arg1, 2 - icost1, icost1); | |
733 | } | |
734 | break; | |
735 | ||
736 | case POST_INC: | |
737 | case PRE_INC: | |
738 | case POST_DEC: | |
739 | case PRE_DEC: | |
740 | /* Double the importance of a pseudo register that is incremented | |
741 | or decremented, since it would take two extra insns | |
742 | if it ends up in the wrong place. */ | |
743 | record_address_regs (XEXP (x, 0), 2 * bcost, 2 * icost); | |
744 | break; | |
745 | ||
746 | case REG: | |
747 | { | |
748 | register struct savings *pp; | |
749 | register enum reg_class class, class1; | |
750 | pp = &savings[REGNO (x)]; | |
751 | pp->nrefs++; | |
752 | ||
753 | /* We have an address (or part of one) that is just one register. */ | |
754 | ||
755 | /* Record BCOST worth of savings for classes contained | |
756 | in BASE_REG_CLASS. */ | |
757 | ||
758 | class = BASE_REG_CLASS; | |
759 | if (class != NO_REGS && class != ALL_REGS) | |
760 | { | |
761 | register int i; | |
762 | pp->savings[(int) class] += bcost; | |
763 | for (i = 0; ; i++) | |
764 | { | |
765 | class1 = reg_class_subclasses[(int)class][i]; | |
766 | if (class1 == LIM_REG_CLASSES) | |
767 | break; | |
768 | pp->savings[(int) class1] += bcost; | |
769 | } | |
770 | } | |
771 | ||
772 | /* Record ICOST worth of savings for classes contained | |
773 | in INDEX_REG_CLASS. */ | |
774 | ||
775 | class = INDEX_REG_CLASS; | |
776 | if (icost != 0 && class != NO_REGS && class != ALL_REGS) | |
777 | { | |
778 | register int i; | |
779 | pp->savings[(int) class] += icost; | |
780 | for (i = 0; ; i++) | |
781 | { | |
782 | class1 = reg_class_subclasses[(int)class][i]; | |
783 | if (class1 == LIM_REG_CLASSES) | |
784 | break; | |
785 | pp->savings[(int) class1] += icost; | |
786 | } | |
787 | } | |
788 | } | |
789 | break; | |
790 | ||
791 | default: | |
792 | { | |
793 | register char *fmt = GET_RTX_FORMAT (code); | |
794 | register int i; | |
795 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
796 | if (fmt[i] == 'e') | |
797 | record_address_regs (XEXP (x, i), bcost, icost); | |
798 | } | |
799 | } | |
800 | } | |
801 | #endif /* REGISTER_CONSTRAINTS */ | |
802 | \f | |
803 | /* This is the `regscan' pass of the compiler, run just before cse | |
804 | and again just before loop. | |
805 | ||
806 | It finds the first and last use of each pseudo-register | |
807 | and records them in the vectors regno_first_uid, regno_last_uid. | |
808 | REPEAT is nonzero the second time this is called. */ | |
809 | ||
810 | /* Indexed by pseudo register number, gives uid of first insn using the reg | |
811 | (as of the time reg_scan is called). */ | |
812 | ||
813 | short *regno_first_uid; | |
814 | ||
815 | /* Indexed by pseudo register number, gives uid of last insn using the reg | |
816 | (as of the time reg_scan is called). */ | |
817 | ||
818 | short *regno_last_uid; | |
819 | ||
820 | /* Maximum number of parallel sets and clobbers in any insn in this fn. | |
821 | Always at least 3, since the combiner could put that many togetherm | |
822 | and we want this to remain correct for all the remaining passes. */ | |
823 | ||
824 | int max_parallel; | |
825 | ||
826 | void reg_scan_mark_refs (); | |
827 | ||
828 | void | |
829 | reg_scan (f, nregs, repeat) | |
830 | rtx f; | |
831 | int nregs; | |
832 | int repeat; | |
833 | { | |
834 | register rtx insn; | |
835 | ||
836 | if (!repeat) | |
837 | regno_first_uid = (short *) oballoc (nregs * sizeof (short)); | |
838 | bzero (regno_first_uid, nregs * sizeof (short)); | |
839 | ||
840 | if (!repeat) | |
841 | regno_last_uid = (short *) oballoc (nregs * sizeof (short)); | |
842 | bzero (regno_last_uid, nregs * sizeof (short)); | |
843 | ||
844 | max_parallel = 3; | |
845 | ||
846 | for (insn = f; insn; insn = NEXT_INSN (insn)) | |
847 | if (GET_CODE (insn) == INSN | |
848 | || GET_CODE (insn) == CALL_INSN | |
849 | || GET_CODE (insn) == JUMP_INSN) | |
850 | { | |
851 | if (GET_CODE (PATTERN (insn)) == PARALLEL | |
852 | && XVECLEN (PATTERN (insn), 0) > max_parallel) | |
853 | max_parallel = XVECLEN (PATTERN (insn), 0); | |
854 | reg_scan_mark_refs (PATTERN (insn), INSN_UID (insn)); | |
855 | } | |
856 | } | |
857 | ||
858 | void | |
859 | reg_scan_mark_refs (x, uid) | |
860 | rtx x; | |
861 | int uid; | |
862 | { | |
863 | register enum rtx_code code = GET_CODE (x); | |
864 | ||
865 | switch (code) | |
866 | { | |
867 | case CONST_INT: | |
868 | case CONST: | |
869 | case CONST_DOUBLE: | |
870 | case CC0: | |
871 | case PC: | |
872 | case SYMBOL_REF: | |
873 | case LABEL_REF: | |
874 | case ADDR_VEC: | |
875 | case ADDR_DIFF_VEC: | |
876 | return; | |
877 | ||
878 | case REG: | |
879 | { | |
880 | register int regno = REGNO (x); | |
881 | ||
882 | regno_last_uid[regno] = uid; | |
883 | if (regno_first_uid[regno] == 0) | |
884 | regno_first_uid[regno] = uid; | |
885 | } | |
886 | break; | |
887 | ||
888 | default: | |
889 | { | |
890 | register char *fmt = GET_RTX_FORMAT (code); | |
891 | register int i; | |
892 | for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) | |
893 | { | |
894 | if (fmt[i] == 'e') | |
895 | reg_scan_mark_refs (XEXP (x, i), uid); | |
896 | else if (fmt[i] == 'E' && XVEC (x, i) != 0) | |
897 | { | |
898 | register int j; | |
899 | for (j = XVECLEN (x, i) - 1; j >= 0; j--) | |
900 | reg_scan_mark_refs (XVECEXP (x, i, j), uid); | |
901 | } | |
902 | } | |
903 | } | |
904 | } | |
905 | } |