add rd53
[unix-history] / usr / src / sys / vax / uba / tsreg.h
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1/*
2 * Copyright (c) 1982 Regents of the University of California.
3 * All rights reserved. The Berkeley software License Agreement
4 * specifies the terms and conditions for redistribution.
5 *
6 * @(#)tsreg.h 6.2 (Berkeley) %G%
7 */
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8
9/*
10 * TS11 controller registers
11 */
2da9d74d 12struct tsdevice {
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13 u_short tsdb; /* data buffer */
14 u_short tssr; /* status register */
15};
16
17/* Bits in (unibus) status register */
18#define TS_SC 0100000 /* special condition (error) */
19#define TS_UPE 0040000 /* Unibus parity error */
20#define TS_SPE 0020000 /* serial bus parity error */
21#define TS_RMR 0010000 /* register modification refused */
22#define TS_NXM 0004000 /* nonexistant memory */
23#define TS_NBA 0002000 /* need buffer address */
24#define TS_XMEM 0001400 /* Unibus xmem bits */
25#define TS_SSR 0000200 /* subsytem ready */
26#define TS_OFL 0000100 /* off-line */
27#define TS_FTC 0000060 /* fatal termination class */
28#define TS_TC 0000016 /* termination class */
29
30#define TS_SUCC 000 /* successful termination */
31#define TS_ATTN 002 /* attention */
32#define TS_ALERT 004 /* tape status alert */
33#define TS_REJECT 06 /* function reject */
34#define TS_RECOV 010 /* recoverable error */
35#define TS_RECNM 012 /* recoverable error, no tape motion */
36#define TS_UNREC 014 /* unrecoverable error */
37#define TS_FATAL 016 /* fatal error */
38
39#define TSSR_BITS \
40"\10\20SC\17UPE\16SPE\15RMR\14NXM\13NBA\12A17\11A16\10SSR\
41\7OFL\6FC1\5FC0\4TC2\3TC1\2TC0\1-"
42
43#define b_repcnt b_bcount
44#define b_command b_resid
45
46/* status message */
47struct ts_sts {
48 u_short s_sts; /* packet header */
49 u_short s_len; /* packet length */
50 u_short s_rbpcr; /* residual frame count */
51 u_short s_xs0; /* extended status 0 - 3 */
52 u_short s_xs1;
53 u_short s_xs2;
54 u_short s_xs3;
55};
56
57/* Error codes in xstat 0 */
58#define TS_TMK 0100000 /* tape mark detected */
59#define TS_RLS 0040000 /* record length short */
60#define TS_LET 0020000 /* logical end of tape */
61#define TS_RLL 0010000 /* record length long */
62#define TS_WLE 0004000 /* write lock error */
63#define TS_NEF 0002000 /* non-executable function */
64#define TS_ILC 0001000 /* illegal command */
65#define TS_ILA 0000400 /* illegal address */
66#define TS_MOT 0000200 /* capstan is moving */
67#define TS_ONL 0000100 /* on-line */
68#define TS_IES 0000040 /* interrupt enable status */
69#define TS_VCK 0000020 /* volume check */
70#define TS_PED 0000010 /* phase-encoded drive */
71#define TS_WLK 0000004 /* write locked */
72#define TS_BOT 0000002 /* beginning of tape */
73#define TS_EOT 0000001 /* end of tape */
74
75#define TSXS0_BITS \
76"\10\20TMK\17RLS\16LET\15RLL\14WLE\13NEF\12ILC\11ILA\10MOT\
77\7ONL\6IES\5VCK\4PED\3WLK\2BOT\1EOT"
78
79/* Error codes in xstat 1 */
80#define TS_DLT 0100000 /* data late */
81#define TS_COR 0020000 /* correctable data */
82#define TS_CRS 0010000 /* crease detected */
83#define TS_TIG 0004000 /* trash in the gap */
84#define TS_DBF 0002000 /* deskew buffer full */
85#define TS_SCK 0001000 /* speed check */
86#define TS_IPR 0000200 /* invalid preamble */
87#define TS_SYN 0000100 /* synchronization failure */
88#define TS_IPO 0000040 /* invalid postamble */
89#define TS_IED 0000020 /* invalid end of data */
90#define TS_POS 0000010 /* postamble short */
91#define TS_POL 0000004 /* postamble long */
92#define TS_UNC 0000002 /* uncorrectable data */
93#define TS_MTE 0000001 /* multitrack error */
94
95#define TSXS1_BITS \
96"\10\20DLT\17-\16COR\15CRS\14TIG\13DBF\12SCK\11-\10IPR\
97\7SYN\6IPO\5IED\4POS\3POL\2UNC\1MTE"
98
99/* Error codes in xstat 2 */
100#define TS_OPM 0100000 /* operation in progress */
101#define TS_SIP 0040000 /* silo parity error */
102#define TS_BPE 0020000 /* serial bus parity error */
103#define TS_CAF 0010000 /* capstan acceleration failure */
104#define TS_WCF 0002000 /* write card fail */
105#define TS_DTP 0000400 /* dead track parity */
106#define TS_DT 0000377 /* dead tracks */
107
108#define TSXS2_BITS \
109"\10\20OPM\17SIP\16BPE\15CAF\14-\13WCF\12-\11DTP"
110
111/* Error codes in xstat 3 */
112#define TS_MEC 0177400 /* microdiagnostic error code */
113#define TS_LMX 0000200 /* limit exceeded */
114#define TS_OPI 0000100 /* operation incomplete */
115#define TS_REV 0000040 /* reverse */
116#define TS_CRF 0000020 /* capstan response fail */
117#define TS_DCK 0000010 /* density check */
118#define TS_NOI 0000004 /* noise record */
119#define TS_LXS 0000002 /* limit exceeded statically */
120#define TS_RIB 0000001 /* reverse into BOT */
121
122#define TSXS3_BITS \
123"\10\10LMX\7OPI\6REV\5CRF\4DCK\3NOI\2LXS\1RIB"
124
125
126/* command message */
127struct ts_cmd {
128 u_short c_cmd; /* command */
129 u_short c_loba; /* low order buffer address */
130 u_short c_hiba; /* high order buffer address */
131#define c_repcnt c_loba
132 u_short c_size; /* byte count */
133};
134
135/* commands and command bits */
136#define TS_ACK 0100000 /* ack - release command packet */
137#define TS_CVC 0040000 /* clear volume check */
138#define TS_IE 0000200
139#define TS_RCOM 0000001
140#define TS_REREAD 0001001 /* read data retry */
141#define TS_SETCHR 0000004 /* set characteristics */
142#define TS_WCOM 0000005
143#define TS_REWRITE 0001005 /* write data retry */
144#define TS_RETRY 0001000 /* retry bit for read and write */
145#define TS_SFORW 0000010 /* forward space record */
146#define TS_SREV 0000410 /* reverse space record */
147#define TS_SFORWF 0001010 /* forward space file */
148#define TS_SREVF 0001410 /* reverse space file */
149#define TS_REW 0002010 /* rewind */
150#define TS_OFFL 0000412 /* unload */
151#define TS_WEOF 0000011 /* write tape mark */
152#define TS_SENSE 0000017 /* get status */
153
154/* characteristics data */
155struct ts_char {
156 long char_addr; /* address of status packet */
157 u_short char_size; /* its size */
158 u_short char_mode; /* characteristics */
159};
160
161
162/* characteristics */
163#define TS_ESS 0200 /* enable skip tape marks stop */
164#define TS_ENB 0100 /* ??? */
165#define TS_EAI 0040 /* enable attention interrupts */
166#define TS_ERI 0020 /* enable message buffer release interrupts */