Commit | Line | Data |
---|---|---|
da7c5cc6 KM |
1 | /* |
2 | * Copyright (c) 1982 Regents of the University of California. | |
3 | * All rights reserved. The Berkeley software License Agreement | |
4 | * specifies the terms and conditions for redistribution. | |
5 | * | |
6 | * @(#)ikreg.h 6.2 (Berkeley) %G% | |
7 | */ | |
45bd4d10 SL |
8 | |
9 | struct ikdevice { | |
39d536e6 BJ |
10 | short ik_wc; /* Unibus word count reg */ |
11 | u_short ik_ubaddr; /* Unibus address register */ | |
12 | u_short ik_ustat; /* Unibus status/command reg */ | |
13 | u_short ik_data; /* Data register */ | |
14 | u_short ik_xaddr; /* X address in frame buffer */ | |
15 | u_short ik_yaddr; /* Y address in frame buffer */ | |
16 | u_short ik_istat; /* Ikonas status/command reg */ | |
c5c0b1fb | 17 | u_short ik_chan; /* Channel control register */ |
45bd4d10 SL |
18 | }; |
19 | ||
4b72e2f9 SL |
20 | #define IK_GETADDR IKIOGETADDR |
21 | #define IK_WAITINT IKIOWAITINT | |
22 | #define IKIOGETADDR _IOR(i, 0, caddr_t) /* get Unibus device address */ | |
23 | #define IKIOWAITINT _IO(i, 1) /* await device interrupt */ | |
45bd4d10 SL |
24 | |
25 | /* | |
26 | * Unibus status/command register bits | |
27 | */ | |
28 | ||
29 | #define IK_GO 01 | |
30 | #define IK_IENABLE 0100 | |
31 | #define IK_READY 0200 | |
32 | #define IK_IKONAS_INTR 0100000 | |
33 | ||
34 | /* | |
35 | * Ikonas status/command register bits | |
36 | */ | |
37 | ||
38 | #define WORD32 0 | |
39 | #define RES512 2 | |
40 | #define RES1024 3 | |
41 | #define READ_SELECT 0 | |
42 | #define WRITE_MASK 010 | |
43 | #define WRITE_SELECT 020 | |
44 | #define HALFWORD 040 | |
45 | #define DMAENABLE 0100 | |
46 | #define INVISIBLE_IO 0200 | |
47 | #define AUTOINCREMENT 0400 | |
48 | #define RUN_PROCESSOR 01000 | |
49 | #define CLEAR 02000 | |
50 | #define BYTE_MODE 04000 | |
51 | #define FRAME_ENABLE 010000 | |
52 | #define PROC_ENABLE 020000 | |
53 | #define RED_SELECT 0 | |
54 | #define GREEN_SELECT 040000 | |
55 | #define BLUE_SELECT 0100000 | |
56 | #define ALPHA_SELECT 0140000 | |
57 | ||
58 | /* | |
59 | * Frame buffer controller | |
60 | */ | |
61 | ||
62 | #define FBC0 060000000 | |
63 | #define FBC1 062000000 | |
64 | ||
65 | #define VIEWPORT_LOC 0 | |
66 | #define VIEWPORT_SIZE 1 | |
67 | #define WINDOW_LOC 2 | |
68 | #define ZOOM 3 | |
69 | #define DISPLAY_RATE 4 | |
70 | #define VIDEO_CONTROL 5 | |
71 | #define FORMAT_CONTROL_MASK 03 | |
72 | #define CURSOR_ON 04 | |
73 | #define LOW_RESOL 0 | |
74 | #define HIGH_RESOL 010 | |
75 | #define AUTO_CLEAR 040 | |
76 | #define EXT_SYNC 0100 | |
77 | #define COLOR_MAP_PAGES 0600 | |
78 | #define HIGH_RESOL_SYNC 01000 | |
79 | #define REPEAT_FIELD 02000 | |
80 | #define PIXEL_CLOCK_RATE_MASK 077 | |
81 | #define CURSOR_LOC 6 | |
82 | #define CURSOR_SHADE 7 | |
83 | ||
84 | #define CURSOR_MAP 0400 | |
85 | ||
86 | /* | |
87 | * Color map lookup table | |
88 | */ | |
89 | ||
90 | #define CMAP0 040600000 | |
91 | #define CMAP1 040610000 | |
92 | ||
93 | #define CHAN_SELECT 02000 | |
94 | ||
95 | /* | |
96 | * Frame buffer memories | |
97 | */ | |
98 | ||
99 | #define MEM0 000000000 | |
100 | #define MEM1 004000000 | |
101 | ||
102 | /* | |
103 | * Bit-slice processor | |
104 | */ | |
105 | ||
106 | #define UMEM 040000000 | |
107 | #define SCRPAD 040400000 | |
108 | #define PROC 041200000 | |
109 | ||
110 | /* | |
111 | * Frame grabber | |
112 | */ | |
113 | ||
114 | #define FMG0 060200000 |