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1 | /* |
2 | * Copyright (c) 1988 University of Utah. | |
3 | * Copyright (c) 1982, 1990 The Regents of the University of California. | |
4 | * All rights reserved. | |
5 | * | |
6 | * This code is derived from software contributed to Berkeley by | |
7 | * the Systems Programming Group of the University of Utah Computer | |
8 | * Science Department. | |
9 | * | |
10 | * %sccs.include.redist.c% | |
11 | * | |
9e153d67 | 12 | * from: Utah $Hdr: cpu.h 1.16 91/03/25$ |
88a7e859 | 13 | * |
e19239c3 | 14 | * @(#)cpu.h 7.12 (Berkeley) %G% |
ba327c15 MK |
15 | */ |
16 | ||
ba327c15 MK |
17 | /* |
18 | * Exported definitions unique to hp300/68k cpu support. | |
19 | */ | |
20 | ||
21 | /* | |
22 | * definitions of cpu-dependent requirements | |
23 | * referenced in generic code | |
24 | */ | |
25 | #define COPY_SIGCODE /* copy sigcode above user stack in exec */ | |
26 | ||
ba327c15 | 27 | #define cpu_exec(p) /* nothing */ |
54ba99e8 | 28 | #define cpu_wait(p) /* nothing */ |
ec183d9e KM |
29 | #define cpu_setstack(p, ap) \ |
30 | (p)->p_md.md_regs[SP] = ap | |
ba327c15 MK |
31 | |
32 | /* | |
e19239c3 CT |
33 | * Arguments to hardclock and gatherstats encapsulate the previous |
34 | * machine state in an opaque clockframe. One the hp300, we use | |
35 | * what the hardware pushes on an interrupt (but we pad the sr to a | |
36 | * longword boundary). | |
ba327c15 | 37 | */ |
cf8f54d4 CT |
38 | struct clockframe { |
39 | u_short pad; /* pad to get stack aligned */ | |
40 | u_short sr; /* sr at time of interrupt */ | |
41 | u_long pc; /* pc at time of interrupt */ | |
42 | u_short vo; /* vector offset (4-word frame) */ | |
43 | }; | |
ba327c15 | 44 | |
cf8f54d4 CT |
45 | #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) |
46 | #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) | |
ba327c15 | 47 | #define CLKF_PC(framep) ((framep)->pc) |
cf8f54d4 CT |
48 | #if 0 |
49 | /* We would like to do it this way... */ | |
50 | #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) | |
51 | #else | |
52 | /* but until we start using PSL_M, we have to do this instead */ | |
53 | #define CLKF_INTR(framep) (0) /* XXX */ | |
54 | #endif | |
ba327c15 MK |
55 | |
56 | ||
57 | /* | |
58 | * Preempt the current process if in interrupt from user mode, | |
59 | * or after the current trap/syscall if in system mode. | |
60 | */ | |
61 | #define need_resched() { want_resched++; aston(); } | |
62 | ||
ba327c15 | 63 | /* |
cf8f54d4 CT |
64 | * Give a profiling tick to the current process when the user profiling |
65 | * buffer pages are invalid. On the hp300, request an ast to send us | |
66 | * through trap, marking the proc as needing a profiling tick. | |
ba327c15 | 67 | */ |
cf8f54d4 | 68 | #define need_proftick(p) { (p)->p_flag |= SOWEUPC; aston(); } |
ba327c15 | 69 | |
600bf028 MK |
70 | /* |
71 | * Notify the current process (p) that it has a signal pending, | |
72 | * process as soon as possible. | |
73 | */ | |
74 | #define signotify(p) aston() | |
75 | ||
76 | #define aston() (astpending++) | |
77 | ||
78 | int astpending; /* need to trap before returning to user mode */ | |
ba327c15 MK |
79 | int want_resched; /* resched() was called */ |
80 | ||
81 | ||
82 | /* | |
83 | * simulated software interrupt register | |
84 | */ | |
85 | extern unsigned char ssir; | |
86 | ||
87 | #define SIR_NET 0x1 | |
88 | #define SIR_CLOCK 0x2 | |
89 | ||
90 | #define siroff(x) ssir &= ~(x) | |
91 | #define setsoftnet() ssir |= SIR_NET | |
92 | #define setsoftclock() ssir |= SIR_CLOCK | |
93 | ||
94 | ||
95 | ||
96 | /* | |
97 | * The rest of this should probably be moved to ../hp300/hp300cpu.h, | |
98 | * although some of it could probably be put into generic 68k headers. | |
88a7e859 KM |
99 | */ |
100 | ||
101 | /* values for machineid */ | |
4534a638 KM |
102 | #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ |
103 | #define HP_330 1 /* 16Mhz 68020+68851 MMU */ | |
104 | #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ | |
105 | #define HP_360 3 /* 25Mhz 68030 */ | |
106 | #define HP_370 4 /* 33Mhz 68030+64K external cache */ | |
107 | #define HP_340 5 /* 16Mhz 68030 */ | |
108 | #define HP_375 6 /* 50Mhz 68030+32K external cache */ | |
9acfa6cd | 109 | #define HP_380 7 /* 25Mhz 68040 */ |
88a7e859 KM |
110 | |
111 | /* values for mmutype (assigned for quick testing) */ | |
9acfa6cd | 112 | #define MMU_68040 -2 /* 68040 on-chip MMU */ |
4534a638 KM |
113 | #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ |
114 | #define MMU_HP 0 /* HP proprietary */ | |
115 | #define MMU_68851 1 /* Motorola 68851 */ | |
88a7e859 KM |
116 | |
117 | /* values for ectype */ | |
4534a638 KM |
118 | #define EC_PHYS -1 /* external physical address cache */ |
119 | #define EC_NONE 0 /* no external cache */ | |
120 | #define EC_VIRT 1 /* external virtual address cache */ | |
88a7e859 KM |
121 | |
122 | /* values for cpuspeed (not really related to clock speed due to caches) */ | |
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123 | #define MHZ_8 1 |
124 | #define MHZ_16 2 | |
125 | #define MHZ_25 3 | |
126 | #define MHZ_33 4 | |
127 | #define MHZ_50 6 | |
88a7e859 KM |
128 | |
129 | #ifdef KERNEL | |
130 | extern int machineid, mmutype, ectype; | |
9e153d67 | 131 | extern char *intiobase, *intiolimit; |
88a7e859 KM |
132 | |
133 | /* what is this supposed to do? i.e. how is it different than startrtclock? */ | |
134 | #define enablertclock() | |
135 | ||
136 | #endif | |
137 | ||
138 | /* physical memory sections */ | |
4534a638 | 139 | #define ROMBASE (0x00000000) |
9e153d67 MH |
140 | #define INTIOBASE (0x00400000) |
141 | #define INTIOTOP (0x00600000) | |
142 | #define EXTIOBASE (0x00600000) | |
143 | #define EXTIOTOP (0x20000000) | |
4534a638 KM |
144 | #define MAXADDR (0xFFFFF000) |
145 | ||
9e153d67 MH |
146 | /* |
147 | * Internal IO space: | |
148 | * | |
149 | * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). | |
150 | * | |
151 | * Internal IO space is mapped in the kernel from ``intiobase'' to | |
152 | * ``intiolimit'' (defined in locore.s). Since it is always mapped, | |
153 | * conversion between physical and kernel virtual addresses is easy. | |
154 | */ | |
155 | #define ISIIOVA(va) \ | |
156 | ((char *)(va) >= intiobase && (char *)(va) < intiolimit) | |
157 | #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) | |
158 | #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) | |
159 | #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) | |
160 | #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ | |
88a7e859 | 161 | |
9e153d67 MH |
162 | /* |
163 | * External IO space: | |
164 | * | |
165 | * DIO ranges from select codes 0-63 at physical addresses given by: | |
166 | * 0x600000 + (sc - 32) * 0x10000 | |
167 | * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for | |
168 | * their control space and the remaining areas, [0x200000-0x400000) and | |
169 | * [0x800000-0x1000000), are for additional space required by a card; | |
170 | * e.g. a display framebuffer. | |
171 | * | |
172 | * DIO-II ranges from select codes 132-255 at physical addresses given by: | |
173 | * 0x1000000 + (sc - 132) * 0x400000 | |
174 | * The address range of DIO-II space is thus [0x1000000-0x20000000). | |
175 | * | |
176 | * DIO/DIO-II space is too large to map in its entirety, instead devices | |
177 | * are mapped into kernel virtual address space allocated from a range | |
178 | * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. | |
179 | */ | |
180 | #define DIOBASE (0x600000) | |
181 | #define DIOTOP (0x1000000) | |
182 | #define DIOCSIZE (0x10000) | |
4534a638 KM |
183 | #define DIOIIBASE (0x01000000) |
184 | #define DIOIITOP (0x20000000) | |
185 | #define DIOIICSIZE (0x00400000) | |
186 | ||
9e153d67 MH |
187 | /* |
188 | * HP MMU | |
189 | */ | |
190 | #define MMUBASE IIOPOFF(0x5F4000) | |
4534a638 KM |
191 | #define MMUSSTP 0x0 |
192 | #define MMUUSTP 0x4 | |
193 | #define MMUTBINVAL 0x8 | |
194 | #define MMUSTAT 0xC | |
88a7e859 KM |
195 | #define MMUCMD MMUSTAT |
196 | ||
4534a638 KM |
197 | #define MMU_UMEN 0x0001 /* enable user mapping */ |
198 | #define MMU_SMEN 0x0002 /* enable supervisor mapping */ | |
199 | #define MMU_CEN 0x0004 /* enable data cache */ | |
200 | #define MMU_BERR 0x0008 /* bus error */ | |
201 | #define MMU_IEN 0x0020 /* enable instruction cache */ | |
202 | #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ | |
203 | #define MMU_WPF 0x2000 /* write protect fault */ | |
204 | #define MMU_PF 0x4000 /* page fault */ | |
205 | #define MMU_PTF 0x8000 /* page table fault */ | |
206 | ||
207 | #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) | |
208 | #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) | |
209 | ||
9e153d67 MH |
210 | /* |
211 | * 68851 and 68030 MMU | |
212 | */ | |
4534a638 KM |
213 | #define PMMU_LVLMASK 0x0007 |
214 | #define PMMU_INV 0x0400 | |
215 | #define PMMU_WP 0x0800 | |
216 | #define PMMU_ALV 0x1000 | |
217 | #define PMMU_SO 0x2000 | |
218 | #define PMMU_LV 0x4000 | |
219 | #define PMMU_BE 0x8000 | |
4534a638 KM |
220 | #define PMMU_FAULT (PMMU_WP|PMMU_INV) |
221 | ||
9acfa6cd MH |
222 | /* |
223 | * 68040 MMU | |
224 | */ | |
225 | #define MMU4_RES 0x001 | |
226 | #define MMU4_TTR 0x002 | |
227 | #define MMU4_WP 0x004 | |
228 | #define MMU4_MOD 0x010 | |
229 | #define MMU4_CMMASK 0x060 | |
230 | #define MMU4_SUP 0x080 | |
231 | #define MMU4_U0 0x100 | |
232 | #define MMU4_U1 0x200 | |
233 | #define MMU4_GLB 0x400 | |
234 | #define MMU4_BE 0x800 | |
235 | ||
4534a638 KM |
236 | /* 680X0 function codes */ |
237 | #define FC_USERD 1 /* user data space */ | |
238 | #define FC_USERP 2 /* user program space */ | |
239 | #define FC_PURGE 3 /* HPMMU: clear TLB entries */ | |
240 | #define FC_SUPERD 5 /* supervisor data space */ | |
241 | #define FC_SUPERP 6 /* supervisor program space */ | |
242 | #define FC_CPU 7 /* CPU space */ | |
88a7e859 KM |
243 | |
244 | /* fields in the 68020 cache control register */ | |
4534a638 KM |
245 | #define IC_ENABLE 0x0001 /* enable instruction cache */ |
246 | #define IC_FREEZE 0x0002 /* freeze instruction cache */ | |
247 | #define IC_CE 0x0004 /* clear instruction cache entry */ | |
248 | #define IC_CLR 0x0008 /* clear entire instruction cache */ | |
88a7e859 KM |
249 | |
250 | /* additional fields in the 68030 cache control register */ | |
4534a638 KM |
251 | #define IC_BE 0x0010 /* instruction burst enable */ |
252 | #define DC_ENABLE 0x0100 /* data cache enable */ | |
253 | #define DC_FREEZE 0x0200 /* data cache freeze */ | |
254 | #define DC_CE 0x0400 /* clear data cache entry */ | |
255 | #define DC_CLR 0x0800 /* clear entire data cache */ | |
256 | #define DC_BE 0x1000 /* data burst enable */ | |
257 | #define DC_WA 0x2000 /* write allocate */ | |
258 | ||
259 | #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) | |
260 | #define CACHE_OFF (DC_CLR|IC_CLR) | |
261 | #define CACHE_CLR (CACHE_ON) | |
262 | #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) | |
263 | #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) | |
9acfa6cd MH |
264 | |
265 | /* 68040 cache control register */ | |
266 | #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ | |
267 | #define DC4_ENABLE 0x80000000 /* data cache enable bit */ | |
268 | ||
269 | #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) | |
270 | #define CACHE4_OFF (0) |