[unix-history] / usr / src / sys / vax / uba / dh.c

/*	dh.c	4.11	%G%	*/

#include "dh.h"
#if NDH11 > 0
/*
 * DH-11 driver
 *
 * Loaded with dhdm if there are DM-11's otherwise with dhfdm.
 *
 * NB: WE HAVEN'T TESTED dhdm CODE ON VAX.
 */

#include "../h/param.h"
#include "../h/conf.h"
#include "../h/dir.h"
#include "../h/user.h"
#include "../h/tty.h"
#include "../h/map.h"
#include "../h/pte.h"
#include "../h/uba.h"
#include "../h/bk.h"
#include "../h/clist.h"
#include "../h/mx.h"

/*
 * When running dz's using only SAE (silo alarm) on input
 * it is necessary to call dzrint() at clock interrupt time.
 * This is unsafe unless spl5()s in tty code are changed to
 * spl6()s to block clock interrupts.  Note that the dh driver
 * currently in use works the same way as the dz, even though
 * we could try to more intelligently manage its silo.
 * Thus don't take this out if you have no dz's unless you
 * change clock.c and dhtimer().
 */
#define	spl5	spl6

#define	UBACVT(x) (cbase + (short)((x)-(char *)cfree))

struct	tty dh11[NDH11];
int	dhact;
int	dhisilo;
int	ndh11	= NDH11;
int	dhstart();
int	ttrstrt();
int	dh_ubinfo;
int	cbase;
int	getcbase;

/*
 * Hardware control bits
 */
#define	BITS6	01
#define	BITS7	02
#define	BITS8	03
#define	TWOSB	04
#define	PENABLE	020
/* DEC manuals incorrectly say this bit causes generation of even parity. */
#define	OPAR	040
#define	HDUPLX	040000

#define	IENAB	030100
#define	NXM	02000
#define	CLRNXM	0400
#define	PERROR	010000
#define	FRERROR	020000
#define	OVERRUN	040000
#define	XINT	0100000
#define	SSPEED	7	/* standard speed: 300 baud */

/*
 * DM control bits
 */
#define	TURNON	03	/* CD lead + line enable */
#define	TURNOFF	01	/* line enable */
#define	DTR	02	/* data terminal ready */
#define	RQS	04	/* request to send */

/*
 * Software copy of last dhbar
 */
short	dhsar[(NDH11+15)/16];

struct device
{
	union {
		short	dhcsr;
		char	dhcsrl;
	} un;
	short	dhnxch;
	short	dhlpr;
	unsigned short	dhcar;
	short	dhbcr;
	unsigned short	dhbar;
	short	dhbreak;
	short	dhsilo;
};

/*
 * Open a DH11 line.
 */
/*ARGSUSED*/
dhopen(dev, flag)
{
	register struct tty *tp;
	register d;
	register struct device *addr;
	int s;

	d = minor(dev) & 0177;
	if (d >= NDH11) {
		u.u_error = ENXIO;
		return;
	}
	tp = &dh11[d];
	addr = DHADDR;
	addr += d>>4;
	tp->t_addr = (caddr_t)addr;
	tp->t_oproc = dhstart;
	tp->t_iproc = NULL;
	tp->t_state |= WOPEN;
	s = spl6();
	if (!getcbase) {
		getcbase++;
		/* 512+ is a kludge to try to get around a hardware problem */
		dh_ubinfo = uballoc((caddr_t)cfree, 512+NCLIST*sizeof(struct cblock), 0);
		cbase = (short)dh_ubinfo;
	}
	splx(s);
	addr->un.dhcsr |= IENAB;
	dhact |= (1<<(d>>4));
	if ((tp->t_state&ISOPEN) == 0) {
		ttychars(tp);
		if (tp->t_ispeed == 0) {
			tp->t_ispeed = SSPEED;
			tp->t_ospeed = SSPEED;
			tp->t_flags = ODDP|EVENP|ECHO;
		}
		dhparam(d);
	}
	if (tp->t_state&XCLUDE && u.u_uid!=0) {
		u.u_error = EBUSY;
		return;
	}
	dmopen(dev);
	(*linesw[tp->t_line].l_open)(dev,tp);
}

/*
 * Close a DH11 line.
 */
/*ARGSUSED*/
dhclose(dev, flag)
dev_t dev;
int  flag;
{
	register struct tty *tp;
	register d;

	d = minor(dev) & 0177;
	tp = &dh11[d];
	(*linesw[tp->t_line].l_close)(tp);
	/*
	 * Turn of the break bit in case somebody did a TIOCSBRK without
	 * a TIOCCBRK.
	 */
	((struct device *)(tp->t_addr))->dhbreak &= ~(1<<(minor(dev)&017));
	if (tp->t_state&HUPCLS || (tp->t_state&ISOPEN)==0)
		dmctl(d, TURNOFF, DMSET);
	ttyclose(tp);
}

/*
 * Read from a DH11 line.
 */
dhread(dev)
{
register struct tty *tp;

	tp = &dh11[minor(dev) & 0177];
	(*linesw[tp->t_line].l_read)(tp);
}

/*
 * write on a DH11 line
 */
dhwrite(dev)
{
register struct tty *tp;

	tp = &dh11[minor(dev) & 0177];
	(*linesw[tp->t_line].l_write)(tp);
}

/*
 * DH11 receiver interrupt.
 */
dhrint(dev)
{
	register struct tty *tp;
	register short c;
	register struct device *addr;
	register struct tty *tp0;
	int s;

	s = spl6();	/* see comment in clock.c */
	addr = DHADDR;
	addr += minor(dev) & 0177;
	tp0 = &dh11[((minor(dev)&0177)<<4)];
	while ((c = addr->dhnxch) < 0) {	/* char. present */
		tp = tp0 + ((c>>8)&017);
		if (tp >= &dh11[NDH11])
			continue;
		if((tp->t_state&ISOPEN)==0) {
			wakeup((caddr_t)tp);
			continue;
		}
		if (c&PERROR)
			if ((tp->t_flags&(EVENP|ODDP))==EVENP
			 || (tp->t_flags&(EVENP|ODDP))==ODDP )
				continue;
		if (c&OVERRUN)
			printf("O");
		if (c&FRERROR)		/* break */
			if (tp->t_flags&RAW)
				c = 0;	/* null (for getty) */
			else
#ifdef IIASA
				continue;
#else
				c = tun.t_intrc;
#endif
		if (tp->t_line == NETLDISC) {
			c &= 0177;
			BKINPUT(c, tp);
		} else
			(*linesw[tp->t_line].l_rint)(c,tp);
	}
	splx(s);
}

/*
 * stty/gtty for DH11
 */
/*ARGSUSED*/
dhioctl(dev, cmd, addr, flag)
caddr_t addr;
{
	register struct tty *tp;

	tp = &dh11[minor(dev) & 0177];
	cmd = (*linesw[tp->t_line].l_ioctl)(tp, cmd, addr);
	if (cmd==0)
		return;
	if (ttioctl(tp, cmd, addr, flag)) {
		if (cmd==TIOCSETP||cmd==TIOCSETN)
			dhparam(dev);
	} else switch(cmd) {
	case TIOCSBRK:
		((struct device *)(tp->t_addr))->dhbreak |= 1<<(minor(dev)&017);
		break;
	case TIOCCBRK:
		((struct device *)(tp->t_addr))->dhbreak &= ~(1<<(minor(dev)&017));
		break;
	case TIOCSDTR:
		dmctl(minor(dev), DTR|RQS, DMBIS);
		break;
	case TIOCCDTR:
		dmctl(minor(dev), DTR|RQS, DMBIC);
		break;
	default:
		u.u_error = ENOTTY;
	}
}

/*
 * Set parameters from open or stty into the DH hardware
 * registers.
 */
dhparam(dev)
{
	register struct tty *tp;
	register struct device *addr;
	register d;
	int s;

	d = minor(dev) & 0177;
	tp = &dh11[d];
	addr = (struct device *)tp->t_addr;
	s = spl5();
	addr->un.dhcsrl = (d&017) | IENAB;
	/*
	 * Hang up line?
	 */
	if ((tp->t_ispeed)==0) {
		tp->t_state |= HUPCLS;
		dmctl(d, TURNOFF, DMSET);
		return;
	}
	d = ((tp->t_ospeed)<<10) | ((tp->t_ispeed)<<6);
	if ((tp->t_ispeed) == 4)		/* 134.5 baud */
		d |= BITS6|PENABLE|HDUPLX;
	else if ((tp->t_flag&RAW) || (tp->t_local&LLITOUT))
		d |= BITS8;
	else
		d |= BITS7|PENABLE;
	if ((tp->t_flags&EVENP) == 0)
		d |= OPAR;
	if ((tp->t_ospeed) == 3)	/* 110 baud */
		d |= TWOSB;
	addr->dhlpr = d;
	splx(s);
}

/*
 * DH11 transmitter interrupt.
 * Restart each line which used to be active but has
 * terminated transmission since the last interrupt.
 */
dhxint(dev)
{
	register struct tty *tp;
	register struct device *addr;
	register d;
	short ttybit, bar, *sbar;
	int s;

	s = spl6();	/* block the clock */
	d = minor(dev) & 0177;
	addr = DHADDR + d;
	addr->un.dhcsr &= (short)~XINT;
	if (addr->un.dhcsr & NXM) {
		addr->un.dhcsr |= CLRNXM;
		printf("dh clr NXM\n");
	}
	sbar = &dhsar[d];
	bar = *sbar & ~addr->dhbar;
	d <<= 4; ttybit = 1;

	for(; bar; d++, ttybit <<= 1) {
		if(bar&ttybit) {
			*sbar &= ~ttybit;
			bar &= ~ttybit;
			tp = &dh11[d];
			tp->t_state &= ~BUSY;
			if (tp->t_state&FLUSH)
				tp->t_state &= ~FLUSH;
			else {
				addr->un.dhcsrl = (d&017)|IENAB;
				ndflush(&tp->t_outq,
				    (int)(short)addr->dhcar-UBACVT(tp->t_outq.c_cf));
			}
			if (tp->t_line)
				(*linesw[tp->t_line].l_start)(tp);
			else
				dhstart(tp);
		}
	}
	splx(s);
}

/*
 * Start (restart) transmission on the given DH11 line.
 */
dhstart(tp)
register struct tty *tp;
{
	register struct device *addr;
	register short nch;
	int s, d;

	/*
	 * If it's currently active, or delaying,
	 * no need to do anything.
	 */
	s = spl5();
	d = tp-dh11;
	addr = (struct device *)tp->t_addr;
	if (tp->t_state&(TIMEOUT|BUSY|TTSTOP))
		goto out;

	/*
	 * If the writer was sleeping on output overflow,
	 * wake him when low tide is reached.
	 */
	if (tp->t_state&ASLEEP && tp->t_outq.c_cc<=TTLOWAT(tp)) {
		tp->t_state &= ~ASLEEP;
		if (tp->t_chan)
			mcstart(tp->t_chan, (caddr_t)&tp->t_outq);
		else
			wakeup((caddr_t)&tp->t_outq);
	}

	if (tp->t_outq.c_cc == 0)
		goto out;

	/*
	 * Find number of characters to transfer.
	 */
	if (tp->t_flags & RAW) {
		nch = ndqb(&tp->t_outq, 0);
	} else {
		nch = ndqb(&tp->t_outq, 0200);
		if (nch == 0) {
			nch = getc(&tp->t_outq);
			timeout(ttrstrt, (caddr_t)tp, (nch&0177)+6);
			tp->t_state |= TIMEOUT;
			goto out;
		}
	}
	/*
	 * If any characters were set up, start transmission;
	 */
	if (nch) {
		addr->un.dhcsrl = (d&017)|IENAB;
		addr->dhcar = UBACVT(tp->t_outq.c_cf);
		addr->dhbcr = -nch;
		nch = 1<<(d&017);
		addr->dhbar |= nch;
		dhsar[d>>4] |= nch;
		tp->t_state |= BUSY;
	}
    out:
	splx(s);
}

/*
 * Stop output on a line.
 * Assume call is made at spl6.
 */
/*ARGSUSED*/
dhstop(tp, flag)
register struct tty *tp;
{
	register struct device *addr;
	register d, s;

	addr = (struct device *)tp->t_addr;
	s = spl6();
	if (tp->t_state & BUSY) {
		d = minor(tp->t_dev);
		addr->un.dhcsrl = (d&017) | IENAB;
		if ((tp->t_state&TTSTOP)==0)
			tp->t_state |= FLUSH;
		addr->dhbcr = -1;
	}
	splx(s);
}

int	dhsilo = 16;
/*
 * Silo control is fixed strategy
 * here, paralleling only option available
 * on DZ-11.
 */
/*ARGSUSED*/
dhtimer()
{
	register d;
	register struct device *addr;

	addr = DHADDR; d = 0;
	do {
		if (dhact & (1<<d)) {
			if ((dhisilo & (1<<d)) == 0) {
				addr->dhsilo = dhsilo;
				dhisilo |= 1<<d;
			}
			dhrint(d);
		}
		d++;
		addr++;
	} while (d < (NDH11+15)/16);
}

/*
 * Reset state of driver if UBA reset was necessary.
 * Reset the csrl and lpr registers on open lines, and
 * restart transmitters.
 */
dhreset()
{
	int d;
	register struct tty *tp;
	register struct device *addr;

	if (getcbase == 0)
		return;
	printf(" dh");
	dhisilo = 0;
	ubarelse(&dh_ubinfo);
	dh_ubinfo = uballoc((caddr_t)cfree, NCLIST*sizeof (struct cblock), 0);
	cbase = (short)dh_ubinfo;
	d = 0;
	do {
		addr = DHADDR + d;
		if (dhact & (1<<d))
			addr->un.dhcsr |= IENAB;
		d++;
	} while (d < (NDH11+15)/16);
	for (d = 0; d < NDH11; d++) {
		tp = &dh11[d];
		if (tp->t_state & (ISOPEN|WOPEN)) {
			dhparam(d);
			dmctl(d, TURNON, DMSET);
			tp->t_state &= ~BUSY;
			dhstart(tp);
		}
	}
	dhtimer();
}
#if DHDM > 0
#include "../dev/dhdm.c"
#else
#include "../dev/dhfdm.c"
#endif
#endif
Commit	Line	Data
be5b7974	1	/* dh.c 4.11 %G% */
a18f326f	2
66b4fb09	3	#include "dh.h"
a5cc519e	4	#if NDH11 > 0
a18f326f	5	/*
a5cc519e BJ	6	* DH-11 driver
	7	*
	8	* Loaded with dhdm if there are DM-11's otherwise with dhfdm.
	9	*
	10	* NB: WE HAVEN'T TESTED dhdm CODE ON VAX.
a18f326f BJ	11	*/
	12
	13	#include "../h/param.h"
	14	#include "../h/conf.h"
	15	#include "../h/dir.h"
	16	#include "../h/user.h"
	17	#include "../h/tty.h"
	18	#include "../h/map.h"
	19	#include "../h/pte.h"
	20	#include "../h/uba.h"
038bbe6b	21	#include "../h/bk.h"
a5cc519e	22	#include "../h/clist.h"
1b05b375	23	#include "../h/mx.h"
a18f326f	24
d3ebf5ee BJ	25	/*
	26	* When running dz's using only SAE (silo alarm) on input
	27	* it is necessary to call dzrint() at clock interrupt time.
	28	* This is unsafe unless spl5()s in tty code are changed to
	29	* spl6()s to block clock interrupts. Note that the dh driver
	30	* currently in use works the same way as the dz, even though
	31	* we could try to more intelligently manage its silo.
	32	* Thus don't take this out if you have no dz's unless you
	33	* change clock.c and dhtimer().
	34	*/
	35	#define spl5 spl6
	36
a5cc519e	37	#define UBACVT(x) (cbase + (short)((x)-(char *)cfree))
a18f326f BJ	38
a18f326f BJ	39	struct tty dh11[NDH11];
0e239190	40	int dhact;
5c30d566	41	int dhisilo;
a18f326f BJ	42	int ndh11 = NDH11;
	43	int dhstart();
	44	int ttrstrt();
5c30d566 BJ	45	int dh_ubinfo;
	46	int cbase;
	47	int getcbase;
a18f326f BJ	48
	49	/*
	50	* Hardware control bits
	51	*/
	52	#define BITS6 01
	53	#define BITS7 02
	54	#define BITS8 03
	55	#define TWOSB 04
	56	#define PENABLE 020
	57	/* DEC manuals incorrectly say this bit causes generation of even parity. */
	58	#define OPAR 040
	59	#define HDUPLX 040000
	60
	61	#define IENAB 030100
b4ec79ea BJ	62	#define NXM 02000
b4ec79ea BJ	63	#define CLRNXM 0400
a18f326f BJ	64	#define PERROR 010000
	65	#define FRERROR 020000
	66	#define OVERRUN 040000
	67	#define XINT 0100000
	68	#define SSPEED 7 /* standard speed: 300 baud */
	69
a18f326f BJ	70	/*
	71	* DM control bits
	72	*/
	73	#define TURNON 03 /* CD lead + line enable */
	74	#define TURNOFF 01 /* line enable */
87f51a66	75	#define DTR 02 /* data terminal ready */
a18f326f BJ	76	#define RQS 04 /* request to send */
	77
	78	/*
	79	* Software copy of last dhbar
	80	*/
	81	short dhsar[(NDH11+15)/16];
	82
	83	struct device
	84	{
	85	union {
	86	short dhcsr;
	87	char dhcsrl;
	88	} un;
	89	short dhnxch;
	90	short dhlpr;
	91	unsigned short dhcar;
	92	short dhbcr;
	93	unsigned short dhbar;
	94	short dhbreak;
	95	short dhsilo;
	96	};
	97
	98	/*
	99	* Open a DH11 line.
	100	*/
	101	/ARGSUSED/
	102	dhopen(dev, flag)
	103	{
	104	register struct tty *tp;
	105	register d;
	106	register struct device *addr;
a18f326f BJ	107	int s;
	108
	109	d = minor(dev) & 0177;
	110	if (d >= NDH11) {
	111	u.u_error = ENXIO;
	112	return;
	113	}
	114	tp = &dh11[d];
	115	addr = DHADDR;
	116	addr += d>>4;
	117	tp->t_addr = (caddr_t)addr;
	118	tp->t_oproc = dhstart;
	119	tp->t_iproc = NULL;
	120	tp->t_state \|= WOPEN;
	121	s = spl6();
0e239190 BJ	122	if (!getcbase) {
0e239190 BJ	123	getcbase++;
d319892b BJ	124	/* 512+ is a kludge to try to get around a hardware problem */
d319892b BJ	125	dh_ubinfo = uballoc((caddr_t)cfree, 512+NCLIST*sizeof(struct cblock), 0);
5c30d566	126	cbase = (short)dh_ubinfo;
a18f326f BJ	127	}
	128	splx(s);
	129	addr->un.dhcsr \|= IENAB;
0e239190	130	dhact \|= (1<<(d>>4));
a18f326f BJ	131	if ((tp->t_state&ISOPEN) == 0) {
a18f326f BJ	132	ttychars(tp);
87f51a66 BJ	133	if (tp->t_ispeed == 0) {
	134	tp->t_ispeed = SSPEED;
	135	tp->t_ospeed = SSPEED;
	136	tp->t_flags = ODDP\|EVENP\|ECHO;
	137	}
a18f326f BJ	138	dhparam(d);
	139	}
	140	if (tp->t_state&XCLUDE && u.u_uid!=0) {
	141	u.u_error = EBUSY;
	142	return;
	143	}
	144	dmopen(dev);
	145	(*linesw[tp->t_line].l_open)(dev,tp);
	146	}
	147
	148	/*
	149	* Close a DH11 line.
	150	*/
	151	/ARGSUSED/
	152	dhclose(dev, flag)
	153	dev_t dev;
	154	int flag;
	155	{
	156	register struct tty *tp;
	157	register d;
	158
	159	d = minor(dev) & 0177;
	160	tp = &dh11[d];
	161	(*linesw[tp->t_line].l_close)(tp);
8196703b MT	162	/*
	163	* Turn of the break bit in case somebody did a TIOCSBRK without
	164	* a TIOCCBRK.
	165	*/
	166	((struct device *)(tp->t_addr))->dhbreak &= ~(1<<(minor(dev)&017));
a18f326f	167	if (tp->t_state&HUPCLS \|\| (tp->t_state&ISOPEN)==0)
87f51a66	168	dmctl(d, TURNOFF, DMSET);
a18f326f BJ	169	ttyclose(tp);
	170	}
	171
	172	/*
	173	* Read from a DH11 line.
	174	*/
	175	dhread(dev)
	176	{
	177	register struct tty *tp;
	178
	179	tp = &dh11[minor(dev) & 0177];
	180	(*linesw[tp->t_line].l_read)(tp);
	181	}
	182
	183	/*
	184	* write on a DH11 line
	185	*/
	186	dhwrite(dev)
	187	{
	188	register struct tty *tp;
	189
	190	tp = &dh11[minor(dev) & 0177];
	191	(*linesw[tp->t_line].l_write)(tp);
	192	}
	193
	194	/*
	195	* DH11 receiver interrupt.
	196	*/
	197	dhrint(dev)
	198	{
	199	register struct tty *tp;
	200	register short c;
	201	register struct device *addr;
0e239190	202	register struct tty *tp0;
5c6adb3e	203	int s;
a18f326f	204
5c6adb3e	205	s = spl6(); /* see comment in clock.c */
a18f326f BJ	206	addr = DHADDR;
a18f326f BJ	207	addr += minor(dev) & 0177;
0e239190	208	tp0 = &dh11[((minor(dev)&0177)<<4)];
a18f326f	209	while ((c = addr->dhnxch) < 0) { /* char. present */
0e239190	210	tp = tp0 + ((c>>8)&017);
a18f326f BJ	211	if (tp >= &dh11[NDH11])
	212	continue;
	213	if((tp->t_state&ISOPEN)==0) {
	214	wakeup((caddr_t)tp);
	215	continue;
	216	}
	217	if (c&PERROR)
	218	if ((tp->t_flags&(EVENP\|ODDP))==EVENP
	219	\|\| (tp->t_flags&(EVENP\|ODDP))==ODDP )
	220	continue;
	221	if (c&OVERRUN)
	222	printf("O");
	223	if (c&FRERROR) /* break */
	224	if (tp->t_flags&RAW)
	225	c = 0; /* null (for getty) */
	226	else
87f51a66 BJ	227	#ifdef IIASA
	228	continue;
	229	#else
1c17c385	230	c = tun.t_intrc;
87f51a66	231	#endif
5c6adb3e	232	if (tp->t_line == NETLDISC) {
0e239190	233	c &= 0177;
87f51a66	234	BKINPUT(c, tp);
0e239190	235	} else
0e239190	236	(*linesw[tp->t_line].l_rint)(c,tp);
a18f326f	237	}
5c6adb3e	238	splx(s);
a18f326f BJ	239	}
	240
	241	/*
	242	* stty/gtty for DH11
	243	*/
	244	/ARGSUSED/
	245	dhioctl(dev, cmd, addr, flag)
	246	caddr_t addr;
	247	{
	248	register struct tty *tp;
	249
	250	tp = &dh11[minor(dev) & 0177];
038bbe6b BJ	251	cmd = (*linesw[tp->t_line].l_ioctl)(tp, cmd, addr);
	252	if (cmd==0)
	253	return;
f4e18828	254	if (ttioctl(tp, cmd, addr, flag)) {
a18f326f BJ	255	if (cmd==TIOCSETP\|\|cmd==TIOCSETN)
a18f326f BJ	256	dhparam(dev);
87f51a66 BJ	257	} else switch(cmd) {
	258	case TIOCSBRK:
	259	((struct device *)(tp->t_addr))->dhbreak \|= 1<<(minor(dev)&017);
	260	break;
	261	case TIOCCBRK:
	262	((struct device *)(tp->t_addr))->dhbreak &= ~(1<<(minor(dev)&017));
	263	break;
	264	case TIOCSDTR:
	265	dmctl(minor(dev), DTR\|RQS, DMBIS);
	266	break;
	267	case TIOCCDTR:
	268	dmctl(minor(dev), DTR\|RQS, DMBIC);
	269	break;
	270	default:
a18f326f	271	u.u_error = ENOTTY;
87f51a66	272	}
a18f326f BJ	273	}
	274
	275	/*
	276	* Set parameters from open or stty into the DH hardware
	277	* registers.
	278	*/
	279	dhparam(dev)
	280	{
	281	register struct tty *tp;
	282	register struct device *addr;
	283	register d;
0072a3c2	284	int s;
a18f326f BJ	285
	286	d = minor(dev) & 0177;
	287	tp = &dh11[d];
	288	addr = (struct device *)tp->t_addr;
0072a3c2	289	s = spl5();
a18f326f BJ	290	addr->un.dhcsrl = (d&017) \| IENAB;
	291	/*
	292	* Hang up line?
	293	*/
	294	if ((tp->t_ispeed)==0) {
	295	tp->t_state \|= HUPCLS;
87f51a66	296	dmctl(d, TURNOFF, DMSET);
a18f326f BJ	297	return;
	298	}
	299	d = ((tp->t_ospeed)<<10) \| ((tp->t_ispeed)<<6);
	300	if ((tp->t_ispeed) == 4) /* 134.5 baud */
	301	d \|= BITS6\|PENABLE\|HDUPLX;
be5b7974	302	else if ((tp->t_flag&RAW) \|\| (tp->t_local&LLITOUT))
a18f326f BJ	303	d \|= BITS8;
	304	else
	305	d \|= BITS7\|PENABLE;
	306	if ((tp->t_flags&EVENP) == 0)
	307	d \|= OPAR;
	308	if ((tp->t_ospeed) == 3) /* 110 baud */
	309	d \|= TWOSB;
	310	addr->dhlpr = d;
0072a3c2	311	splx(s);
a18f326f BJ	312	}
	313
	314	/*
	315	* DH11 transmitter interrupt.
	316	* Restart each line which used to be active but has
	317	* terminated transmission since the last interrupt.
	318	*/
	319	dhxint(dev)
	320	{
	321	register struct tty *tp;
	322	register struct device *addr;
	323	register d;
	324	short ttybit, bar, *sbar;
d3ebf5ee	325	int s;
a18f326f	326
d3ebf5ee	327	s = spl6(); /* block the clock */
a18f326f BJ	328	d = minor(dev) & 0177;
	329	addr = DHADDR + d;
	330	addr->un.dhcsr &= (short)~XINT;
b4ec79ea BJ	331	if (addr->un.dhcsr & NXM) {
	332	addr->un.dhcsr \|= CLRNXM;
	333	printf("dh clr NXM\n");
	334	}
a18f326f BJ	335	sbar = &dhsar[d];
	336	bar = *sbar & ~addr->dhbar;
	337	d <<= 4; ttybit = 1;
	338
	339	for(; bar; d++, ttybit <<= 1) {
	340	if(bar&ttybit) {
	341	*sbar &= ~ttybit;
	342	bar &= ~ttybit;
	343	tp = &dh11[d];
038bbe6b BJ	344	tp->t_state &= ~BUSY;
	345	if (tp->t_state&FLUSH)
	346	tp->t_state &= ~FLUSH;
	347	else {
a18f326f	348	addr->un.dhcsrl = (d&017)\|IENAB;
293c7069	349	ndflush(&tp->t_outq,
4905b7c3	350	(int)(short)addr->dhcar-UBACVT(tp->t_outq.c_cf));
a18f326f	351	}
038bbe6b BJ	352	if (tp->t_line)
	353	(*linesw[tp->t_line].l_start)(tp);
	354	else
	355	dhstart(tp);
a18f326f BJ	356	}
a18f326f BJ	357	}
d3ebf5ee	358	splx(s);
a18f326f BJ	359	}
	360
	361	/*
	362	* Start (restart) transmission on the given DH11 line.
	363	*/
	364	dhstart(tp)
	365	register struct tty *tp;
	366	{
	367	register struct device *addr;
	368	register short nch;
	369	int s, d;
	370
	371	/*
	372	* If it's currently active, or delaying,
	373	* no need to do anything.
	374	*/
	375	s = spl5();
	376	d = tp-dh11;
	377	addr = (struct device *)tp->t_addr;
	378	if (tp->t_state&(TIMEOUT\|BUSY\|TTSTOP))
	379	goto out;
	380
a18f326f BJ	381	/*
	382	* If the writer was sleeping on output overflow,
	383	* wake him when low tide is reached.
	384	*/
b25a5292	385	if (tp->t_state&ASLEEP && tp->t_outq.c_cc<=TTLOWAT(tp)) {
a18f326f BJ	386	tp->t_state &= ~ASLEEP;
a18f326f BJ	387	if (tp->t_chan)
87f51a66 BJ	388	mcstart(tp->t_chan, (caddr_t)&tp->t_outq);
87f51a66 BJ	389	else
a18f326f BJ	390	wakeup((caddr_t)&tp->t_outq);
	391	}
	392
	393	if (tp->t_outq.c_cc == 0)
	394	goto out;
	395
a18f326f BJ	396	/*
	397	* Find number of characters to transfer.
	398	*/
	399	if (tp->t_flags & RAW) {
	400	nch = ndqb(&tp->t_outq, 0);
	401	} else {
	402	nch = ndqb(&tp->t_outq, 0200);
	403	if (nch == 0) {
	404	nch = getc(&tp->t_outq);
	405	timeout(ttrstrt, (caddr_t)tp, (nch&0177)+6);
	406	tp->t_state \|= TIMEOUT;
	407	goto out;
	408	}
	409	}
	410	/*
	411	* If any characters were set up, start transmission;
	412	*/
	413	if (nch) {
	414	addr->un.dhcsrl = (d&017)\|IENAB;
	415	addr->dhcar = UBACVT(tp->t_outq.c_cf);
	416	addr->dhbcr = -nch;
a18f326f BJ	417	nch = 1<<(d&017);
	418	addr->dhbar \|= nch;
	419	dhsar[d>>4] \|= nch;
	420	tp->t_state \|= BUSY;
	421	}
	422	out:
	423	splx(s);
	424	}
	425
a18f326f BJ	426	/*
	427	* Stop output on a line.
	428	* Assume call is made at spl6.
	429	*/
	430	/ARGSUSED/
	431	dhstop(tp, flag)
	432	register struct tty *tp;
	433	{
038bbe6b BJ	434	register struct device *addr;
038bbe6b BJ	435	register d, s;
a18f326f	436
038bbe6b	437	addr = (struct device *)tp->t_addr;
a18f326f	438	s = spl6();
038bbe6b BJ	439	if (tp->t_state & BUSY) {
	440	d = minor(tp->t_dev);
	441	addr->un.dhcsrl = (d&017) \| IENAB;
a18f326f BJ	442	if ((tp->t_state&TTSTOP)==0)
a18f326f BJ	443	tp->t_state \|= FLUSH;
038bbe6b BJ	444	addr->dhbcr = -1;
038bbe6b BJ	445	}
a18f326f BJ	446	splx(s);
	447	}
	448
0e239190	449	int dhsilo = 16;
87f51a66 BJ	450	/*
	451	* Silo control is fixed strategy
	452	* here, paralleling only option available
	453	* on DZ-11.
	454	*/
a18f326f	455	/ARGSUSED/
87f51a66	456	dhtimer()
a18f326f	457	{
87f51a66	458	register d;
0e239190 BJ	459	register struct device *addr;
0e239190 BJ	460
a18f326f BJ	461	addr = DHADDR; d = 0;
a18f326f BJ	462	do {
0e239190	463	if (dhact & (1<<d)) {
5c30d566 BJ	464	if ((dhisilo & (1<<d)) == 0) {
	465	addr->dhsilo = dhsilo;
	466	dhisilo \|= 1<<d;
	467	}
0e239190 BJ	468	dhrint(d);
	469	}
	470	d++;
a18f326f	471	addr++;
a18f326f	472	} while (d < (NDH11+15)/16);
a18f326f	473	}
5c30d566 BJ	474
	475	/*
	476	* Reset state of driver if UBA reset was necessary.
	477	* Reset the csrl and lpr registers on open lines, and
	478	* restart transmitters.
	479	*/
	480	dhreset()
	481	{
	482	int d;
	483	register struct tty *tp;
	484	register struct device *addr;
	485
	486	if (getcbase == 0)
	487	return;
	488	printf(" dh");
5c30d566	489	dhisilo = 0;
b28deaf8	490	ubarelse(&dh_ubinfo);
5c30d566 BJ	491	dh_ubinfo = uballoc((caddr_t)cfree, NCLIST*sizeof (struct cblock), 0);
5c30d566 BJ	492	cbase = (short)dh_ubinfo;
5c30d566 BJ	493	d = 0;
	494	do {
	495	addr = DHADDR + d;
5c30d566	496	if (dhact & (1<<d))
0072a3c2	497	addr->un.dhcsr \|= IENAB;
5c30d566 BJ	498	d++;
5c30d566 BJ	499	} while (d < (NDH11+15)/16);
0072a3c2 BJ	500	for (d = 0; d < NDH11; d++) {
	501	tp = &dh11[d];
	502	if (tp->t_state & (ISOPEN\|WOPEN)) {
	503	dhparam(d);
	504	dmctl(d, TURNON, DMSET);
	505	tp->t_state &= ~BUSY;
	506	dhstart(tp);
	507	}
	508	}
	509	dhtimer();
5c30d566	510	}
ea99d5bf BJ	511	#if DHDM > 0
	512	#include "../dev/dhdm.c"
	513	#else
	514	#include "../dev/dhfdm.c"
	515	#endif
ae7f533a	516	#endif