[unix-history] / sys / i386 / netboot / ether.h

/**************************************************************************
NETBOOT -  BOOTP/TFTP Bootstrap Program

Author: Martin Renters
  Date: Jun/94

**************************************************************************/

#define TRUE		1
#define FALSE		0

#define ETH_MIN_PACKET	64
#define ETH_MAX_PACKET	1518

#define VENDOR_NONE	0
#define VENDOR_WD	1
#define VENDOR_NOVELL	2

#define FLAG_PIO	0x01
#define FLAG_16BIT	0x02
#define FLAG_790	0x04

#define MEM_8192	32
#define MEM_16384	64
#define MEM_32768	128

/**************************************************************************
Western Digital/SMC Board Definitions
**************************************************************************/
#define WD_LOW_BASE	0x200
#define WD_HIGH_BASE	0x3e0
#ifndef WD_DEFAULT_MEM
#define WD_DEFAULT_MEM	0xD0000
#endif
#define WD_NIC_ADDR	0x10

/**************************************************************************
Western Digital/SMC ASIC Addresses
**************************************************************************/
#define WD_MSR		0x00
#define WD_ICR		0x01
#define WD_IAR		0x02
#define WD_BIO		0x03
#define WD_IRR		0x04
#define WD_LAAR		0x05
#define WD_IJR		0x06
#define WD_GP2		0x07
#define WD_LAR		0x08
#define WD_BID		0x0E

#define WD_ICR_16BIT	0x01

#define WD_MSR_MENB	0x40

#define WD_LAAR_L16EN	0x40
#define WD_LAAR_M16EN	0x80

#define WD_SOFTCONFIG	0x20

/**************************************************************************
Western Digital/SMC Board Types
**************************************************************************/
#define TYPE_WD8003S	0x02
#define TYPE_WD8003E	0x03
#define TYPE_WD8013EBT	0x05
#define TYPE_WD8003W	0x24
#define TYPE_WD8003EB	0x25
#define TYPE_WD8013W	0x26
#define TYPE_WD8013EP	0x27
#define TYPE_WD8013WC	0x28
#define TYPE_WD8013EPC	0x29
#define TYPE_SMC8216T	0x2a
#define TYPE_SMC8216C	0x2b
#define TYPE_SMC8013EBP	0x2c

#ifdef INCLUDE_WD
struct wd_board {
	char *name;
	char id;
	char flags;
	char memsize;
} wd_boards[] = {
	{"WD8003S",	TYPE_WD8003S,	0,			MEM_8192},
	{"WD8003E",	TYPE_WD8003E,	0,			MEM_8192},
	{"WD8013EBT",	TYPE_WD8013EBT,	FLAG_16BIT,		MEM_16384},
	{"WD8003W",	TYPE_WD8003W,	0,			MEM_8192},
	{"WD8003EB",	TYPE_WD8003EB,	0,			MEM_8192},
	{"WD8013W",	TYPE_WD8013W,	FLAG_16BIT,		MEM_16384},
	{"WD8003EP/WD8013EP",
			TYPE_WD8013EP,	0,			MEM_8192},
	{"WD8013WC",	TYPE_WD8013WC,	FLAG_16BIT,		MEM_16384},
	{"WD8013EPC",	TYPE_WD8013EPC,	FLAG_16BIT,		MEM_16384},
	{"SMC8216T",	TYPE_SMC8216T,	FLAG_16BIT | FLAG_790,	MEM_16384},
	{"SMC8216C",	TYPE_SMC8216C,	FLAG_16BIT | FLAG_790,	MEM_16384},
	{"SMC8013EBP",	TYPE_SMC8013EBP,FLAG_16BIT,		MEM_16384},
	{NULL,		0,		0}
};
#endif

/**************************************************************************
NE1000/2000 definitions
**************************************************************************/
#ifndef NE_BASE
#define NE_BASE		0x320
#endif
#define NE_ASIC_OFFSET	0x10
#define NE_RESET	0x0F		/* Used to reset card */
#define NE_DATA		0x00		/* Used to read/write NIC mem */

/**************************************************************************
8390 Register Definitions
**************************************************************************/
#define D8390_P0_COMMAND	0x00
#define D8390_P0_PSTART		0x01
#define D8390_P0_PSTOP		0x02
#define D8390_P0_BOUND		0x03
#define D8390_P0_TSR		0x04
#define	D8390_P0_TPSR		0x04
#define D8390_P0_TBCR0		0x05
#define D8390_P0_TBCR1		0x06
#define D8390_P0_ISR		0x07
#define D8390_P0_RSAR0		0x08
#define D8390_P0_RSAR1		0x09
#define D8390_P0_RBCR0		0x0A
#define D8390_P0_RBCR1		0x0B
#define D8390_P0_RSR		0x0C
#define D8390_P0_RCR		0x0C
#define D8390_P0_TCR		0x0D
#define D8390_P0_DCR		0x0E
#define D8390_P0_IMR		0x0F
#define D8390_P1_COMMAND	0x00
#define D8390_P1_PAR0		0x01
#define D8390_P1_PAR1		0x02
#define D8390_P1_PAR2		0x03
#define D8390_P1_PAR3		0x04
#define D8390_P1_PAR4		0x05
#define D8390_P1_PAR5		0x06
#define D8390_P1_CURR		0x07
#define D8390_P1_MAR0		0x08

#define D8390_COMMAND_PS0	0x0		/* Page 0 select */
#define D8390_COMMAND_PS1	0x40		/* Page 1 select */
#define D8390_COMMAND_PS2	0x80		/* Page 2 select */
#define	D8390_COMMAND_RD2	0x20		/* Remote DMA control */
#define D8390_COMMAND_RD1	0x10
#define D8390_COMMAND_RD0	0x08
#define D8390_COMMAND_TXP	0x04		/* transmit packet */
#define D8390_COMMAND_STA	0x02		/* start */
#define D8390_COMMAND_STP	0x01		/* stop */

#define D8390_RCR_MON		0x20		/* monitor mode */

#define D8390_DCR_FT1		0x40
#define D8390_DCR_LS		0x08		/* Loopback select */
#define D8390_DCR_WTS		0x01		/* Word transfer select */

#define D8390_ISR_PRX		0x01		/* successful recv */
#define D8390_ISR_PTX		0x02		/* successful xmit */
#define D8390_ISR_RXE		0x04		/* receive error */
#define D8390_ISR_TXE		0x08		/* transmit error */
#define D8390_ISR_OVW		0x10		/* Overflow */
#define D8390_ISR_CNT		0x20		/* Counter overflow */
#define D8390_ISR_RDC		0x40		/* Remote DMA complete */
#define D8390_ISR_RST		0x80		/* reset */

#define D8390_RSTAT_PRX		0x01		/* successful recv */
#define D8390_RSTAT_CRC		0x02		/* CRC error */
#define D8390_RSTAT_FAE		0x04		/* Frame alignment error */
#define D8390_RSTAT_OVER	0x08		/* overflow */

#define D8390_TXBUF_SIZE	6
#define D8390_RXBUF_END		32

struct ringbuffer {
	unsigned char status;
	unsigned char bound;
	unsigned short len;
};
Commit	Line	Data
86e2ea7e MR	1	/**************************************************************************
	2	NETBOOT - BOOTP/TFTP Bootstrap Program
	3
	4	Author: Martin Renters
	5	Date: Jun/94
	6
	7	**************************************************************************/
	8
	9	#define TRUE 1
	10	#define FALSE 0
	11
	12	#define ETH_MIN_PACKET 64
	13	#define ETH_MAX_PACKET 1518
	14
	15	#define VENDOR_NONE 0
	16	#define VENDOR_WD 1
	17	#define VENDOR_NOVELL 2
	18
	19	#define FLAG_PIO 0x01
	20	#define FLAG_16BIT 0x02
	21	#define FLAG_790 0x04
	22
	23	#define MEM_8192 32
	24	#define MEM_16384 64
	25	#define MEM_32768 128
	26
	27	/**************************************************************************
	28	Western Digital/SMC Board Definitions
	29	**************************************************************************/
	30	#define WD_LOW_BASE 0x200
	31	#define WD_HIGH_BASE 0x3e0
	32	#ifndef WD_DEFAULT_MEM
	33	#define WD_DEFAULT_MEM 0xD0000
	34	#endif
	35	#define WD_NIC_ADDR 0x10
	36
	37	/**************************************************************************
	38	Western Digital/SMC ASIC Addresses
	39	**************************************************************************/
	40	#define WD_MSR 0x00
	41	#define WD_ICR 0x01
	42	#define WD_IAR 0x02
	43	#define WD_BIO 0x03
	44	#define WD_IRR 0x04
	45	#define WD_LAAR 0x05
	46	#define WD_IJR 0x06
	47	#define WD_GP2 0x07
	48	#define WD_LAR 0x08
	49	#define WD_BID 0x0E
	50
	51	#define WD_ICR_16BIT 0x01
	52
	53	#define WD_MSR_MENB 0x40
	54
	55	#define WD_LAAR_L16EN 0x40
	56	#define WD_LAAR_M16EN 0x80
	57
	58	#define WD_SOFTCONFIG 0x20
	59
	60	/**************************************************************************
	61	Western Digital/SMC Board Types
	62	**************************************************************************/
	63	#define TYPE_WD8003S 0x02
	64	#define TYPE_WD8003E 0x03
65	#define TYPE_WD8013EBT 0x05
66	#define TYPE_WD8003W 0x24
67	#define TYPE_WD8003EB 0x25
68	#define TYPE_WD8013W 0x26
69	#define TYPE_WD8013EP 0x27
70	#define TYPE_WD8013WC 0x28
71	#define TYPE_WD8013EPC 0x29
72	#define TYPE_SMC8216T 0x2a
73	#define TYPE_SMC8216C 0x2b
74	#define TYPE_SMC8013EBP 0x2c
75
76	#ifdef INCLUDE_WD
77	struct wd_board {
78	char *name;
79	char id;
80	char flags;
81	char memsize;
82	} wd_boards[] = {
83	{"WD8003S", TYPE_WD8003S, 0, MEM_8192},
84	{"WD8003E", TYPE_WD8003E, 0, MEM_8192},
85	{"WD8013EBT", TYPE_WD8013EBT, FLAG_16BIT, MEM_16384},
86	{"WD8003W", TYPE_WD8003W, 0, MEM_8192},
87	{"WD8003EB", TYPE_WD8003EB, 0, MEM_8192},
88	{"WD8013W", TYPE_WD8013W, FLAG_16BIT, MEM_16384},
89	{"WD8003EP/WD8013EP",
90	TYPE_WD8013EP, 0, MEM_8192},
91	{"WD8013WC", TYPE_WD8013WC, FLAG_16BIT, MEM_16384},
92	{"WD8013EPC", TYPE_WD8013EPC, FLAG_16BIT, MEM_16384},
93	{"SMC8216T", TYPE_SMC8216T, FLAG_16BIT \| FLAG_790, MEM_16384},
94	{"SMC8216C", TYPE_SMC8216C, FLAG_16BIT \| FLAG_790, MEM_16384},
95	{"SMC8013EBP", TYPE_SMC8013EBP,FLAG_16BIT, MEM_16384},
96	{NULL, 0, 0}
97	};
98	#endif
99
100	/**************************************************************************
101	NE1000/2000 definitions
102	**************************************************************************/
103	#ifndef NE_BASE
104	#define NE_BASE 0x320
105	#endif
106	#define NE_ASIC_OFFSET 0x10
107	#define NE_RESET 0x0F /* Used to reset card */
108	#define NE_DATA 0x00 /* Used to read/write NIC mem */
109
110	/**************************************************************************
111	8390 Register Definitions
112	**************************************************************************/
113	#define D8390_P0_COMMAND 0x00
114	#define D8390_P0_PSTART 0x01
115	#define D8390_P0_PSTOP 0x02
116	#define D8390_P0_BOUND 0x03
117	#define D8390_P0_TSR 0x04
118	#define D8390_P0_TPSR 0x04
119	#define D8390_P0_TBCR0 0x05
120	#define D8390_P0_TBCR1 0x06
121	#define D8390_P0_ISR 0x07
122	#define D8390_P0_RSAR0 0x08
123	#define D8390_P0_RSAR1 0x09
124	#define D8390_P0_RBCR0 0x0A
125	#define D8390_P0_RBCR1 0x0B
126	#define D8390_P0_RSR 0x0C
127	#define D8390_P0_RCR 0x0C
128	#define D8390_P0_TCR 0x0D
129	#define D8390_P0_DCR 0x0E
130	#define D8390_P0_IMR 0x0F
131	#define D8390_P1_COMMAND 0x00
132	#define D8390_P1_PAR0 0x01
133	#define D8390_P1_PAR1 0x02
134	#define D8390_P1_PAR2 0x03
135	#define D8390_P1_PAR3 0x04
136	#define D8390_P1_PAR4 0x05
137	#define D8390_P1_PAR5 0x06
138	#define D8390_P1_CURR 0x07
139	#define D8390_P1_MAR0 0x08
140
141	#define D8390_COMMAND_PS0 0x0 /* Page 0 select */
142	#define D8390_COMMAND_PS1 0x40 /* Page 1 select */
143	#define D8390_COMMAND_PS2 0x80 /* Page 2 select */
144	#define D8390_COMMAND_RD2 0x20 /* Remote DMA control */
145	#define D8390_COMMAND_RD1 0x10
146	#define D8390_COMMAND_RD0 0x08
147	#define D8390_COMMAND_TXP 0x04 /* transmit packet */
148	#define D8390_COMMAND_STA 0x02 /* start */
149	#define D8390_COMMAND_STP 0x01 /* stop */
150
151	#define D8390_RCR_MON 0x20 /* monitor mode */
152
153	#define D8390_DCR_FT1 0x40
154	#define D8390_DCR_LS 0x08 /* Loopback select */
155	#define D8390_DCR_WTS 0x01 /* Word transfer select */
156
157	#define D8390_ISR_PRX 0x01 /* successful recv */
158	#define D8390_ISR_PTX 0x02 /* successful xmit */
159	#define D8390_ISR_RXE 0x04 /* receive error */
160	#define D8390_ISR_TXE 0x08 /* transmit error */
161	#define D8390_ISR_OVW 0x10 /* Overflow */
162	#define D8390_ISR_CNT 0x20 /* Counter overflow */
163	#define D8390_ISR_RDC 0x40 /* Remote DMA complete */
164	#define D8390_ISR_RST 0x80 /* reset */
165
166	#define D8390_RSTAT_PRX 0x01 /* successful recv */
167	#define D8390_RSTAT_CRC 0x02 /* CRC error */
168	#define D8390_RSTAT_FAE 0x04 /* Frame alignment error */
169	#define D8390_RSTAT_OVER 0x08 /* overflow */
170
171	#define D8390_TXBUF_SIZE 6
172	#define D8390_RXBUF_END 32
173
174	struct ringbuffer {
175	unsigned char status;
176	unsigned char bound;
177	unsigned short len;
178	};