projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| 80992c50 KB |
1 | /*- |
| 2 | * Copyright (c) 1982, 1986, 1988 The Regents of the University of California. | |
| 3 | * All rights reserved. | |
| 4 | * | |
| 5 | * %sccs.include.proprietary.c% | |
| da7c5cc6 | 6 | * |
| 80992c50 | 7 | * @(#)mtpr.h 7.6 (Berkeley) %G% |
| da7c5cc6 | 8 | */ |
| 03f24a6b BJ |
9 | |
| 10 | /* | |
| 11 | * VAX processor register numbers | |
| 12 | */ | |
| 13 | ||
| bbe0bf68 BJ |
14 | #define KSP 0x0 /* kernel stack pointer */ |
| 15 | #define ESP 0x1 /* exec stack pointer */ | |
| 16 | #define SSP 0x2 /* supervisor stack pointer */ | |
| 17 | #define USP 0x3 /* user stack pointer */ | |
| 18 | #define ISP 0x4 /* interrupt stack pointer */ | |
| 19 | #define P0BR 0x8 /* p0 base register */ | |
| 20 | #define P0LR 0x9 /* p0 length register */ | |
| 21 | #define P1BR 0xa /* p1 base register */ | |
| 22 | #define P1LR 0xb /* p1 length register */ | |
| 23 | #define SBR 0xc /* system segment base register */ | |
| 24 | #define SLR 0xd /* system segment length register */ | |
| 25 | #define PCBB 0x10 /* process control block base */ | |
| 26 | #define SCBB 0x11 /* system control block base */ | |
| 27 | #define IPL 0x12 /* interrupt priority level */ | |
| 28 | #define ASTLVL 0x13 /* async. system trap level */ | |
| 29 | #define SIRR 0x14 /* software interrupt request */ | |
| 30 | #define SISR 0x15 /* software interrupt summary */ | |
| 9a0de372 MK |
31 | #if VAX8200 |
| 32 | #define IPIR 0x16 /* interprocessor interrupt register */ | |
| 33 | #endif | |
| 34 | #if VAX750 || VAX730 | |
| 35 | #define MCSR 0x17 /* machine check status register */ | |
| 36 | #endif | |
| bbe0bf68 BJ |
37 | #define ICCS 0x18 /* interval clock control */ |
| 38 | #define NICR 0x19 /* next interval count */ | |
| 39 | #define ICR 0x1a /* interval count */ | |
| 802ae52e | 40 | #if VAX8600 || VAX8200 || VAX780 || VAX750 || VAX730 || VAX650 |
| bbe0bf68 | 41 | #define TODR 0x1b /* time of year (day) */ |
| 9a0de372 MK |
42 | #endif |
| 43 | #if VAX750 || VAX730 | |
| 44 | #define CSRS 0x1c /* console storage receive status register */ | |
| 45 | #define CSRD 0x1d /* console storage receive data register */ | |
| 46 | #define CSTS 0x1e /* console storage transmit status register */ | |
| 47 | #define CSTD 0x1f /* console storage transmit data register */ | |
| 48 | #endif | |
| bbe0bf68 BJ |
49 | #define RXCS 0x20 /* console receiver control and status */ |
| 50 | #define RXDB 0x21 /* console receiver data buffer */ | |
| 51 | #define TXCS 0x22 /* console transmitter control and status */ | |
| 52 | #define TXDB 0x23 /* console transmitter data buffer */ | |
| 802ae52e | 53 | #if VAX8200 || VAX750 || VAX730 || VAX650 |
| 9a0de372 MK |
54 | #define TBDR 0x24 /* translation buffer disable register */ |
| 55 | #define CADR 0x25 /* cache disable register */ | |
| dd70a7d6 TF |
56 | #endif |
| 57 | #if VAX8200 || VAX750 || VAX730 | |
| 9a0de372 MK |
58 | #define MCESR 0x26 /* machine check error summary register */ |
| 59 | #endif | |
| 802ae52e | 60 | #if VAX750 || VAX730 || VAX650 |
| 9a0de372 MK |
61 | #define CAER 0x27 /* cache error */ |
| 62 | #endif | |
| 63 | #define ACCS 0x28 /* accelerator control and status */ | |
| 64 | #if VAX780 | |
| 65 | #define ACCR 0x29 /* accelerator maintenance */ | |
| 66 | #endif | |
| 67 | #if VAX8200 || VAX780 | |
| 68 | #define WCSA 0x2c /* WCS address */ | |
| 69 | #define WCSD 0x2d /* WCS data */ | |
| 70 | #endif | |
| 71 | #if VAX8200 | |
| 72 | #define WCSL 0x2e /* WCS load */ | |
| 73 | #endif | |
| 74 | #if VAX8600 || VAX780 | |
| 75 | #define SBIFS 0x30 /* SBI fault and status */ | |
| 76 | #define SBIS 0x31 /* SBI silo */ | |
| 77 | #define SBISC 0x32 /* SBI silo comparator */ | |
| 78 | #define SBIMT 0x33 /* SBI maintenance */ | |
| 79 | #define SBIER 0x34 /* SBI error register */ | |
| 80 | #define SBITA 0x35 /* SBI timeout address */ | |
| 81 | #define SBIQC 0x36 /* SBI quadword clear */ | |
| 82 | #endif | |
| 802ae52e TF |
83 | #if VAX750 || VAX730 || VAX630 || VAX650 |
| 84 | #define IUR 0x37 /* init unibus (Qbus on 6x0) register */ | |
| 9a0de372 | 85 | #endif |
| bbe0bf68 BJ |
86 | #define MAPEN 0x38 /* memory management enable */ |
| 87 | #define TBIA 0x39 /* translation buffer invalidate all */ | |
| 88 | #define TBIS 0x3a /* translation buffer invalidate single */ | |
| 9a0de372 MK |
89 | #if VAX750 || VAX730 |
| 90 | #define TB 0x3b /* translation buffer */ | |
| 91 | #endif | |
| 92 | #if VAX780 | |
| 93 | #define MBRK 0x3c /* micro-program breakpoint */ | |
| 94 | #endif | |
| bbe0bf68 BJ |
95 | #define PMR 0x3d /* performance monitor enable */ |
| 96 | #define SID 0x3e /* system identification */ | |
| 802ae52e | 97 | #if VAX8600 || VAX8200 || VAX650 |
| 6692a5c8 | 98 | #define TBCHK 0x3f /* Translation Buffer Check */ |
| 9a0de372 MK |
99 | #endif |
| 100 | #if VAX8600 | |
| 6692a5c8 JB |
101 | #define PAMACC 0x40 /* PAMM access */ |
| 102 | #define PAMLOC 0x41 /* PAMM location */ | |
| 103 | #define CSWP 0x42 /* Cache sweep */ | |
| 104 | #define MDECC 0x43 /* MBOX data ecc register */ | |
| 105 | #define MENA 0x44 /* MBOX error enable register */ | |
| 106 | #define MDCTL 0x45 /* MBOX data control register */ | |
| 107 | #define MCCTL 0x46 /* MBOX mcc control register */ | |
| 108 | #define MERG 0x47 /* MBOX error generator register */ | |
| 109 | #define CRBT 0x48 /* Console reboot */ | |
| 110 | #define DFI 0x49 /* Diag fault insertion register */ | |
| 111 | #define EHSR 0x4a /* Error handling status register */ | |
| 112 | #define STXCS 0x4c /* Console block storage C/S */ | |
| 113 | #define STXDB 0x4d /* Console block storage D/B */ | |
| 114 | #define ESPA 0x4e /* EBOX scratchpad address */ | |
| 115 | #define ESPD 0x4f /* EBOX sratchpad data */ | |
| 116 | #endif | |
| 9a0de372 MK |
117 | #if VAX8200 |
| 118 | #define RXCS1 0x50 /* receive csr, console line 1 */ | |
| 119 | #define RXDB1 0x51 /* receive data buffer, console line 1 */ | |
| 120 | #define TXCS1 0x52 /* transmit csr, console line 1 */ | |
| 121 | #define TXDB1 0x53 /* transmit data buffer, console line 1 */ | |
| 122 | #define RXCS2 0x54 /* etc */ | |
| 123 | #define RXDB2 0x55 | |
| 124 | #define TXCS2 0x56 | |
| 125 | #define TXDB2 0x57 | |
| 126 | #define RXCS3 0x58 | |
| 127 | #define RXDB3 0x59 | |
| 128 | #define TXCS3 0x5a | |
| 129 | #define TXDB3 0x5b | |
| 130 | #define RXCD 0x5c /* receive console data register */ | |
| 131 | #define CACHEX 0x5d /* cache invalidate register */ | |
| 132 | #define BINID 0x5e /* VAXBI node ID register */ | |
| 133 | #define BISTOP 0x5f /* VAXBI stop register */ | |
| 03d3d455 | 134 | #endif |