BSD 4_4_Lite1 release
[unix-history] / usr / src / sys / sparc / include / reg.h
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e3d866b1 1/*
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2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
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4 *
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
8 *
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9 * All advertising materials mentioning features or use of this software
10 * must display the following acknowledgement:
11 * This product includes software developed by the University of
1869bdc0 12 * California, Lawrence Berkeley Laboratory.
b480239a 13 *
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14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. All advertising materials mentioning features or use of this software
23 * must display the following acknowledgement:
24 * This product includes software developed by the University of
25 * California, Berkeley and its contributors.
26 * 4. Neither the name of the University nor the names of its contributors
27 * may be used to endorse or promote products derived from this software
28 * without specific prior written permission.
29 *
30 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
31 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
33 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
38 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
39 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
40 * SUCH DAMAGE.
e3d866b1 41 *
ad787160 42 * @(#)reg.h 8.1 (Berkeley) 6/11/93
e3d866b1 43 *
1869bdc0 44 * from: $Header: reg.h,v 1.8 92/11/26 02:04:44 torek Exp $
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45 */
46
47#ifndef _MACHINE_REG_H_
48#define _MACHINE_REG_H_
49
50/*
51 * Registers passed to trap/syscall/etc.
52 * This structure is known to occupy exactly 80 bytes (see locore.s).
53 * Note, tf_global[0] is not actually written (since g0 is always 0).
54 * (The slot tf_global[0] is used to send a copy of %wim to kernel gdb.
55 * This is known as `cheating'.)
56 */
57struct trapframe {
58 int tf_psr; /* psr */
59 int tf_pc; /* return pc */
60 int tf_npc; /* return npc */
61 int tf_y; /* %y register */
62 int tf_global[8]; /* global registers in trap's caller */
63 int tf_out[8]; /* output registers in trap's caller */
64};
65
66/*
67 * Register windows. Each stack pointer (%o6 aka %sp) in each window
68 * must ALWAYS point to some place at which it is safe to scribble on
69 * 64 bytes. (If not, your process gets mangled.) Furthermore, each
70 * stack pointer should be aligned on an 8-byte boundary (the kernel
71 * as currently coded allows arbitrary alignment, but with a hefty
72 * performance penalty).
73 */
74struct rwindow {
75 int rw_local[8]; /* %l0..%l7 */
76 int rw_in[8]; /* %i0..%i7 */
77};
78
5548a02f 79#include <machine/fsr.h>
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80
81/*
82 * FP coprocessor registers.
83 *
84 * FP_QSIZE is the maximum coprocessor instruction queue depth
85 * of any implementation on which the kernel will run. David Hough:
86 * ``I'd suggest allowing 16 ... allowing an indeterminate variable
87 * size would be even better''. Of course, we cannot do that; we
88 * need to malloc these.
89 */
90#define FP_QSIZE 16
91
92struct fp_qentry {
93 int *fq_addr; /* the instruction's address */
94 int fq_instr; /* the instruction itself */
95};
96struct fpstate {
97 u_int fs_regs[32]; /* our view is 32 32-bit registers */
98 int fs_fsr; /* %fsr */
99 int fs_qsize; /* actual queue depth */
100 struct fp_qentry fs_queue[FP_QSIZE]; /* queue contents */
101};
102
103#endif /* _MACHINE_REG_H_ */