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| Commit | Line | Data |
|---|---|---|
| 2693ab1f C |
1 | /* mem.h 4.9 81/04/03 */ |
| 2 | ||
| 3 | /* | |
| 4 | * Memory controller registers | |
| 5 | * | |
| 6 | * The way in which the data is stored in these registers varies | |
| 7 | * per cpu, so we define macros here to mask that. | |
| 8 | */ | |
| 9 | struct mcr { | |
| 10 | int mc_reg[3]; | |
| 11 | }; | |
| 12 | ||
| 13 | /* | |
| 14 | * Compute maximum possible number of memory controllers, | |
| 15 | * for sizing of the mcraddr array. | |
| 16 | */ | |
| 17 | #if VAX780 | |
| 18 | #define MAXNMCR 4 | |
| 19 | #else | |
| 20 | #define MAXNMCR 1 | |
| 21 | #endif | |
| 22 | ||
| 23 | /* | |
| 24 | * For each processor type we define 5 macros: | |
| 25 | * M???_INH(mcr) inhibits further crd interrupts from mcr | |
| 26 | * M???_ENA(mcr) enables another crd interrupt from mcr | |
| 27 | * M???_ERR(mcr) tells whether an error is waiting | |
| 28 | * M???_SYN(mcr) gives the syndrome bits of the error | |
| 29 | * M???_ADDR(mcr) gives the address of the error | |
| 30 | */ | |
| 31 | #if VAX780 | |
| 32 | #define M780_ICRD 0x40000000 /* inhibit crd interrupts, in [2] */ | |
| 33 | #define M780_HIER 0x20000000 /* high error rate, in reg[2] */ | |
| 34 | #define M780_ERLOG 0x10000000 /* error log request, in reg[2] */ | |
| 35 | /* on a 780, memory crd's occur only when bit 15 is set in the SBIER */ | |
| 36 | /* register; bit 14 there is an error bit which we also clear */ | |
| 37 | /* these bits are in the back of the ``red book'' (or in the VMS code) */ | |
| 38 | ||
| 39 | #define M780_INH(mcr) \ | |
| 40 | (((mcr)->mc_reg[2] = (M780_ICRD|M780_HIER|M780_ERLOG)), mtpr(SBIER, 0)) | |
| 41 | #define M780_ENA(mcr) \ | |
| 42 | (((mcr)->mc_reg[2] = (M780_HIER|M780_ERLOG)), mtpr(SBIER, 3<<14)) | |
| 43 | #define M780_ERR(mcr) \ | |
| 44 | ((mcr)->mc_reg[2] & (M780_ERLOG)) | |
| 45 | ||
| 46 | #define M780_SYN(mcr) ((mcr)->mc_reg[2] & 0xff) | |
| 47 | #define M780_ADDR(mcr) (((mcr)->mc_reg[2] >> 8) & 0xfffff) | |
| 48 | #endif | |
| 49 | ||
| 50 | #if VAX750 | |
| 51 | #define M750_ICRD 0x10000000 /* inhibit crd interrupts, in [1] */ | |
| 52 | #define M750_UNCORR 0xc0000000 /* uncorrectable error, in [0] */ | |
| 53 | #define M750_CORERR 0x40000000 /* correctable error, in [0] */ | |
| 54 | ||
| 55 | #define M750_INH(mcr) ((mcr)->mc_reg[1] = M750_ICRD) | |
| 56 | #define M750_ENA(mcr) ((mcr)->mc_reg[0] = (M750_UNCORR|M750_CORERR), \ | |
| 57 | (mcr)->mc_reg[1] = 0) | |
| 58 | #define M750_ERR(mcr) ((mcr)->mc_reg[0] & (M750_UNCORR|M750_CORERR)) | |
| 59 | ||
| 60 | #define M750_SYN(mcr) ((mcr)->mc_reg[0] & 0x3f) | |
| 61 | #define M750_ADDR(mcr) (((mcr)->mc_reg[0] >> 8) & 0x7fff) | |
| 62 | #endif | |
| 63 | ||
| 64 | #if VAX7ZZ | |
| 65 | #define M7ZZ_CRD 0x40000000 /* crd, in [1] */ | |
| 66 | #define M7ZZ_FTBPE 0x20000000 /* force tbuf parity error, in [1] */ | |
| 67 | #define M7ZZ_ENACRD 0x10000000 /* enable crd interrupt, in [1] */ | |
| 68 | #define M7ZZ_MME 0x08000000 /* mem-man enable (ala ipr), in [1] */ | |
| 69 | #define M7ZZ_DM 0x04000000 /* diagnostic mode, in [1] */ | |
| 70 | #define M7ZZ_DISECC 0x02000000 /* disable ecc, in [1] */ | |
| 71 | ||
| 72 | #define M7ZZ_INH(mcr) ((mcr)->mc_reg[1] = M7ZZ_MME) | |
| 73 | #define M7ZZ_ENA(mcr) ((mcr)->mc_reg[1] = (M7ZZ_MME|M7ZZ_ENACRD)) | |
| 74 | #define M7ZZ_ERR(mcr) ((mcr)->mc_reg[1] & M7ZZ_CRD) | |
| 75 | #define M7ZZ_SYN(mcr) ((mcr)->mc_reg[0] & 0x7f) | |
| 76 | #define M7ZZ_ADDR(mcr) (((mcr)->mc_reg[0] >> 8) & 0x7fff) | |
| 77 | #endif | |
| 78 | ||
| 79 | #define MEMINTVL (60*60*10) /* 10 minutes */ | |
| 80 | ||
| 81 | #ifdef KERNEL | |
| 82 | int nmcr; | |
| 83 | struct mcr *mcraddr[MAXNMCR]; | |
| 84 | #endif |