projects / unix-history / blame
| Commit | Line | Data |
|---|---|---|
| 2693ab1f C |
1 | /* ubareg.h 4.22 81/04/03 */ |
| 2 | ||
| 3 | /* | |
| 4 | * VAX UNIBUS adapter registers | |
| 5 | */ | |
| 6 | #ifndef LOCORE | |
| 7 | /* | |
| 8 | * UBA hardware registers | |
| 9 | */ | |
| 10 | struct uba_regs | |
| 11 | { | |
| 12 | int uba_cnfgr; /* configuration register */ | |
| 13 | int uba_cr; /* control register */ | |
| 14 | int uba_sr; /* status register */ | |
| 15 | int uba_dcr; /* diagnostic control register */ | |
| 16 | int uba_fmer; /* failed map entry register */ | |
| 17 | int uba_fubar; /* failed UNIBUS address register */ | |
| 18 | int pad1[2]; | |
| 19 | int uba_brsvr[4]; | |
| 20 | int uba_brrvr[4]; /* receive vector registers */ | |
| 21 | int uba_dpr[16]; /* buffered data path register */ | |
| 22 | int pad2[480]; | |
| 23 | struct pte uba_map[496]; /* unibus map register */ | |
| 24 | int pad3[16]; /* no maps for device address space */ | |
| 25 | }; | |
| 26 | #endif | |
| 27 | ||
| 28 | #if VAX780 | |
| 29 | /* uba_cnfgr */ | |
| 30 | #define UBACNFGR_UBINIT 0x00040000 /* unibus init asserted */ | |
| 31 | #define UBACNFGR_UBPDN 0x00020000 /* unibus power down */ | |
| 32 | #define UBACNFGR_UBIC 0x00010000 /* unibus init complete */ | |
| 33 | ||
| 34 | /* uba_cr */ | |
| 35 | #define UBACR_MRD16 0x40000000 /* map reg disable bit 4 */ | |
| 36 | #define UBACR_MRD8 0x20000000 /* map reg disable bit 3 */ | |
| 37 | #define UBACR_MRD4 0x10000000 /* map reg disable bit 2 */ | |
| 38 | #define UBACR_MRD2 0x08000000 /* map reg disable bit 1 */ | |
| 39 | #define UBACR_MRD1 0x04000000 /* map reg disable bit 0 */ | |
| 40 | #define UBACR_IFS 0x00000040 /* interrupt field switch */ | |
| 41 | #define UBACR_BRIE 0x00000020 /* BR interrupt enable */ | |
| 42 | #define UBACR_USEFIE 0x00000010 /* UNIBUS to SBI error field IE */ | |
| 43 | #define UBACR_SUEFIE 0x00000008 /* SBI to UNIBUS error field IE */ | |
| 44 | #define UBACR_CNFIE 0x00000004 /* configuration IE */ | |
| 45 | #define UBACR_UPF 0x00000002 /* UNIBUS power fail */ | |
| 46 | #define UBACR_ADINIT 0x00000001 /* adapter init */ | |
| 47 | ||
| 48 | /* uba_sr */ | |
| 49 | #define UBASR_BR7FULL 0x08000000 /* BR7 receive vector reg full */ | |
| 50 | #define UBASR_BR6FULL 0x04000000 /* BR6 receive vector reg full */ | |
| 51 | #define UBASR_BR5FULL 0x02000000 /* BR5 receive vector reg full */ | |
| 52 | #define UBASR_BR4FULL 0x01000000 /* BR4 receive vector reg full */ | |
| 53 | #define UBASR_RDTO 0x00000400 /* UNIBUS to SBI read data timeout */ | |
| 54 | #define UBASR_RDS 0x00000200 /* read data substitute */ | |
| 55 | #define UBASR_CRD 0x00000100 /* corrected read data */ | |
| 56 | #define UBASR_CXTER 0x00000080 /* command transmit error */ | |
| 57 | #define UBASR_CXTMO 0x00000040 /* command transmit timeout */ | |
| 58 | #define UBASR_DPPE 0x00000020 /* data path parity error */ | |
| 59 | #define UBASR_IVMR 0x00000010 /* invalid map register */ | |
| 60 | #define UBASR_MRPF 0x00000008 /* map register parity failure */ | |
| 61 | #define UBASR_LEB 0x00000004 /* lost error */ | |
| 62 | #define UBASR_UBSTO 0x00000002 /* UNIBUS select timeout */ | |
| 63 | #define UBASR_UBSSYNTO 0x00000001 /* UNIBUS slave sync timeout */ | |
| 64 | ||
| 65 | #define UBASR_BITS \ | |
| 66 | "\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO" | |
| 67 | ||
| 68 | /* uba_brrvr[] */ | |
| 69 | #define UBABRRVR_AIRI 0x80000000 /* adapter interrupt request */ | |
| 70 | #define UBABRRVR_DIV 0x0000ffff /* device interrupt vector field */ | |
| 71 | #endif VAX780 | |
| 72 | ||
| 73 | /* uba_dpr */ | |
| 74 | #if VAX780 | |
| 75 | #define UBADPR_BNE 0x80000000 /* buffer not empty - purge */ | |
| 76 | #define UBADPR_BTE 0x40000000 /* buffer transfer error */ | |
| 77 | #define UBADPR_DPF 0x20000000 /* DP function (RO) */ | |
| 78 | #define UBADPR_BS 0x007f0000 /* buffer state field */ | |
| 79 | #define UBADPR_BUBA 0x0000ffff /* buffered UNIBUS address */ | |
| 80 | #endif VAX780 | |
| 81 | #if VAX750 | |
| 82 | #define UBADPR_ERROR 0x80000000 /* error occurred */ | |
| 83 | #define UBADPR_NXM 0x40000000 /* nxm from memory */ | |
| 84 | #define UBADPR_UCE 0x20000000 /* uncorrectable error */ | |
| 85 | #define UBADPR_PURGE 0x00000001 /* purge bdp */ | |
| 86 | #endif VAX750 | |
| 87 | ||
| 88 | /* uba_mr[] */ | |
| 89 | #define UBAMR_MRV 0x80000000 /* map register valid */ | |
| 90 | #define UBAMR_BO 0x02000000 /* byte offset bit */ | |
| 91 | #define UBAMR_DPDB 0x01e00000 /* data path designator field */ | |
| 92 | #define UBAMR_SBIPFN 0x000fffff /* SBI page address field */ | |
| 93 | ||
| 94 | #define UBAMR_DPSHIFT 21 /* shift to data path designator */ | |
| 95 | ||
| 96 | /* | |
| 97 | * Number of UNIBUS map registers. We can't use the last 8k of UNIBUS | |
| 98 | * address space for i/o transfers since it is used by the devices, | |
| 99 | * hence have slightly less than 256K of UNIBUS address space. | |
| 100 | */ | |
| 101 | #define NUBMREG 496 | |
| 102 | ||
| 103 | /* | |
| 104 | * Number of unibus buffered data paths and possible uba's per cpu type. | |
| 105 | */ | |
| 106 | #define NBDP780 15 | |
| 107 | #define NBDP750 3 | |
| 108 | #define NBDP7ZZ 0 | |
| 109 | #define MAXNBDP 15 | |
| 110 | ||
| 111 | #define NUBA780 4 | |
| 112 | #define NUBA750 1 | |
| 113 | #define NUBA7ZZ 1 | |
| 114 | #if VAX780 | |
| 115 | #define MAXNUBA 4 | |
| 116 | #else | |
| 117 | #define MAXNUBA 1 | |
| 118 | #endif | |
| 119 | ||
| 120 | /* | |
| 121 | * Formulas for locations of the last 8k of UNIBUS memory | |
| 122 | * for each possible uba. | |
| 123 | */ | |
| 124 | #if VAX7ZZ | |
| 125 | #define UMEM7ZZ ((u_short *)(0xffe000)) | |
| 126 | #endif | |
| 127 | #if VAX750 | |
| 128 | #define UMEM750(i) ((u_short *)(0xffe000-(i)*0x40000)) | |
| 129 | #endif | |
| 130 | #if VAX780 | |
| 131 | #define UMEM780(i) ((u_short *)(0x2013e000+(i)*0x40000)) | |
| 132 | #endif |