| 1 | /* |
| 2 | * Copyright (c) 1988 University of Utah. |
| 3 | * Copyright (c) 1982, 1990, 1993 |
| 4 | * The Regents of the University of California. All rights reserved. |
| 5 | * |
| 6 | * This code is derived from software contributed to Berkeley by |
| 7 | * the Systems Programming Group of the University of Utah Computer |
| 8 | * Science Department. |
| 9 | * |
| 10 | * %sccs.include.redist.c% |
| 11 | * |
| 12 | * from: Utah $Hdr: cpu.h 1.16 91/03/25$ |
| 13 | * |
| 14 | * @(#)cpu.h 8.3 (Berkeley) %G% |
| 15 | */ |
| 16 | |
| 17 | /* |
| 18 | * Exported definitions unique to hp300/68k cpu support. |
| 19 | */ |
| 20 | |
| 21 | /* |
| 22 | * definitions of cpu-dependent requirements |
| 23 | * referenced in generic code |
| 24 | */ |
| 25 | #define COPY_SIGCODE /* copy sigcode above user stack in exec */ |
| 26 | |
| 27 | #define cpu_exec(p) /* nothing */ |
| 28 | #define cpu_wait(p) /* nothing */ |
| 29 | #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap |
| 30 | #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp |
| 31 | |
| 32 | /* |
| 33 | * Arguments to hardclock and gatherstats encapsulate the previous |
| 34 | * machine state in an opaque clockframe. One the hp300, we use |
| 35 | * what the hardware pushes on an interrupt (frame format 0). |
| 36 | */ |
| 37 | struct clockframe { |
| 38 | u_short sr; /* sr at time of interrupt */ |
| 39 | u_long pc; /* pc at time of interrupt */ |
| 40 | u_short vo; /* vector offset (4-word frame) */ |
| 41 | }; |
| 42 | |
| 43 | #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) |
| 44 | #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) |
| 45 | #define CLKF_PC(framep) ((framep)->pc) |
| 46 | #if 0 |
| 47 | /* We would like to do it this way... */ |
| 48 | #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) |
| 49 | #else |
| 50 | /* but until we start using PSL_M, we have to do this instead */ |
| 51 | #define CLKF_INTR(framep) (0) /* XXX */ |
| 52 | #endif |
| 53 | |
| 54 | |
| 55 | /* |
| 56 | * Preempt the current process if in interrupt from user mode, |
| 57 | * or after the current trap/syscall if in system mode. |
| 58 | */ |
| 59 | #define need_resched() { want_resched++; aston(); } |
| 60 | |
| 61 | /* |
| 62 | * Give a profiling tick to the current process when the user profiling |
| 63 | * buffer pages are invalid. On the hp300, request an ast to send us |
| 64 | * through trap, marking the proc as needing a profiling tick. |
| 65 | */ |
| 66 | #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } |
| 67 | |
| 68 | /* |
| 69 | * Notify the current process (p) that it has a signal pending, |
| 70 | * process as soon as possible. |
| 71 | */ |
| 72 | #define signotify(p) aston() |
| 73 | |
| 74 | #define aston() (astpending++) |
| 75 | |
| 76 | int astpending; /* need to trap before returning to user mode */ |
| 77 | int want_resched; /* resched() was called */ |
| 78 | |
| 79 | |
| 80 | /* |
| 81 | * simulated software interrupt register |
| 82 | */ |
| 83 | extern unsigned char ssir; |
| 84 | |
| 85 | #define SIR_NET 0x1 |
| 86 | #define SIR_CLOCK 0x2 |
| 87 | |
| 88 | #define siroff(x) ssir &= ~(x) |
| 89 | #define setsoftnet() ssir |= SIR_NET |
| 90 | #define setsoftclock() ssir |= SIR_CLOCK |
| 91 | |
| 92 | /* |
| 93 | * CTL_MACHDEP definitions. |
| 94 | */ |
| 95 | #define CPU_CONSDEV 1 /* dev_t: console terminal device */ |
| 96 | #define CPU_MAXID 2 /* number of valid machdep ids */ |
| 97 | |
| 98 | #define CTL_MACHDEP_NAMES { \ |
| 99 | { 0, 0 }, \ |
| 100 | { "console_device", CTLTYPE_STRUCT }, \ |
| 101 | } |
| 102 | |
| 103 | /* |
| 104 | * The rest of this should probably be moved to ../hp300/hp300cpu.h, |
| 105 | * although some of it could probably be put into generic 68k headers. |
| 106 | */ |
| 107 | |
| 108 | /* values for machineid */ |
| 109 | #define HP_320 0 /* 16Mhz 68020+HP MMU+16K external cache */ |
| 110 | #define HP_330 1 /* 16Mhz 68020+68851 MMU */ |
| 111 | #define HP_350 2 /* 25Mhz 68020+HP MMU+32K external cache */ |
| 112 | #define HP_360 3 /* 25Mhz 68030 */ |
| 113 | #define HP_370 4 /* 33Mhz 68030+64K external cache */ |
| 114 | #define HP_340 5 /* 16Mhz 68030 */ |
| 115 | #define HP_375 6 /* 50Mhz 68030+32K external cache */ |
| 116 | #define HP_380 7 /* 25Mhz 68040 */ |
| 117 | #define HP_433 8 /* 33Mhz 68040 */ |
| 118 | |
| 119 | /* values for mmutype (assigned for quick testing) */ |
| 120 | #define MMU_68040 -2 /* 68040 on-chip MMU */ |
| 121 | #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ |
| 122 | #define MMU_HP 0 /* HP proprietary */ |
| 123 | #define MMU_68851 1 /* Motorola 68851 */ |
| 124 | |
| 125 | /* values for ectype */ |
| 126 | #define EC_PHYS -1 /* external physical address cache */ |
| 127 | #define EC_NONE 0 /* no external cache */ |
| 128 | #define EC_VIRT 1 /* external virtual address cache */ |
| 129 | |
| 130 | /* values for cpuspeed (not really related to clock speed due to caches) */ |
| 131 | #define MHZ_8 1 |
| 132 | #define MHZ_16 2 |
| 133 | #define MHZ_25 3 |
| 134 | #define MHZ_33 4 |
| 135 | #define MHZ_50 6 |
| 136 | |
| 137 | #ifdef KERNEL |
| 138 | extern int machineid, mmutype, ectype; |
| 139 | extern char *intiobase, *intiolimit; |
| 140 | |
| 141 | /* what is this supposed to do? i.e. how is it different than startrtclock? */ |
| 142 | #define enablertclock() |
| 143 | |
| 144 | #endif |
| 145 | |
| 146 | /* physical memory sections */ |
| 147 | #define ROMBASE (0x00000000) |
| 148 | #define INTIOBASE (0x00400000) |
| 149 | #define INTIOTOP (0x00600000) |
| 150 | #define EXTIOBASE (0x00600000) |
| 151 | #define EXTIOTOP (0x20000000) |
| 152 | #define MAXADDR (0xFFFFF000) |
| 153 | |
| 154 | /* |
| 155 | * Internal IO space: |
| 156 | * |
| 157 | * Ranges from 0x400000 to 0x600000 (IIOMAPSIZE). |
| 158 | * |
| 159 | * Internal IO space is mapped in the kernel from ``intiobase'' to |
| 160 | * ``intiolimit'' (defined in locore.s). Since it is always mapped, |
| 161 | * conversion between physical and kernel virtual addresses is easy. |
| 162 | */ |
| 163 | #define ISIIOVA(va) \ |
| 164 | ((char *)(va) >= intiobase && (char *)(va) < intiolimit) |
| 165 | #define IIOV(pa) ((int)(pa)-INTIOBASE+(int)intiobase) |
| 166 | #define IIOP(va) ((int)(va)-(int)intiobase+INTIOBASE) |
| 167 | #define IIOPOFF(pa) ((int)(pa)-INTIOBASE) |
| 168 | #define IIOMAPSIZE btoc(INTIOTOP-INTIOBASE) /* 2mb */ |
| 169 | |
| 170 | /* |
| 171 | * External IO space: |
| 172 | * |
| 173 | * DIO ranges from select codes 0-63 at physical addresses given by: |
| 174 | * 0x600000 + (sc - 32) * 0x10000 |
| 175 | * DIO cards are addressed in the range 0-31 [0x600000-0x800000) for |
| 176 | * their control space and the remaining areas, [0x200000-0x400000) and |
| 177 | * [0x800000-0x1000000), are for additional space required by a card; |
| 178 | * e.g. a display framebuffer. |
| 179 | * |
| 180 | * DIO-II ranges from select codes 132-255 at physical addresses given by: |
| 181 | * 0x1000000 + (sc - 132) * 0x400000 |
| 182 | * The address range of DIO-II space is thus [0x1000000-0x20000000). |
| 183 | * |
| 184 | * DIO/DIO-II space is too large to map in its entirety, instead devices |
| 185 | * are mapped into kernel virtual address space allocated from a range |
| 186 | * of EIOMAPSIZE pages (vmparam.h) starting at ``extiobase''. |
| 187 | */ |
| 188 | #define DIOBASE (0x600000) |
| 189 | #define DIOTOP (0x1000000) |
| 190 | #define DIOCSIZE (0x10000) |
| 191 | #define DIOIIBASE (0x01000000) |
| 192 | #define DIOIITOP (0x20000000) |
| 193 | #define DIOIICSIZE (0x00400000) |
| 194 | |
| 195 | /* |
| 196 | * HP MMU |
| 197 | */ |
| 198 | #define MMUBASE IIOPOFF(0x5F4000) |
| 199 | #define MMUSSTP 0x0 |
| 200 | #define MMUUSTP 0x4 |
| 201 | #define MMUTBINVAL 0x8 |
| 202 | #define MMUSTAT 0xC |
| 203 | #define MMUCMD MMUSTAT |
| 204 | |
| 205 | #define MMU_UMEN 0x0001 /* enable user mapping */ |
| 206 | #define MMU_SMEN 0x0002 /* enable supervisor mapping */ |
| 207 | #define MMU_CEN 0x0004 /* enable data cache */ |
| 208 | #define MMU_BERR 0x0008 /* bus error */ |
| 209 | #define MMU_IEN 0x0020 /* enable instruction cache */ |
| 210 | #define MMU_FPE 0x0040 /* enable 68881 FP coprocessor */ |
| 211 | #define MMU_WPF 0x2000 /* write protect fault */ |
| 212 | #define MMU_PF 0x4000 /* page fault */ |
| 213 | #define MMU_PTF 0x8000 /* page table fault */ |
| 214 | |
| 215 | #define MMU_FAULT (MMU_PTF|MMU_PF|MMU_WPF|MMU_BERR) |
| 216 | #define MMU_ENAB (MMU_UMEN|MMU_SMEN|MMU_IEN|MMU_FPE) |
| 217 | |
| 218 | /* |
| 219 | * 68851 and 68030 MMU |
| 220 | */ |
| 221 | #define PMMU_LVLMASK 0x0007 |
| 222 | #define PMMU_INV 0x0400 |
| 223 | #define PMMU_WP 0x0800 |
| 224 | #define PMMU_ALV 0x1000 |
| 225 | #define PMMU_SO 0x2000 |
| 226 | #define PMMU_LV 0x4000 |
| 227 | #define PMMU_BE 0x8000 |
| 228 | #define PMMU_FAULT (PMMU_WP|PMMU_INV) |
| 229 | |
| 230 | /* |
| 231 | * 68040 MMU |
| 232 | */ |
| 233 | #define MMU4_RES 0x001 |
| 234 | #define MMU4_TTR 0x002 |
| 235 | #define MMU4_WP 0x004 |
| 236 | #define MMU4_MOD 0x010 |
| 237 | #define MMU4_CMMASK 0x060 |
| 238 | #define MMU4_SUP 0x080 |
| 239 | #define MMU4_U0 0x100 |
| 240 | #define MMU4_U1 0x200 |
| 241 | #define MMU4_GLB 0x400 |
| 242 | #define MMU4_BE 0x800 |
| 243 | |
| 244 | /* 680X0 function codes */ |
| 245 | #define FC_USERD 1 /* user data space */ |
| 246 | #define FC_USERP 2 /* user program space */ |
| 247 | #define FC_PURGE 3 /* HPMMU: clear TLB entries */ |
| 248 | #define FC_SUPERD 5 /* supervisor data space */ |
| 249 | #define FC_SUPERP 6 /* supervisor program space */ |
| 250 | #define FC_CPU 7 /* CPU space */ |
| 251 | |
| 252 | /* fields in the 68020 cache control register */ |
| 253 | #define IC_ENABLE 0x0001 /* enable instruction cache */ |
| 254 | #define IC_FREEZE 0x0002 /* freeze instruction cache */ |
| 255 | #define IC_CE 0x0004 /* clear instruction cache entry */ |
| 256 | #define IC_CLR 0x0008 /* clear entire instruction cache */ |
| 257 | |
| 258 | /* additional fields in the 68030 cache control register */ |
| 259 | #define IC_BE 0x0010 /* instruction burst enable */ |
| 260 | #define DC_ENABLE 0x0100 /* data cache enable */ |
| 261 | #define DC_FREEZE 0x0200 /* data cache freeze */ |
| 262 | #define DC_CE 0x0400 /* clear data cache entry */ |
| 263 | #define DC_CLR 0x0800 /* clear entire data cache */ |
| 264 | #define DC_BE 0x1000 /* data burst enable */ |
| 265 | #define DC_WA 0x2000 /* write allocate */ |
| 266 | |
| 267 | #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) |
| 268 | #define CACHE_OFF (DC_CLR|IC_CLR) |
| 269 | #define CACHE_CLR (CACHE_ON) |
| 270 | #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) |
| 271 | #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) |
| 272 | |
| 273 | /* 68040 cache control register */ |
| 274 | #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ |
| 275 | #define DC4_ENABLE 0x80000000 /* data cache enable bit */ |
| 276 | |
| 277 | #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) |
| 278 | #define CACHE4_OFF (0) |