| 1 | /* |
| 2 | * Copyright (c) 1988 University of Utah. |
| 3 | * Copyright (c) 1992 OMRON Corporation. |
| 4 | * Copyright (c) 1982, 1990, 1992 The Regents of the University of California. |
| 5 | * All rights reserved. |
| 6 | * |
| 7 | * This code is derived from software contributed to Berkeley by |
| 8 | * the Systems Programming Group of the University of Utah Computer |
| 9 | * Science Department. |
| 10 | * |
| 11 | * %sccs.include.redist.c% |
| 12 | * |
| 13 | * from: Utah $Hdr: cpu.h 1.16 91/03/25$ |
| 14 | * from: hp300/include/cpu.h 7.13 (Berkeley) 12/27/92 |
| 15 | * |
| 16 | * @(#)cpu.h 7.3 (Berkeley) %G% |
| 17 | */ |
| 18 | |
| 19 | /* |
| 20 | * Exported definitions unique to luna/68k cpu support, |
| 21 | * taken from hp300/68k. |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * definitions of cpu-dependent requirements |
| 26 | * referenced in generic code |
| 27 | */ |
| 28 | #define COPY_SIGCODE /* copy sigcode above user stack in exec */ |
| 29 | |
| 30 | #define cpu_exec(p) /* nothing */ |
| 31 | #define cpu_wait(p) /* nothing */ |
| 32 | #define cpu_setstack(p, ap) \ |
| 33 | (p)->p_md.md_regs[SP] = ap |
| 34 | |
| 35 | /* |
| 36 | * Arguments to hardclock and gatherstats encapsulate the previous |
| 37 | * machine state in an opaque clockframe. One the 68k, we use |
| 38 | * what the hardware pushes on an interrupt (but we pad the sr to a |
| 39 | * longword boundary). |
| 40 | */ |
| 41 | struct clockframe { |
| 42 | u_short sr; /* sr at time of interrupt */ |
| 43 | u_long pc; /* pc at time of interrupt */ |
| 44 | u_short vo; /* vector offset (4-word frame) */ |
| 45 | }; |
| 46 | |
| 47 | #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) |
| 48 | #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) |
| 49 | #define CLKF_PC(framep) ((framep)->pc) |
| 50 | #if 0 |
| 51 | /* We would like to do it this way... */ |
| 52 | #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) |
| 53 | #else |
| 54 | /* but until we start using PSL_M, we have to do this instead */ |
| 55 | #define CLKF_INTR(framep) (0) /* XXX */ |
| 56 | #endif |
| 57 | |
| 58 | |
| 59 | /* |
| 60 | * Preempt the current process if in interrupt from user mode, |
| 61 | * or after the current trap/syscall if in system mode. |
| 62 | */ |
| 63 | #define need_resched() { want_resched++; aston(); } |
| 64 | |
| 65 | /* |
| 66 | * Give a profiling tick to the current process when the user profiling |
| 67 | * buffer pages are invalid. On the 68k, request an ast to send us |
| 68 | * through trap, marking the proc as needing a profiling tick. |
| 69 | */ |
| 70 | #define need_proftick(p) { (p)->p_flag |= SOWEUPC; aston(); } |
| 71 | |
| 72 | /* |
| 73 | * Notify the current process (p) that it has a signal pending, |
| 74 | * process as soon as possible. |
| 75 | */ |
| 76 | #define signotify(p) aston() |
| 77 | |
| 78 | #define aston() (astpending++) |
| 79 | |
| 80 | int astpending; /* need to trap before returning to user mode */ |
| 81 | int want_resched; /* resched() was called */ |
| 82 | |
| 83 | |
| 84 | /* |
| 85 | * simulated software interrupt register |
| 86 | */ |
| 87 | extern unsigned char ssir; |
| 88 | |
| 89 | #define SIR_NET 0x1 |
| 90 | #define SIR_CLOCK 0x2 |
| 91 | |
| 92 | #define siroff(x) ssir &= ~(x) |
| 93 | #define setsoftnet() ssir |= SIR_NET |
| 94 | #define setsoftclock() ssir |= SIR_CLOCK |
| 95 | |
| 96 | /* values for mmutype (assigned for quick testing) */ |
| 97 | #define MMU_68040 -2 /* 68040 on-chip MMU */ |
| 98 | #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ |
| 99 | |
| 100 | /* values for cpuspeed (not really related to clock speed due to caches) */ |
| 101 | #define MHZ_8 1 |
| 102 | #define MHZ_16 2 |
| 103 | #define MHZ_25 3 |
| 104 | #define MHZ_33 4 |
| 105 | #define MHZ_50 6 |
| 106 | |
| 107 | /* |
| 108 | * 68851 and 68030 MMU |
| 109 | */ |
| 110 | #define PMMU_LVLMASK 0x0007 |
| 111 | #define PMMU_INV 0x0400 |
| 112 | #define PMMU_WP 0x0800 |
| 113 | #define PMMU_ALV 0x1000 |
| 114 | #define PMMU_SO 0x2000 |
| 115 | #define PMMU_LV 0x4000 |
| 116 | #define PMMU_BE 0x8000 |
| 117 | #define PMMU_FAULT (PMMU_WP|PMMU_INV) |
| 118 | |
| 119 | /* |
| 120 | * 68040 MMU |
| 121 | */ |
| 122 | #define MMU4_RES 0x001 |
| 123 | #define MMU4_TTR 0x002 |
| 124 | #define MMU4_WP 0x004 |
| 125 | #define MMU4_MOD 0x010 |
| 126 | #define MMU4_CMMASK 0x060 |
| 127 | #define MMU4_SUP 0x080 |
| 128 | #define MMU4_U0 0x100 |
| 129 | #define MMU4_U1 0x200 |
| 130 | #define MMU4_GLB 0x400 |
| 131 | #define MMU4_BE 0x800 |
| 132 | |
| 133 | /* 680X0 function codes */ |
| 134 | #define FC_USERD 1 /* user data space */ |
| 135 | #define FC_USERP 2 /* user program space */ |
| 136 | #define FC_PURGE 3 /* HPMMU: clear TLB entries */ |
| 137 | #define FC_SUPERD 5 /* supervisor data space */ |
| 138 | #define FC_SUPERP 6 /* supervisor program space */ |
| 139 | #define FC_CPU 7 /* CPU space */ |
| 140 | |
| 141 | /* fields in the 68020 cache control register */ |
| 142 | #define IC_ENABLE 0x0001 /* enable instruction cache */ |
| 143 | #define IC_FREEZE 0x0002 /* freeze instruction cache */ |
| 144 | #define IC_CE 0x0004 /* clear instruction cache entry */ |
| 145 | #define IC_CLR 0x0008 /* clear entire instruction cache */ |
| 146 | |
| 147 | /* additional fields in the 68030 cache control register */ |
| 148 | #define IC_BE 0x0010 /* instruction burst enable */ |
| 149 | #define DC_ENABLE 0x0100 /* data cache enable */ |
| 150 | #define DC_FREEZE 0x0200 /* data cache freeze */ |
| 151 | #define DC_CE 0x0400 /* clear data cache entry */ |
| 152 | #define DC_CLR 0x0800 /* clear entire data cache */ |
| 153 | #define DC_BE 0x1000 /* data burst enable */ |
| 154 | #define DC_WA 0x2000 /* write allocate */ |
| 155 | |
| 156 | #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) |
| 157 | #define CACHE_OFF (DC_CLR|IC_CLR) |
| 158 | #define CACHE_CLR (CACHE_ON) |
| 159 | #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) |
| 160 | #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) |
| 161 | |
| 162 | /* 68040 cache control register */ |
| 163 | #define IC4_ENABLE 0x8000 /* instruction cache enable bit */ |
| 164 | #define DC4_ENABLE 0x80000000 /* data cache enable bit */ |
| 165 | |
| 166 | #define CACHE4_ON (IC4_ENABLE|DC4_ENABLE) |
| 167 | #define CACHE4_OFF (0) |