| 1 | /* |
| 2 | * National Semiconductor DS8390 NIC register definitions |
| 3 | * |
| 4 | * $Log: if_edreg.h,v $ |
| 5 | * Revision 1.2 93/06/23 03:03:05 davidg |
| 6 | * added some additional definitions for the 83C584 bus interface |
| 7 | * chip (SMC/WD boards) |
| 8 | * |
| 9 | * Revision 1.1 93/06/23 03:01:07 davidg |
| 10 | * Initial revision |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | /* |
| 15 | * Page 0 register offsets |
| 16 | */ |
| 17 | #define ED_P0_CR 0x00 /* Command Register */ |
| 18 | |
| 19 | #define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */ |
| 20 | #define ED_P0_PSTART 0x01 /* Page Start register (write) */ |
| 21 | |
| 22 | #define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */ |
| 23 | #define ED_P0_PSTOP 0x02 /* Page Stop register (write) */ |
| 24 | |
| 25 | #define ED_P0_BNRY 0x03 /* Boundary Pointer */ |
| 26 | |
| 27 | #define ED_P0_TSR 0x04 /* Transmit Status Register (read) */ |
| 28 | #define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */ |
| 29 | |
| 30 | #define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */ |
| 31 | #define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */ |
| 32 | |
| 33 | #define ED_P0_FIFO 0x06 /* FIFO register (read) */ |
| 34 | #define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */ |
| 35 | |
| 36 | #define ED_P0_ISR 0x07 /* Interrupt Status Register */ |
| 37 | |
| 38 | #define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */ |
| 39 | #define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */ |
| 40 | |
| 41 | #define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */ |
| 42 | #define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */ |
| 43 | |
| 44 | #define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */ |
| 45 | |
| 46 | #define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */ |
| 47 | |
| 48 | #define ED_P0_RSR 0x0c /* Receive Status (read) */ |
| 49 | #define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */ |
| 50 | |
| 51 | #define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */ |
| 52 | #define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */ |
| 53 | |
| 54 | #define ED_P0_CNTR1 0x0e /* CRC error counter (read) */ |
| 55 | #define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */ |
| 56 | |
| 57 | #define ED_P0_CNTR2 0x0f /* missed packet counter (read) */ |
| 58 | #define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */ |
| 59 | |
| 60 | /* |
| 61 | * Page 1 register offsets |
| 62 | */ |
| 63 | #define ED_P1_CR 0x00 /* Command Register */ |
| 64 | #define ED_P1_PAR0 0x01 /* Physical Address Register 0 */ |
| 65 | #define ED_P1_PAR1 0x02 /* Physical Address Register 1 */ |
| 66 | #define ED_P1_PAR2 0x03 /* Physical Address Register 2 */ |
| 67 | #define ED_P1_PAR3 0x04 /* Physical Address Register 3 */ |
| 68 | #define ED_P1_PAR4 0x05 /* Physical Address Register 4 */ |
| 69 | #define ED_P1_PAR5 0x06 /* Physical Address Register 5 */ |
| 70 | #define ED_P1_CURR 0x07 /* Current RX ring-buffer page */ |
| 71 | #define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */ |
| 72 | #define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */ |
| 73 | #define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */ |
| 74 | #define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */ |
| 75 | #define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */ |
| 76 | #define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */ |
| 77 | #define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */ |
| 78 | #define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */ |
| 79 | |
| 80 | /* |
| 81 | * Page 2 register offsets |
| 82 | */ |
| 83 | #define ED_P2_CR 0x00 /* Command Register */ |
| 84 | #define ED_P2_PSTART 0x01 /* Page Start (read) */ |
| 85 | #define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */ |
| 86 | #define ED_P2_PSTOP 0x02 /* Page Stop (read) */ |
| 87 | #define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */ |
| 88 | #define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */ |
| 89 | #define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */ |
| 90 | #define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */ |
| 91 | #define ED_P2_ACU 0x06 /* Address Counter Upper */ |
| 92 | #define ED_P2_ACL 0x07 /* Address Counter Lower */ |
| 93 | #define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */ |
| 94 | #define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */ |
| 95 | #define ED_P2_DCR 0x0e /* Data Configuration Register (read) */ |
| 96 | #define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */ |
| 97 | |
| 98 | /* |
| 99 | * Command Register (CR) definitions |
| 100 | */ |
| 101 | |
| 102 | /* |
| 103 | * STP: SToP. Software reset command. Takes the controller offline. No |
| 104 | * packets will be received or transmitted. Any reception or |
| 105 | * transmission in progress will continue to completion before |
| 106 | * entering reset state. To exit this state, the STP bit must |
| 107 | * reset and the STA bit must be set. The software reset has |
| 108 | * executed only when indicated by the RST bit in the ISR being |
| 109 | * set. |
| 110 | */ |
| 111 | #define ED_CR_STP 0x01 |
| 112 | |
| 113 | /* |
| 114 | * STA: STArt. This bit is used to activate the NIC after either power-up, |
| 115 | * or when the NIC has been put in reset mode by software command |
| 116 | * or error. |
| 117 | */ |
| 118 | #define ED_CR_STA 0x02 |
| 119 | |
| 120 | /* |
| 121 | * TXP: Transmit Packet. This bit must be set to indicate transmission of |
| 122 | * a packet. TXP is internally reset either after the transmission is |
| 123 | * completed or aborted. This bit should be set only after the Transmit |
| 124 | * Byte Count and Transmit Page Start register have been programmed. |
| 125 | */ |
| 126 | #define ED_CR_TXP 0x04 |
| 127 | |
| 128 | /* |
| 129 | * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation |
| 130 | * of the remote DMA channel. RD2 can be set to abort any remote DMA |
| 131 | * command in progress. The Remote Byte Count registers should be cleared |
| 132 | * when a remote DMA has been aborted. The Remote Start Addresses are not |
| 133 | * restored to the starting address if the remote DMA is aborted. |
| 134 | * |
| 135 | * RD2 RD1 RD0 function |
| 136 | * 0 0 0 not allowed |
| 137 | * 0 0 1 remote read |
| 138 | * 0 1 0 remote write |
| 139 | * 0 1 1 send packet |
| 140 | * 1 X X abort |
| 141 | */ |
| 142 | #define ED_CR_RD0 0x08 |
| 143 | #define ED_CR_RD1 0x10 |
| 144 | #define ED_CR_RD2 0x20 |
| 145 | |
| 146 | /* |
| 147 | * PS0, PS1: Page Select. The two bits select which register set or 'page' to |
| 148 | * access. |
| 149 | * |
| 150 | * PS1 PS0 page |
| 151 | * 0 0 0 |
| 152 | * 0 1 1 |
| 153 | * 1 0 2 |
| 154 | * 1 1 reserved |
| 155 | */ |
| 156 | #define ED_CR_PS0 0x40 |
| 157 | #define ED_CR_PS1 0x80 |
| 158 | /* bit encoded aliases */ |
| 159 | #define ED_CR_PAGE_0 0x00 /* (for consistency) */ |
| 160 | #define ED_CR_PAGE_1 0x40 |
| 161 | #define ED_CR_PAGE_2 0x80 |
| 162 | |
| 163 | /* |
| 164 | * Interrupt Status Register (ISR) definitions |
| 165 | */ |
| 166 | |
| 167 | /* |
| 168 | * PRX: Packet Received. Indicates packet received with no errors. |
| 169 | */ |
| 170 | #define ED_ISR_PRX 0x01 |
| 171 | |
| 172 | /* |
| 173 | * PTX: Packet Transmitted. Indicates packet transmitted with no errors. |
| 174 | */ |
| 175 | #define ED_ISR_PTX 0x02 |
| 176 | |
| 177 | /* |
| 178 | * RXE: Receive Error. Indicates that a packet was received with one or more |
| 179 | * the following errors: CRC error, frame alignment error, FIFO overrun, |
| 180 | * missed packet. |
| 181 | */ |
| 182 | #define ED_ISR_RXE 0x04 |
| 183 | |
| 184 | /* |
| 185 | * TXE: Transmission Error. Indicates that an attempt to transmit a packet |
| 186 | * resulted in one or more of the following errors: excessive |
| 187 | * collisions, FIFO underrun. |
| 188 | */ |
| 189 | #define ED_ISR_TXE 0x08 |
| 190 | |
| 191 | /* |
| 192 | * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network |
| 193 | * would exceed (has exceeded?) the boundry pointer, resulting in data |
| 194 | * that was previously received and not yet read from the buffer to be |
| 195 | * overwritten. |
| 196 | */ |
| 197 | #define ED_ISR_OVW 0x10 |
| 198 | |
| 199 | /* |
| 200 | * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley |
| 201 | * Counters has been set. |
| 202 | */ |
| 203 | #define ED_ISR_CNT 0x20 |
| 204 | |
| 205 | /* |
| 206 | * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed. |
| 207 | */ |
| 208 | #define ED_ISR_RDC 0x40 |
| 209 | |
| 210 | /* |
| 211 | * RST: Reset status. Set when the NIC enters the reset state and cleared when a |
| 212 | * Start Command is issued to the CR. This bit is also set when a receive |
| 213 | * ring-buffer overrun (OverWrite) occurs and is cleared when one or more |
| 214 | * packets have been removed from the ring. This is a read-only bit. |
| 215 | */ |
| 216 | #define ED_ISR_RST 0x80 |
| 217 | |
| 218 | /* |
| 219 | * Interrupt Mask Register (IMR) definitions |
| 220 | */ |
| 221 | |
| 222 | /* |
| 223 | * PRXE: Packet Received interrupt Enable. If set, a received packet will cause |
| 224 | * an interrupt. |
| 225 | */ |
| 226 | #define ED_IMR_PRXE 0x01 |
| 227 | |
| 228 | /* |
| 229 | * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when |
| 230 | * a packet transmission completes. |
| 231 | */ |
| 232 | #define ED_IMR_PTXE 0x02 |
| 233 | |
| 234 | /* |
| 235 | * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a |
| 236 | * packet is received with an error. |
| 237 | */ |
| 238 | #define ED_IMR_RXEE 0x04 |
| 239 | |
| 240 | /* |
| 241 | * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever |
| 242 | * a transmission results in an error. |
| 243 | */ |
| 244 | #define ED_IMR_TXEE 0x08 |
| 245 | |
| 246 | /* |
| 247 | * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever |
| 248 | * the receive ring-buffer is overrun. i.e. when the boundry pointer is exceeded. |
| 249 | */ |
| 250 | #define ED_IMR_OVWE 0x10 |
| 251 | |
| 252 | /* |
| 253 | * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever |
| 254 | * the MSB of one or more of the Network Statistics counters has been set. |
| 255 | */ |
| 256 | #define ED_IMR_CNTE 0x20 |
| 257 | |
| 258 | /* |
| 259 | * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated |
| 260 | * when a remote DMA transfer has completed. |
| 261 | */ |
| 262 | #define ED_IMR_RDCE 0x40 |
| 263 | |
| 264 | /* |
| 265 | * bit 7 is unused/reserved |
| 266 | */ |
| 267 | |
| 268 | /* |
| 269 | * Data Configuration Register (DCR) definitions |
| 270 | */ |
| 271 | |
| 272 | /* |
| 273 | * WTS: Word Transfer Select. WTS establishes byte or word transfers for |
| 274 | * both remote and local DMA transfers |
| 275 | */ |
| 276 | #define ED_DCR_WTS 0x01 |
| 277 | |
| 278 | /* |
| 279 | * BOS: Byte Order Select. BOS sets the byte order for the host. |
| 280 | * Should be 0 for 80x86, and 1 for 68000 series processors |
| 281 | */ |
| 282 | #define ED_DCR_BOS 0x02 |
| 283 | |
| 284 | /* |
| 285 | * LAS: Long Address Select. When LAS is 1, the contents of the remote |
| 286 | * DMA registers RSAR0 and RSAR1 are used to provide A16-A31 |
| 287 | */ |
| 288 | #define ED_DCR_LAS 0x04 |
| 289 | |
| 290 | /* |
| 291 | * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2 |
| 292 | * of the TCR must also be programmed for loopback operation. |
| 293 | * When 1, normal operation is selected. |
| 294 | */ |
| 295 | #define ED_DCR_LS 0x08 |
| 296 | |
| 297 | /* |
| 298 | * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer |
| 299 | * under program control. When 1, remote DMA is automatically initiated |
| 300 | * and the boundry pointer is automatically updated |
| 301 | */ |
| 302 | #define ED_DCR_AR 0x10 |
| 303 | |
| 304 | /* |
| 305 | * FT0, FT1: Fifo Threshold select. |
| 306 | * FT1 FT0 Word-width Byte-width |
| 307 | * 0 0 1 word 2 bytes |
| 308 | * 0 1 2 words 4 bytes |
| 309 | * 1 0 4 words 8 bytes |
| 310 | * 1 1 8 words 12 bytes |
| 311 | * |
| 312 | * During transmission, the FIFO threshold indicates the number of bytes |
| 313 | * or words that the FIFO has filled from the local DMA before BREQ is |
| 314 | * asserted. The transmission threshold is 16 bytes minus the receiver |
| 315 | * threshold. |
| 316 | */ |
| 317 | #define ED_DCR_FT0 0x20 |
| 318 | #define ED_DCR_FT1 0x40 |
| 319 | |
| 320 | /* |
| 321 | * bit 7 (0x80) is unused/reserved |
| 322 | */ |
| 323 | |
| 324 | /* |
| 325 | * Transmit Configuration Register (TCR) definitions |
| 326 | */ |
| 327 | |
| 328 | /* |
| 329 | * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC |
| 330 | * is not appended by the transmitter. |
| 331 | */ |
| 332 | #define ED_TCR_CRC 0x01 |
| 333 | |
| 334 | /* |
| 335 | * LB0, LB1: Loopback control. These two bits set the type of loopback that is |
| 336 | * to be performed. |
| 337 | * |
| 338 | * LB1 LB0 mode |
| 339 | * 0 0 0 - normal operation (DCR_LS = 0) |
| 340 | * 0 1 1 - internal loopback (DCR_LS = 0) |
| 341 | * 1 0 2 - external loopback (DCR_LS = 1) |
| 342 | * 1 1 3 - external loopback (DCR_LS = 0) |
| 343 | */ |
| 344 | #define ED_TCR_LB0 0x02 |
| 345 | #define ED_TCR_LB1 0x04 |
| 346 | |
| 347 | /* |
| 348 | * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows |
| 349 | * another station to disable the NIC's transmitter by transmitting to |
| 350 | * a multicast address hashing to bit 62. Reception of a multicast address |
| 351 | * hashing to bit 63 enables the transmitter. |
| 352 | */ |
| 353 | #define ED_TCR_ATD 0x08 |
| 354 | |
| 355 | /* |
| 356 | * OFST: Collision Offset enable. This bit when set modifies the backoff |
| 357 | * algorithm to allow prioritization of nodes. |
| 358 | */ |
| 359 | #define ED_TCR_OFST 0x10 |
| 360 | |
| 361 | /* |
| 362 | * bits 5, 6, and 7 are unused/reserved |
| 363 | */ |
| 364 | |
| 365 | /* |
| 366 | * Transmit Status Register (TSR) definitions |
| 367 | */ |
| 368 | |
| 369 | /* |
| 370 | * PTX: Packet Transmitted. Indicates successful transmission of packet. |
| 371 | */ |
| 372 | #define ED_TSR_PTX 0x01 |
| 373 | |
| 374 | /* |
| 375 | * bit 1 (0x02) is unused/reserved |
| 376 | */ |
| 377 | |
| 378 | /* |
| 379 | * COL: Transmit Collided. Indicates that the transmission collided at least |
| 380 | * once with another station on the network. |
| 381 | */ |
| 382 | #define ED_TSR_COL 0x04 |
| 383 | |
| 384 | /* |
| 385 | * ABT: Transmit aborted. Indicates that the transmission was aborted due to |
| 386 | * excessive collisions. |
| 387 | */ |
| 388 | #define ED_TSR_ABT 0x08 |
| 389 | |
| 390 | /* |
| 391 | * CRS: Carrier Sense Lost. Indicates that carrier was lost during the |
| 392 | * transmission of the packet. (Transmission is not aborted because |
| 393 | * of a loss of carrier) |
| 394 | */ |
| 395 | #define ED_TSR_CRS 0x10 |
| 396 | |
| 397 | /* |
| 398 | * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/ |
| 399 | * transmission memory before the FIFO emptied. Transmission of the |
| 400 | * packet was aborted. |
| 401 | */ |
| 402 | #define ED_TSR_FU 0x20 |
| 403 | |
| 404 | /* |
| 405 | * CDH: CD Heartbeat. Indicates that the collision detection circuitry |
| 406 | * isn't working correctly during a collision heartbeat test. |
| 407 | */ |
| 408 | #define ED_TSR_CDH 0x40 |
| 409 | |
| 410 | /* |
| 411 | * OWC: Out of Window Collision: Indicates that a collision occurred after |
| 412 | * a slot time (51.2us). The transmission is rescheduled just as in |
| 413 | * normal collisions. |
| 414 | */ |
| 415 | #define ED_TSR_OWC 0x80 |
| 416 | |
| 417 | /* |
| 418 | * Receiver Configuration Register (RCR) definitions |
| 419 | */ |
| 420 | |
| 421 | /* |
| 422 | * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1, |
| 423 | * packets with CRC and frame errors are not discarded. |
| 424 | */ |
| 425 | #define ED_RCR_SEP 0x01 |
| 426 | |
| 427 | /* |
| 428 | * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded. |
| 429 | * If set to 1, packets with less than 64 byte are not discarded. |
| 430 | */ |
| 431 | #define ED_RCR_AR 0x02 |
| 432 | |
| 433 | /* |
| 434 | * AB: Accept Broadcast. If set, packets sent to the broadcast address will be |
| 435 | * accepted. |
| 436 | */ |
| 437 | #define ED_RCR_AB 0x04 |
| 438 | |
| 439 | /* |
| 440 | * AM: Accept Multicast. If set, packets sent to a multicast address are checked |
| 441 | * for a match in the hashing array. If clear, multicast packets are ignored. |
| 442 | */ |
| 443 | #define ED_RCR_AM 0x08 |
| 444 | |
| 445 | /* |
| 446 | * PRO: Promiscuous Physical. If set, all packets with a physical addresses are |
| 447 | * accepted. If clear, a physical destination address must match this |
| 448 | * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM |
| 449 | * must also be set. In addition, the multicast hashing array must be set |
| 450 | * to all 1's so that all multicast addresses are accepted. |
| 451 | */ |
| 452 | #define ED_RCR_PRO 0x10 |
| 453 | |
| 454 | /* |
| 455 | * MON: Monitor Mode. If set, packets will be checked for good CRC and framing, |
| 456 | * but are not stored in the ring-buffer. If clear, packets are stored (normal |
| 457 | * operation). |
| 458 | */ |
| 459 | #define ED_RCR_MON 0x20 |
| 460 | |
| 461 | /* |
| 462 | * bits 6 and 7 are unused/reserved. |
| 463 | */ |
| 464 | |
| 465 | /* |
| 466 | * Receiver Status Register (RSR) definitions |
| 467 | */ |
| 468 | |
| 469 | /* |
| 470 | * PRX: Packet Received without error. |
| 471 | */ |
| 472 | #define ED_RSR_PRX 0x01 |
| 473 | |
| 474 | /* |
| 475 | * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame |
| 476 | * alignment errors. |
| 477 | */ |
| 478 | #define ED_RSR_CRC 0x02 |
| 479 | |
| 480 | /* |
| 481 | * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on |
| 482 | * a byte boundry and the CRC did not match at the last byte boundry. |
| 483 | */ |
| 484 | #define ED_RSR_FAE 0x04 |
| 485 | |
| 486 | /* |
| 487 | * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA) |
| 488 | * causing it to overrun. Reception of the packet is aborted. |
| 489 | */ |
| 490 | #define ED_RSR_FO 0x08 |
| 491 | |
| 492 | /* |
| 493 | * MPA: Missed Packet. Indicates that the received packet couldn't be stored in |
| 494 | * the ring-buffer because of insufficient buffer space (exceeding the |
| 495 | * boundry pointer), or because the transfer to the ring-buffer was inhibited |
| 496 | * by RCR_MON - monitor mode. |
| 497 | */ |
| 498 | #define ED_RSR_MPA 0x10 |
| 499 | |
| 500 | /* |
| 501 | * PHY: Physical address. If 0, the packet received was sent to a physical address. |
| 502 | * If 1, the packet was accepted because of a multicast/broadcast address |
| 503 | * match. |
| 504 | */ |
| 505 | #define ED_RSR_PHY 0x20 |
| 506 | |
| 507 | /* |
| 508 | * DIS: Receiver Disabled. Set to indicate that the receiver has enetered monitor |
| 509 | * mode. Cleared when the receiver exits monitor mode. |
| 510 | */ |
| 511 | #define ED_RSR_DIS 0x40 |
| 512 | |
| 513 | /* |
| 514 | * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs |
| 515 | * are active, and the transceiver has set the CD line as a result of the |
| 516 | * jabber. |
| 517 | */ |
| 518 | #define ED_RSR_DFR 0x80 |
| 519 | |
| 520 | /* |
| 521 | * receive ring discriptor |
| 522 | * |
| 523 | * The National Semiconductor DS8390 Network interface controller uses |
| 524 | * the following receive ring headers. The way this works is that the |
| 525 | * memory on the interface card is chopped up into 256 bytes blocks. |
| 526 | * A contiguous portion of those blocks are marked for receive packets |
| 527 | * by setting start and end block #'s in the NIC. For each packet that |
| 528 | * is put into the receive ring, one of these headers (4 bytes each) is |
| 529 | * tacked onto the front. |
| 530 | */ |
| 531 | struct ed_ring { |
| 532 | struct edr_status { /* received packet status */ |
| 533 | u_char rs_prx:1, /* packet received intack */ |
| 534 | rs_crc:1, /* crc error */ |
| 535 | rs_fae:1, /* frame alignment error */ |
| 536 | rs_fo:1, /* fifo overrun */ |
| 537 | rs_mpa:1, /* packet received intack */ |
| 538 | rs_phy:1, /* packet received intack */ |
| 539 | rs_dis:1, /* packet received intack */ |
| 540 | rs_dfr:1; /* packet received intack */ |
| 541 | } ed_rcv_status; /* received packet status */ |
| 542 | u_char next_packet; /* pointer to next packet */ |
| 543 | u_short count; /* bytes in packet (length + 4) */ |
| 544 | }; |
| 545 | |
| 546 | /* |
| 547 | * Common constants |
| 548 | */ |
| 549 | #define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */ |
| 550 | #define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */ |
| 551 | |
| 552 | /* |
| 553 | * Vendor types |
| 554 | */ |
| 555 | #define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */ |
| 556 | #define ED_VENDOR_3COM 0x01 /* 3Com */ |
| 557 | |
| 558 | /* |
| 559 | * Compile-time config flags |
| 560 | */ |
| 561 | /* |
| 562 | * this sets the default for enabling/disablng the tranceiver |
| 563 | */ |
| 564 | #define ED_FLAGS_DISABLE_TRANCEIVER 0x01 |
| 565 | |
| 566 | /* |
| 567 | * Definitions for Western digital/SMC WD80x3 series ASIC |
| 568 | */ |
| 569 | /* |
| 570 | * Memory Select Register (MSR) |
| 571 | */ |
| 572 | #define ED_WD_MSR 0 |
| 573 | |
| 574 | #define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */ |
| 575 | #define ED_WD_MSR_MENB 0x40 /* Memory enable */ |
| 576 | #define ED_WD_MSR_RST 0x80 /* Reset board */ |
| 577 | |
| 578 | /* |
| 579 | * Interface Configuration Register (ICR) |
| 580 | */ |
| 581 | #define ED_WD_ICR 1 |
| 582 | |
| 583 | #define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */ |
| 584 | #define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */ |
| 585 | #define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */ |
| 586 | #define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */ |
| 587 | #define ED_WD_ICR_RLA 0x10 /* recall LAN address */ |
| 588 | #define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */ |
| 589 | #define ED_WD_ICR_RIO 0x40 /* recall i/o address */ |
| 590 | #define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */ |
| 591 | |
| 592 | /* |
| 593 | * IO Address Register (IAR) |
| 594 | */ |
| 595 | #define ED_WD_IAR 2 |
| 596 | |
| 597 | /* |
| 598 | * EEROM Address Register |
| 599 | */ |
| 600 | #define ED_WD_EAR 3 |
| 601 | |
| 602 | /* |
| 603 | * Interrupt Request Register (IRR) |
| 604 | */ |
| 605 | #define ED_WD_IRR 4 |
| 606 | |
| 607 | #define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */ |
| 608 | #define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */ |
| 609 | #define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */ |
| 610 | #define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */ |
| 611 | #define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */ |
| 612 | |
| 613 | /* |
| 614 | * The three bit of the encoded IRQ are decoded as follows: |
| 615 | * |
| 616 | * IR2 IR1 IR0 IRQ |
| 617 | * 0 0 0 2/9 |
| 618 | * 0 0 1 3 |
| 619 | * 0 1 0 5 |
| 620 | * 0 1 1 7 |
| 621 | * 1 0 0 10 |
| 622 | * 1 0 1 11 |
| 623 | * 1 1 0 15 |
| 624 | * 1 1 1 4 |
| 625 | */ |
| 626 | #define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */ |
| 627 | #define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */ |
| 628 | #define ED_WD_IRR_IEN 0x80 /* Interrupt enable */ |
| 629 | |
| 630 | /* |
| 631 | * LA Address Register (LAAR) |
| 632 | */ |
| 633 | #define ED_WD_LAAR 5 |
| 634 | |
| 635 | #define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */ |
| 636 | #define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */ |
| 637 | #define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */ |
| 638 | #define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */ |
| 639 | |
| 640 | /* i/o base offset to station address/card-ID PROM */ |
| 641 | #define ED_WD_PROM 8 |
| 642 | |
| 643 | /* i/o base offset to CARD ID */ |
| 644 | #define ED_WD_CARD_ID ED_WD_PROM+6 |
| 645 | |
| 646 | #define ED_TYPE_WD8003S 0x02 |
| 647 | #define ED_TYPE_WD8003E 0x03 |
| 648 | #define ED_TYPE_WD8013EBT 0x05 |
| 649 | #define ED_TYPE_WD8013EB 0x27 |
| 650 | #define ED_TYPE_WD8013EBP 0x2c |
| 651 | #define ED_TYPE_WD8013EPC 0x29 |
| 652 | |
| 653 | /* Bit definitions in card ID */ |
| 654 | #define ED_WD_REV_MASK 0x1f /* Revision mask */ |
| 655 | #define ED_WD_SOFTCONFIG 0x20 /* Soft config */ |
| 656 | #define ED_WD_LARGERAM 0x40 /* Large RAM */ |
| 657 | #define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */ |
| 658 | |
| 659 | /* |
| 660 | * Checksum total. All 8 bytes in station address PROM will add up to this |
| 661 | */ |
| 662 | #define ED_WD_ROM_CHECKSUM_TOTAL 0xFF |
| 663 | |
| 664 | #define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */ |
| 665 | #define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */ |
| 666 | #define ED_WD_IO_PORTS 32 /* # of i/o addresses used */ |
| 667 | |
| 668 | #define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */ |
| 669 | |
| 670 | /* |
| 671 | * Definitions for 3Com 3c503 |
| 672 | */ |
| 673 | #define ED_3COM_NIC_OFFSET 0 |
| 674 | #define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */ |
| 675 | |
| 676 | /* |
| 677 | * XXX - The I/O address range is fragmented in the 3c503; this is the |
| 678 | * number of regs at iobase. |
| 679 | */ |
| 680 | #define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */ |
| 681 | |
| 682 | #define ED_3COM_PAGE_OFFSET 0x20 /* memory starts in second bank */ |
| 683 | |
| 684 | /* |
| 685 | * Page Start Register. Must match PSTART in NIC |
| 686 | */ |
| 687 | #define ED_3COM_PSTR 0 |
| 688 | |
| 689 | /* |
| 690 | * Page Stop Register. Must match PSTOP in NIC |
| 691 | */ |
| 692 | #define ED_3COM_PSPR 1 |
| 693 | |
| 694 | /* |
| 695 | * Drq Timer Register. Determines number of bytes to be transfered during |
| 696 | * a DMA burst. |
| 697 | */ |
| 698 | #define ED_3COM_DQTR 2 |
| 699 | |
| 700 | /* |
| 701 | * Base Configuration Register. Read-only register which contains the |
| 702 | * board-configured I/O base address of the adapter. Bit encoded. |
| 703 | */ |
| 704 | #define ED_3COM_BCFR 3 |
| 705 | |
| 706 | #define ED_3COM_BCFR_2E0 0x01 |
| 707 | #define ED_3COM_BCFR_2A0 0x02 |
| 708 | #define ED_3COM_BCFR_280 0x04 |
| 709 | #define ED_3COM_BCFR_250 0x08 |
| 710 | #define ED_3COM_BCFR_350 0x10 |
| 711 | #define ED_3COM_BCFR_330 0x20 |
| 712 | #define ED_3COM_BCFR_310 0x40 |
| 713 | #define ED_3COM_BCFR_300 0x80 |
| 714 | |
| 715 | /* |
| 716 | * EPROM Configuration Register. Read-only register which contains the |
| 717 | * board-configured memory base address. Bit encoded. |
| 718 | */ |
| 719 | #define ED_3COM_PCFR 4 |
| 720 | |
| 721 | #define ED_3COM_PCFR_C8000 0x10 |
| 722 | #define ED_3COM_PCFR_CC000 0x20 |
| 723 | #define ED_3COM_PCFR_D8000 0x40 |
| 724 | #define ED_3COM_PCFR_DC000 0x80 |
| 725 | |
| 726 | /* |
| 727 | * GA Configuration Register. Gate-Array Configuration Register. |
| 728 | */ |
| 729 | #define ED_3COM_GACFR 5 |
| 730 | |
| 731 | /* |
| 732 | * mbs2 mbs1 mbs0 start address |
| 733 | * 0 0 0 0x0000 |
| 734 | * 0 0 1 0x2000 |
| 735 | * 0 1 0 0x4000 |
| 736 | * 0 1 1 0x6000 |
| 737 | * |
| 738 | * Note that with adapters with only 8K, the setting for 0x2000 must |
| 739 | * always be used. |
| 740 | */ |
| 741 | #define ED_3COM_GACFR_MBS0 0x01 |
| 742 | #define ED_3COM_GACFR_MBS1 0x02 |
| 743 | #define ED_3COM_GACFR_MBS2 0x04 |
| 744 | |
| 745 | #define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */ |
| 746 | #define ED_3COM_GACFR_TEST 0x10 /* for GA testing */ |
| 747 | #define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */ |
| 748 | #define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */ |
| 749 | #define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */ |
| 750 | |
| 751 | /* |
| 752 | * Control Register. Miscellaneous control functions. |
| 753 | */ |
| 754 | #define ED_3COM_CR 6 |
| 755 | |
| 756 | #define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */ |
| 757 | #define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */ |
| 758 | #define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */ |
| 759 | #define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */ |
| 760 | #define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */ |
| 761 | #define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */ |
| 762 | #define ED_3COM_CR_DDIR 0x40 /* DMA direction select */ |
| 763 | #define ED_3COM_CR_START 0x80 /* Start DMA controller */ |
| 764 | |
| 765 | /* |
| 766 | * Status Register. Miscellaneous status information. |
| 767 | */ |
| 768 | #define ED_3COM_STREG 7 |
| 769 | |
| 770 | #define ED_3COM_STREG_REV 0x07 /* GA revision */ |
| 771 | #define ED_3COM_STREG_DIP 0x08 /* DMA in progress */ |
| 772 | #define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */ |
| 773 | #define ED_3COM_STREG_OFLW 0x20 /* Overflow */ |
| 774 | #define ED_3COM_STREG_UFLW 0x40 /* Underflow */ |
| 775 | #define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */ |
| 776 | |
| 777 | /* |
| 778 | * Interrupt/DMA Configuration Register |
| 779 | */ |
| 780 | #define ED_3COM_IDCFR 8 |
| 781 | |
| 782 | #define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */ |
| 783 | #define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */ |
| 784 | #define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */ |
| 785 | #define ED_3COM_IDCFR_UNUSED 0x08 /* not used */ |
| 786 | #define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */ |
| 787 | #define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */ |
| 788 | #define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */ |
| 789 | #define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */ |
| 790 | |
| 791 | /* |
| 792 | * DMA Address Register MSB |
| 793 | */ |
| 794 | #define ED_3COM_DAMSB 9 |
| 795 | |
| 796 | /* |
| 797 | * DMA Address Register LSB |
| 798 | */ |
| 799 | #define ED_3COM_DALSB 0x0a |
| 800 | |
| 801 | /* |
| 802 | * Vector Pointer Register 2 |
| 803 | */ |
| 804 | #define ED_3COM_VPTR2 0x0b |
| 805 | |
| 806 | /* |
| 807 | * Vector Pointer Register 1 |
| 808 | */ |
| 809 | #define ED_3COM_VPTR1 0x0c |
| 810 | |
| 811 | /* |
| 812 | * Vector Pointer Register 0 |
| 813 | */ |
| 814 | #define ED_3COM_VPTR0 0x0d |
| 815 | |
| 816 | /* |
| 817 | * Register File Access MSB |
| 818 | */ |
| 819 | #define ED_3COM_RFMSB 0x0e |
| 820 | |
| 821 | /* |
| 822 | * Register File Access LSB |
| 823 | */ |
| 824 | #define ED_3COM_RFLSB 0x0f |