| 1 | /* |
| 2 | * Copyright (c) 1991 The Regents of the University of California. |
| 3 | * All rights reserved. |
| 4 | * |
| 5 | * This code is derived from software contributed to Berkeley by |
| 6 | * Tim L. Tucker. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * 3. All advertising materials mentioning features or use of this software |
| 17 | * must display the following acknowledgement: |
| 18 | * This product includes software developed by the University of |
| 19 | * California, Berkeley and its contributors. |
| 20 | * 4. Neither the name of the University nor the names of its contributors |
| 21 | * may be used to endorse or promote products derived from this software |
| 22 | * without specific prior written permission. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 30 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 34 | * SUCH DAMAGE. |
| 35 | * |
| 36 | * A lot of this was derived from if_wereg.h and 3c503.asm. |
| 37 | */ |
| 38 | /* |
| 39 | * receive ring discriptor |
| 40 | * |
| 41 | * The National Semiconductor DS8390 Network interface controller uses |
| 42 | * the following receive ring headers. The way this works is that the |
| 43 | * memory on the interface card is chopped up into 256 bytes blocks. |
| 44 | * A contiguous portion of those blocks are marked for receive packets |
| 45 | * by setting start and end block #'s in the NIC. For each packet that |
| 46 | * is put into the receive ring, one of these headers (4 bytes each) is |
| 47 | * tacked onto the front. |
| 48 | */ |
| 49 | struct ec_ring { |
| 50 | struct ecr_status { /* received packet status */ |
| 51 | u_char rs_prx:1, /* packet received intack */ |
| 52 | rs_crc:1, /* crc error */ |
| 53 | rs_fae:1, /* frame alignment error */ |
| 54 | rs_fo:1, /* fifo overrun */ |
| 55 | rs_mpa:1, /* packet received intack */ |
| 56 | rs_phy:1, /* packet received intack */ |
| 57 | rs_dis:1, /* packet received intack */ |
| 58 | rs_dfr:1; /* packet received intack */ |
| 59 | } ec_rcv_status; /* received packet status */ |
| 60 | u_char ec_next_packet; /* pointer to next packet */ |
| 61 | u_short ec_count; /* bytes in packet (length + 4) */ |
| 62 | }; |
| 63 | |
| 64 | #define EC_PAGE_SIZE 256 |
| 65 | #define EC_TXBUF_SIZE 0x06 |
| 66 | #define EC_VMEM_OFFSET 0x20 |
| 67 | #define EC_RXBUF_OFFSET 0x26 |
| 68 | #define EC_RXBUF_END 0x40 |
| 69 | #define EC_ROM_OFFSET 8 |
| 70 | #define ETHER_ADDR_LEN 6 |
| 71 | #define ETHER_MIN_LEN 64 |
| 72 | #define ETHER_HDR_SIZE 14 |
| 73 | /* |
| 74 | * Share memory management parameters. |
| 75 | */ |
| 76 | #define XMIT_MTU 0x600 |
| 77 | #define SM_TSTART_PG 0x020 |
| 78 | #define SM_RSTART_PG 0x026 |
| 79 | #define SM_RSTOP_PG 0x040 |
| 80 | /* |
| 81 | * Description of header of each packet in receive area of shared memory. |
| 82 | */ |
| 83 | #define EN_RBUF_STAT 0x0 /* Received frame status. */ |
| 84 | #define EN_RBUF_NXT_PG 0x1 /* Page after this frame */ |
| 85 | #define EN_RBUF_SIZE_LO 0x2 /* Length of this frame */ |
| 86 | #define EN_RBUF_SIZE_HI 0x3 /* Length of this frame */ |
| 87 | #define EN_RBUF_NHDR 0x4 /* Length of above header area */ |
| 88 | /* |
| 89 | * E33 Control registers. (base + 40x) |
| 90 | */ |
| 91 | #define E33G 0x0 |
| 92 | #define E33G_STARTPG 0x0 |
| 93 | #define E33G_STOPPG 0x1 |
| 94 | #define E33G_NBURST 0x2 |
| 95 | #define E33G_IOBASE 0x3 |
| 96 | #define E33G_ROMBASE 0x4 |
| 97 | #define E33G_GACFR 0x5 |
| 98 | #define E33G_CNTRL 0x6 |
| 99 | #define E33G_STATUS 0x7 |
| 100 | #define E33G_IDCFR 0x8 |
| 101 | #define E33G_DMAAH 0x9 |
| 102 | #define E33G_DMAAL 0xa |
| 103 | #define E33G_VP2 0xb |
| 104 | #define E33G_VP1 0xc |
| 105 | #define E33G_VP0 0xd |
| 106 | #define E33G_FIFOH 0xe |
| 107 | #define E33G_FIFOL 0xf |
| 108 | /* |
| 109 | * Bits in E33G_GACFR register. |
| 110 | */ |
| 111 | #define EGACFR_NORM 0x49 |
| 112 | #define EGACFR_IRQOFF 0xc9 |
| 113 | /* |
| 114 | * Control bits for E33G_CNTRL |
| 115 | */ |
| 116 | #define ECNTRL_RESET 0x01 /* Software reset of ASIC and 8390. */ |
| 117 | #define ECNTRL_THIN 0x02 /* Enable thinnet interface. */ |
| 118 | #define ECNTRL_SAPROM 0x04 /* Map Address Prom. */ |
| 119 | #define ECNTRL_DBLBFR 0x20 /* FIFO Configuration bit */ |
| 120 | #define ECNTRL_OUTPUT 0x40 /* PC->3c503 direction if set*/ |
| 121 | #define ECNTRL_START 0x80 /* Start DMA Logic. */ |
| 122 | /* |
| 123 | * Bits in E33G status register. |
| 124 | */ |
| 125 | #define ESTAT_DPRDY 0x80 /* Data port of FIFO ready */ |
| 126 | #define ESTAT_UFLW 0x40 /* Tried to read FIFO when it was empty. */ |
| 127 | #define ESTAT_OFLW 0x20 /* Tried to write FIFO when it was full */ |
| 128 | #define ESTAT_DTC 0x10 /* Terminal count from PC bus DMA Logic */ |
| 129 | #define ESTAT_DIP 0x8 /* DMA in progress */ |
| 130 | /* |
| 131 | * 8390 chip registers. |
| 132 | */ |
| 133 | #define EN_CCMD 0x0 /* Chip's command register. */ |
| 134 | #define EN0_STARTPG 0x1 /* Starting page of ring buffer. */ |
| 135 | #define EN0_STOPPG 0x2 /* Ending page + 1 of ring buffer */ |
| 136 | #define EN0_BOUNDARY 0x3 /* Boundary page of ring buffer */ |
| 137 | #define EN0_TSR 0x4 /* Transmit status register. */ |
| 138 | #define EN0_TPSR 0x4 /* Transmit starting page. */ |
| 139 | #define EN0_TCNTLO 0x5 /* Low byte of tx byte count */ |
| 140 | #define EN0_TCNTHI 0x6 /* High byte of tx byte count */ |
| 141 | #define EN0_ISR 0x7 /* Interrupt status register. */ |
| 142 | #define EN0_RSARLO 0x8 /* Remote start address reg 0 */ |
| 143 | #define EN0_RSARHI 0x9 /* Remote start address reg 1 */ |
| 144 | #define EN0_RCNTLO 0xa /* Remote byte count reg */ |
| 145 | #define EN0_RCNTHI 0xb /* Remote byte count reg */ |
| 146 | #define EN0_RXCR 0xc /* RX Control reg */ |
| 147 | #define EN0_TXCR 0xd /* TX Control reg */ |
| 148 | #define EN0_COUNTER0 0xd /* Rcv alignment error counter */ |
| 149 | #define EN0_DCFG 0xe /* Data configuration reg */ |
| 150 | #define EN0_COUNTER1 0xe /* rcv CRC error counter */ |
| 151 | #define EN0_IMR 0xf /* Interrupt mask reg */ |
| 152 | #define EN0_COUNTER2 0xf /* rcv missed frame error counter */ |
| 153 | #define EN1_PHYS 0x1 /* boards physical enet addr. */ |
| 154 | #define EN1_CURPAG 0x7 /* current memory page. */ |
| 155 | #define EN1_MULT 0x8 /* multicast filter mask array (8 bytes) */ |
| 156 | /* |
| 157 | * Chip commands in EN_CCMD |
| 158 | */ |
| 159 | #define ENC_STOP 0x1 /* Stop the chip. */ |
| 160 | #define ENC_START 0x2 /* Start the chip */ |
| 161 | #define ENC_TRANS 0x4 /* Transmit a frame. */ |
| 162 | #define ENC_RREAD 0x8 /* Remote read. */ |
| 163 | #define ENC_RWRITE 0x10 /* Remote write */ |
| 164 | #define ENC_NODMA 0x20 /* No remote DMA used on this card */ |
| 165 | #define ENC_PAGE0 0x0 /* Select page 0 of chip regs */ |
| 166 | #define ENC_PAGE1 0x40 /* Select page 1 of chip regs */ |
| 167 | /* |
| 168 | * Commands for RX control reg |
| 169 | */ |
| 170 | #define ENRXCR_MON 0x20 /* Monitor mode (no packets rcvd) */ |
| 171 | #define ENRXCR_PROMP 0x10 /* Promiscuous phys addresses. */ |
| 172 | #define ENRXCR_MULTI 0x8 /* Multicast (if pass filter) */ |
| 173 | #define ENRXCR_BCST 0x4 /* Accept broadcasts */ |
| 174 | #define ENRXCR_BAD 0x3 /* Accept runts and bad CRC frames */ |
| 175 | /* |
| 176 | * Commands for TX control reg |
| 177 | */ |
| 178 | #define ENTXCR_LOOP 0x2 /* Set loopback mode */ |
| 179 | /* |
| 180 | * bits on the EN0_DCFG config register. |
| 181 | */ |
| 182 | #define ENDCFG_BM8 0x48 /* Set bust mode, 8 deep FIFO */ |
| 183 | /* |
| 184 | * Bits in the EN0_ISR Interrup Status Register |
| 185 | */ |
| 186 | #define ENISR_RX 0x1 /* receiver, no error */ |
| 187 | #define ENISR_TX 0x2 /* transmitter, no error */ |
| 188 | #define ENISR_RX_ERR 0x4 /* Receiver with error */ |
| 189 | #define ENISR_TX_ERR 0x8 /* Transmitter with error */ |
| 190 | #define ENISR_OVER 0x10 /* receiver overwrote the ring */ |
| 191 | #define ENISR_COUNTERS 0x20 /* Counters need emptying. */ |
| 192 | #define ENISR_RDC 0x40 /* Remote DMA complete. */ |
| 193 | #define ENISR_RESET 0x80 /* Reset completed */ |
| 194 | #define ENISR_ALL 0x3f /* Interrupts we will enable */ |
| 195 | /* |
| 196 | * Bits in received packet status byte and EN0_RSR |
| 197 | */ |
| 198 | #define ENPS_RXOK 0x1 /* received a good packet */ |
| 199 | /* |
| 200 | * Bits in TX status reg. |
| 201 | */ |
| 202 | #define ENTSR_PTX 0x1 /* Packet transmitted without error */ |
| 203 | #define ENTSR_COLL 0x4 /* Collided at least once */ |
| 204 | #define ENTSR_COLL16 0x8 /* Collided 16 times and was dropped */ |
| 205 | #define ENTSR_FU 0x20 /* TX FIFO Underrun */ |
| 206 | |