-
-#if defined(VAX780)
-#define ACCR 0x29 /* accelerator maintenance */
-#define WCSA 0x2c /* WCS address */
-#define WCSD 0x2d /* WCS data */
-#define SBIFS 0x30 /* SBI fault and status */
-#define SBIS 0x31 /* SBI silo */
-#define SBISC 0x32 /* SBI silo comparator */
-#define SBIMT 0x33 /* SBI maintenance */
-#define SBIER 0x34 /* SBI error register */
-#define SBITA 0x35 /* SBI timeout address */
-#define SBIQC 0x36 /* SBI quadword clear */
-#define MBRK 0x3c /* micro-program breakpoint */
-#endif
-
-#if defined(VAX750) || defined(VAX730)
-#define MCSR 0x17 /* machine check status register */
-#define CSRS 0x1c /* console storage receive status register */
-#define CSRD 0x1d /* console storage receive data register */
-#define CSTS 0x1e /* console storage transmit status register */
-#define CSTD 0x1f /* console storage transmit data register */
-#define TBDR 0x24 /* translation buffer disable register */
-#define CADR 0x25 /* cache disable register */
-#define MCESR 0x26 /* machine check error summary register */
-#define CAER 0x27 /* cache error */
-#define TB 0x3b /* translation buffer */
-#endif
-
-#if defined(VAX750) || defined(VAX730) || defined(VAX630)
-#define IUR 0x37 /* init unibus register */
+#if VAX8200
+#define RXCS1 0x50 /* receive csr, console line 1 */
+#define RXDB1 0x51 /* receive data buffer, console line 1 */
+#define TXCS1 0x52 /* transmit csr, console line 1 */
+#define TXDB1 0x53 /* transmit data buffer, console line 1 */
+#define RXCS2 0x54 /* etc */
+#define RXDB2 0x55
+#define TXCS2 0x56
+#define TXDB2 0x57
+#define RXCS3 0x58
+#define RXDB3 0x59
+#define TXCS3 0x5a
+#define TXDB3 0x5b
+#define RXCD 0x5c /* receive console data register */
+#define CACHEX 0x5d /* cache invalidate register */
+#define BINID 0x5e /* VAXBI node ID register */
+#define BISTOP 0x5f /* VAXBI stop register */