BSD 4_4 release

[unix-history] / usr / src / sys / hp300 / dev / dmareg.h

diff --git a/usr/src/sys/hp300/dev/dmareg.h b/usr/src/sys/hp300/dev/dmareg.h
index d1e412f..3b6fdbf 100644 (file)
--- a/usr/src/sys/hp300/dev/dmareg.h
+++ b/usr/src/sys/hp300/dev/dmareg.h
@@ -1,23 +1,46 @@
 /*
 /*

- * Copyright (c) 1982, 1990 The Regents of the University of California.
- * All rights reserved.
+ * Copyright (c) 1982, 1990, 1993
+ *     The Regents of the University of California.  All rights reserved.

  *
  *

- * %sccs.include.redist.c%
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *     This product includes software developed by the University of
+ *     California, Berkeley and its contributors.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.

  *
  *

- *     @(#)dmareg.h    7.1 (Berkeley) %G%
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *     @(#)dmareg.h    8.1 (Berkeley) 6/10/93

  */
 
  */
 

+#include <hp/dev/iotypes.h>            /* XXX */
+

 /*
  * Hardware layout for the 98620[ABC]:
  *     98620A (old 320s?):     byte/word DMA in up to 64K chunks
  *     98620B (320s only):     98620A with programmable IPL
  *     98620C (all others):    byte/word/longword DMA in up to 4Gb chunks
  */
 /*
  * Hardware layout for the 98620[ABC]:
  *     98620A (old 320s?):     byte/word DMA in up to 64K chunks
  *     98620B (320s only):     98620A with programmable IPL
  *     98620C (all others):    byte/word/longword DMA in up to 4Gb chunks
  */

-#define v_char         volatile char
-#define        v_int           volatile int
-#define vu_char                volatile u_char
-#define vu_short       volatile u_short
-#define vu_int         volatile u_int

 
 struct dmaBdevice {
        v_char          *dmaB_addr;
 
 struct dmaBdevice {
        v_char          *dmaB_addr;


@@ -51,7 +74,7 @@ struct        dmareg {
 #define        DMAINTLVL       5
 
 /* addresses */
 #define        DMAINTLVL       5
 
 /* addresses */

-#define        DMA_BASE        IOV(0x500000)
+#define        DMA_BASE        IIOV(0x500000)

 
 /* command bits */
 #define        DMA_ENAB        0x0001
 
 /* command bits */
 #define        DMA_ENAB        0x0001


@@ -89,24 +112,24 @@ struct     dmareg {
 #define        DMA_STAT(dc)    dc->sc_Bhwaddr->dmaB_stat
 
 #if defined(HP320)
 #define        DMA_STAT(dc)    dc->sc_Bhwaddr->dmaB_stat
 
 #if defined(HP320)

-#define        DMA_ARM(dc, ix) \
+#define        DMA_ARM(dc)     \

        if (dc->sc_type == DMA_B) { \
                register struct dmaBdevice *dma = dc->sc_Bhwaddr; \
        if (dc->sc_type == DMA_B) { \
                register struct dmaBdevice *dma = dc->sc_Bhwaddr; \

-               dma->dmaB_addr = dc->sc_addr[ix]; \
-               dma->dmaB_count = dc->sc_count[ix] - 1; \
+               dma->dmaB_addr = dc->sc_cur->dc_addr; \
+               dma->dmaB_count = dc->sc_cur->dc_count - 1; \

                dma->dmaB_cmd = dc->sc_cmd; \
        } else { \
                register struct dmadevice *dma = dc->sc_hwaddr; \
                dma->dmaB_cmd = dc->sc_cmd; \
        } else { \
                register struct dmadevice *dma = dc->sc_hwaddr; \

-               dma->dma_addr = dc->sc_addr[ix]; \
-               dma->dma_count = dc->sc_count[ix] - 1; \
+               dma->dma_addr = dc->sc_cur->dc_addr; \
+               dma->dma_count = dc->sc_cur->dc_count - 1; \

                dma->dma_cmd = dc->sc_cmd; \
        }
 #else
                dma->dma_cmd = dc->sc_cmd; \
        }
 #else

-#define        DMA_ARM(dc, ix) \
+#define        DMA_ARM(dc)     \

        { \
                register struct dmadevice *dma = dc->sc_hwaddr; \
        { \
                register struct dmadevice *dma = dc->sc_hwaddr; \

-               dma->dma_addr = dc->sc_addr[ix]; \
-               dma->dma_count = dc->sc_count[ix] - 1; \
+               dma->dma_addr = dc->sc_cur->dc_addr; \
+               dma->dma_count = dc->sc_cur->dc_count - 1; \

                dma->dma_cmd = dc->sc_cmd; \
        }
 #endif
                dma->dma_cmd = dc->sc_cmd; \
        }
 #endif