+#define DEBCANCEL 0x8000 /* debug cancel command */
+
+/*
+ * npreg.h version 1.3
+ *
+ * This version retrieved: 8/18/86 @ 18:58:46
+ * This delta created: 8/18/86 @ 18:27:42
+ */
+
+/*
+ * NPREG.H
+ *
+ * This file contain definitions of specific hardware interest
+ * to be used when communicating with the NI1510 Network Processor
+ * Board. More complete information can be found in the NI1510
+ * Multibus compatible Ethernet Communications Processor Hardware
+ * Specification.
+ */
+
+/*
+ * npcmd.h version 1.3
+ *
+ * This version retrieved: 8/18/86 @ 18:58:45
+ * This delta created: 8/18/86 @ 18:27:38
+ */
+#ifdef KERNEL
+# define IoVOID 0
+#else
+# define IoVOID IOC_VOID
+#endif
+
+#define NPRESET (IoVOID|0x01) /* reset the board */
+#define NPSTART (IoVOID|0x04) /* start board execution */
+#define NPGPANIC (IoVOID|0x05) /* Get panic message */
+#define NPINIT (IoVOID|0x06) /* initialize software on board */
+#define NPSTATS (IoVOID|0x07)
+#define NPRCSR0 (IoVOID|0x08) /* read CSR0 */
+#define NPRCSR1 (IoVOID|0x09) /* read CSR1 */
+#define NPRCSR2 (IoVOID|0x0a) /* read CSR2 */
+#define NPRCSR3 (IoVOID|0x0b) /* read CSR3 */
+#define NPWCSR0 (IoVOID|0x0c) /* write CSR0 */
+#define NPWCSR1 (IoVOID|0x0d) /* write CSR1 */
+#define NPWCSR2 (IoVOID|0x0e) /* write CSR2 */
+#define NPWCSR3 (IoVOID|0x0f) /* write CSR3 */
+#define NPPOLL (IoVOID|0x10)
+#define NPKILL (IoVOID|0x11)
+#define NPSETPROT (IoVOID|0x12) /* set the protocol to use */
+#define NPSETBOARD (IoVOID|0x13) /* set board to use */
+#define NPSETNPDEB (IoVOID|0x14) /* set nc debuging level */
+#define NPSETADDR (IoVOID|0x15) /* set host address */
+#define NPNETBOOT (IoVOID|0x16) /* boot from the network */
+#define NPSETLAST (IoVOID|0x17) /* set last command flag in NPIO */
+#define NPCLRICNT (IoVOID|0x18) /* clear interupt count */
+#define NPGETICNT (IoVOID|0x19) /* get interupt count */
+#define NPGETIVEC (IoVOID|0x1a) /* get interupt vector */
+#define NPMAPMEM (IoVOID|0x1b) /* map user memory to shmem */
+
+#define NP_SET 1031 /* set memory mapping */
+#define NP_USET 1032 /* unset memory mapping */
+
+struct np_mem {
+ long mem_type;
+ char *mem_addr;
+ long mem_count;
+} ;
+
+#define NNPCNN 4 /* Number of connections per board */
+#define NPUNIT(a) ((minor(a) >> 4) & 0x0F)
+#define NPCONN(a) ((minor(a)) & 0x03)
+
+#define TRUE 1
+#define FALSE 0
+
+#define IBOOTADDR 0xF8000l /* Addr of 80186 Boot ROM */
+#define INETBOOT 0xF8087l
+#define IXEQADDR 0x400 /* Where to begin Board image XEQ */
+#define DIAGTIME 1200 /* Time for timeout /HZ seconds */
+
+#define DELAYTIME 1000000L /* delay count */
+#define NPDELAY(N) {register int n = (N) >> 1; while(--n > 0); }
+
+/* Handy macros for talking to the Board */
+
+#define RESET(x) (WCSR3(x->iobase,0xff))
+#define CLEARINT(x) {unsign16 y; y = RCSR2(x->iobase); }
+#define INTNI(x) (WCSR1(x->iobase,0xFF))
+
+/* Command and Status Register (CSR) Definitions */
+
+/*
+ * CSR0 is the only direct means for data transfer between the host processor
+ * and the 3510. Access is controlled by the 80186 who sets the CSR1 Enable and
+ * Ready bits to allow writing here. Writing to this register will always
+ * result in an interrupt to the 80186.
+ */
+
+/*
+ * Bit definitions for CSR1.
+ */
+
+#define NPRFU 0x01 /* Reserved for Future Use */
+#define NPHOK 0x02 /* Hardware OK */
+#define NPLAN 0x04 /* Logic 0 indicates operational LAN exists */
+#define NP_IP 0x08 /* Interrupt pending from this board */
+#define NP_IE 0x10 /* Interrupts enabled for this board */
+#define NPRDR 0x20 /* Set when 80186 writes data into CSR0 */
+#define NPRDY 0x40 /* CSR0 ready to accept data */
+#define NPENB 0x80 /* CSR0 available for use by the host */
+
+/*
+ * Bit defintions for CSR0 Command Block
+ */
+
+#define NPLST 0x20 /* Last Command */
+#define NPCMD 0x80 /* Shared Memory Address */
+#define NPBGN 0x200 /* Begin Execution in On-Board Memory */
+#define NPCBI 0x800 /* Interrupt at completion of Command Block */
+#define NPDMP 0x2000 /* Dump 80186 On-Board Memory to Multibus */
+#define NPLD 0x8000 /* Load 80186 On-board Memory from Multibus */
+
+/*
+ * CSR0 Count definitions. These are the lengths of the Command Blocks for the
+ * CSR0 commands above (not counting the Command Word itself).
+ */
+
+#define LSTCNT 0
+#define CMDCNT 2
+#define BGNCNT 2
+#define CBICNT 1
+#define DMPCNT 5
+#define LDCNT 5
+#define IOCNT 5
+
+/* Macros for reading and writing CSR's (Control and Status Registers) */
+
+#define WCSR0(x,y) ((x)->CSR0 = y)
+#define WCSR1(x,y) ((x)->CSR1 = y)
+#define WCSR2(x,y) ((x)->CSR2 = y)
+#define WCSR3(x,y) ((x)->CSR3 = y)
+
+#define RCSR0(x) ((x)->CSR0)
+#define RCSR1(x) ((x)->CSR1)
+#define RCSR2(x) ((x)->CSR2)
+#define RCSR3(x) ((x)->CSR3)
+
+struct npconn {
+
+ struct npmaster *unit; /* Unit number (board) of this connection */
+ unsign16 protocol; /* Protocol used on this connection */
+ struct buf np_wbuf; /* write buf structure for raw access */
+ struct buf np_rbuf; /* read buf structure for raw access */
+};
+
+/* ICP Board Requests */
+
+#define ICPLOAD 0x02
+#define ICPDUMP 0x03
+#define ICPPANIC 0x05
+#define ICPPOLL 0x10
+
+/*
+ * npdebug.h version 1.3
+ *
+ * This version retrieved: 8/18/86 @ 18:58:46
+ * This delta created: 8/18/86 @ 18:27:39
+ */
+
+/*
+ * Debugging Constants
+ */
+
+#define DEBENTRY 0x0001 /* debug entry points */
+#define DEBMEM 0x0002 /* debug memory */
+#define DEBREQ 0x0004 /* debug requests */
+#define DEBCQE 0x0008 /* debug cqe's */
+#define DEBCQ 0x0010 /* debug cq's */
+#define DEBMAINT 0x0020 /* debug maintainance requests */
+#define DEBINTR 0x0040 /* debug interrupt routines */
+#define DEBINIT 0x0080 /* debug initialization routines */
+#define DEBIFC 0x0100 /* debug Internal function codes */
+#define DEBIOCTL 0x0200 /* debug ioctl calls */
+#define DEBOPEN 0x0400 /* debug open calls */
+#define DEBIO 0x0800 /* debug read & write calls */
+#define DEBCSR 0x1000 /* debug CSR commands */
+#define DEBLOCK 0x2000 /* debug lock / unlock calls */
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