fix to reeves fix of dgo handling (reset b_active to 1)

[unix-history] / usr / src / sys / vax / uba / ubavar.h

diff --git a/usr/src/sys/vax/uba/ubavar.h b/usr/src/sys/vax/uba/ubavar.h
index c41e205..9ec4b61 100644 (file)
--- a/usr/src/sys/vax/uba/ubavar.h
+++ b/usr/src/sys/vax/uba/ubavar.h
@@ -1,141 +1,192 @@
-/*     ubavar.h        4.3     %G%     */
+/*     ubavar.h        4.25    82/04/11        */

 
 /*
 
 /*

- * Unibus adapter
+ * This file contains definitions related to the kernel structures
+ * for dealing with the unibus adapters.
+ *
+ * Each uba has a uba_hd structure.
+ * Each unibus controller which is not a device has a uba_ctlr structure.
+ * Each unibus device has a uba_device structure.

  */
 
  */
 

-#define        UBA0            0x80060000      /* sys virt i/o for UBA 0 */
-#define        UBA0_DEV (UBA0+0x2000-0160000)  /* sys virt of device regs */
-#define        UNIBASE 0760000                 /* UNIBUS phys base of i/o reg's */
+#ifndef LOCORE
+/*
+ * Per-uba structure.
+ *
+ * This structure holds the interrupt vector for the uba,
+ * and its address in physical and virtual space.  At boot time
+ * we determine the devices attached to the uba's and their
+ * interrupt vectors, filling in uh_vec.  We free the map
+ * register and bdp resources of the uba into the structures
+ * defined here.
+ *
+ * During normal operation, resources are allocated and returned
+ * to the structures here.  We watch the number of passive releases
+ * on each uba, and if the number is excessive may reset the uba.
+ * 
+ * When uba resources are needed and not available, or if a device
+ * which can tolerate no other uba activity (rk07) gets on the bus,
+ * then device drivers may have to wait to get to the bus and are
+ * queued here.  It is also possible for processes to block in
+ * the unibus driver in resource wait (mrwant, bdpwant); these
+ * wait states are also recorded here.
+ */
+struct uba_hd {
+       struct  uba_regs *uh_uba;       /* virt addr of uba */
+       struct  uba_regs *uh_physuba;   /* phys addr of uba */
+       int     (**uh_vec)();           /* interrupt vector */
+       struct  uba_device *uh_actf;    /* head of queue to transfer */
+       struct  uba_device *uh_actl;    /* tail of queue to transfer */
+       short   uh_mrwant;              /* someone is waiting for map reg */
+       short   uh_bdpwant;             /* someone awaits bdp's */
+       int     uh_bdpfree;             /* free bdp's */
+       int     uh_hangcnt;             /* number of ticks hung */
+       int     uh_zvcnt;               /* number of 0 vectors */
+       int     uh_errcnt;              /* number of errors */
+       int     uh_lastiv;              /* last free interrupt vector */
+       short   uh_users;               /* transient bdp use count */
+       short   uh_xclu;                /* an rk07 is using this uba! */
+#define        UAMSIZ  25
+       struct  map *uh_map;            /* buffered data path regs free */
+};
+
+#ifndef LOCORE
+/*
+ * Per-controller structure.
+ * (E.g. one for each disk and tape controller, and other things
+ * which use and release buffered data paths.)
+ *
+ * If a controller has devices attached, then there are
+ * cross-referenced uba_drive structures.
+ * This structure is the one which is queued in unibus resource wait,
+ * and saves the information about unibus resources which are used.
+ * The queue of devices waiting to transfer is also attached here.
+ */
+struct uba_ctlr {
+       struct  uba_driver *um_driver;
+       short   um_ctlr;        /* controller index in driver */
+       short   um_ubanum;      /* the uba it is on */
+       short   um_alive;       /* controller exists */
+       int     (**um_intr)();  /* interrupt handler(s) */
+       caddr_t um_addr;        /* address of device in i/o space */
+       struct  uba_hd *um_hd;
+/* the driver saves the prototype command here for use in its go routine */
+       int     um_cmd;         /* communication to dgo() */
+       int     um_ubinfo;      /* save unibus registers, etc */
+       struct  buf um_tab;     /* queue of devices for this controller */
+};

 
 

-#if VAX==780
-#define        PHYSUBA0        0x20006000
-#define        PHYSUMEM        0x2013e000
-#else
-#define        PHYSUBA0        0xf30000
-#define        PHYSUMEM        (0xfc0000+UNIBASE)
+/*
+ * Per ``device'' structure.
+ * (A controller has devices or uses and releases buffered data paths).
+ * (Everything else is a ``device''.)
+ *
+ * If a controller has many drives attached, then there will
+ * be several uba_device structures associated with a single uba_ctlr
+ * structure.
+ *
+ * This structure contains all the information necessary to run
+ * a unibus device such as a dz or a dh.  It also contains information
+ * for slaves of unibus controllers as to which device on the slave
+ * this is.  A flags field here can also be given in the system specification
+ * and is used to tell which dz lines are hard wired or other device
+ * specific parameters.
+ */
+struct uba_device {
+       struct  uba_driver *ui_driver;
+       short   ui_unit;        /* unit number on the system */
+       short   ui_ctlr;        /* mass ctlr number; -1 if none */
+       short   ui_ubanum;      /* the uba it is on */
+       short   ui_slave;       /* slave on controller */
+       int     (**ui_intr)();  /* interrupt handler(s) */
+       caddr_t ui_addr;        /* address of device in i/o space */
+       short   ui_dk;          /* if init 1 set to number for iostat */
+       int     ui_flags;       /* parameter from system specification */
+       short   ui_alive;       /* device exists */
+       short   ui_type;        /* driver specific type information */
+       caddr_t ui_physaddr;    /* phys addr, for standalone (dump) code */
+/* this is the forward link in a list of devices on a controller */
+       struct  uba_device *ui_forw;
+/* if the device is connected to a controller, this is the controller */
+       struct  uba_ctlr *ui_mi;
+       struct  uba_hd *ui_hd;
+};

 #endif
 
 #endif
 

-#if VAX==780
-/* UBA Configuration Register, CNFGR */
-#define        PARFLT          0x80000000      /* SBI Parity Fault */
-#define        WSQFLT          0x40000000      /* SBI Write Sequence Fault */
-#define        URDFLT          0x20000000      /* SBI Unexpected Read Fault */
-#define        ISQFLT          0x10000000      /* SBI Interlock Sequence Fault */
-#define        MXTFLT          0x8000000       /* SBI Multiple Transmitter Fault */
-#define        XMTFLT          0x4000000       /* UBA is transmit faulter */
-#define        ADPDN           0x800000        /* Adapter Power Down */
-#define        ADPUP           0x400000        /* Adapter Power Up */
-#define        UBINIT          0x40000         /* UNIBUS INIT is asserted */
-#define        UBPDN           0x20000         /* UNIBUS Power Down */
-#define        UBIC            0x10000         /* UNIBUS Initialization */
-                                       /* UNIBUS Ready */
-#define        UBACOD          0xff            /* UBA Code bits */
- 
-/* UBA Control Register, UBACR */
- 
-#define        MRD16           0x40000000      /* Map Reg Disable Bit 4 */
-#define        MRD8            0x20000000      /* Map Reg Disable Bit 3 */
-#define        MRD4            0x10000000      /* Map Reg Disable Bit 2 */
-#define        MRD2            0x8000000       /* Map Reg Disable Bit 1 */
-#define        MRD1            0x4000000       /* Map Reg Disable Bit 0 */
-#define        IFS             0x40            /* Interrupt Field Switch */
-#define        BRIE            0x20            /* BR Interrupt Enable */
-#define        USEFIE          0x10            /* UNIBUS to SBI Error Field IE */
-#define        SUEFIE          0x8             /* SBI to UNIBUS Error Field IE */
-#define        CNFIE           0x4             /* Configuration IE */
-#define        UPF             0x2             /* UNIBUS Power Fail */
-#define        ADINIT          0x1             /* Adapter Init */
- 
-/* UBA Status Register, UASR */
-#define        BR7FULL         0x8000000       /* BR7 Receive Vector Rg Full */
-#define        BR6FULL         0x4000000       /* BR6 Receive Vector Reg Full */
-#define        BR5FULL         0x2000000       /* BR5 Receive Vector Reg Full */
-#define        BR4FULL         0x1000000       /* BR4 Receive Vector Reg Full */
-#define        RDTO            0x400           /* UNIBUS to SBI Read Data Timeout */
-#define        RDS             0x200           /* Read Data Substitute */
-#define        CRD             0x100           /* Corrected Read Data */
-#define        CXTER           0x80            /* Command Transmit Error */
-#define        CXTMO           0x40            /* Command Transmit Timeout */
-#define        DPPE            0x20            /* Data Path Parity Error */
-#define        IVMR            0x10            /* Invalid Map Register */
-#define        MRPF            0x8             /* Map Register Parity Failure */
-#define        LEB             0x4             /* Lost Error */
-#define        UBSTO           0x2             /* UNIBUS Select Timeout */
-#define        UBSSTO          0x1             /* UNIBUS Slave Sync Timeout */
- 
-/* Failed Map Entry Register, FMER */
- 
-#define        FMRN            0x1ff           /* Failed Map Reg. No. Field */
- 
-/* Failed UNIBUS Address Register, FUBAR */
-#define        FUA             0xffff          /* Failed UNIBUS Address Field */
- 
-/* BR Receive Vector register, BRRVR */
-#define        AIRI            0x80000000      /* Adapter Interrupt Request */
-#define        DIV             0xffff          /* Device Interrupt Vector Field */
+/*
+ * Per-driver structure.
+ *
+ * Each unibus driver defines entries for a set of routines
+ * as well as an array of types which are acceptable to it.
+ * These are used at boot time by the configuration program.
+ */
+struct uba_driver {
+       int     (*ud_probe)();          /* see if a driver is really there */
+       int     (*ud_slave)();          /* see if a slave is there */
+       int     (*ud_attach)();         /* setup driver for a slave */
+       int     (*ud_dgo)();            /* fill csr/ba to start transfer */
+       u_short *ud_addr;               /* device csr addresses */
+       char    *ud_dname;              /* name of a device */
+       struct  uba_device **ud_dinfo;  /* backpointers to ubdinit structs */
+       char    *ud_mname;              /* name of a controller */
+       struct  uba_ctlr **ud_minfo;    /* backpointers to ubminit structs */
+       short   ud_xclu;                /* want exclusive use of bdp's */
+};

 #endif
 #endif

- 
-/* Data Path Register, DPR */
-#define        BNE             0x80000000      /* Buffer Not Empty - Purge */
-#define        BTE             0x40000000      /* Buffer Transfer Error */
-#define        DPF             0x20000000      /* DP Function (RO) */
-#define        BS              0x7f0000        /* Buffer State Field */
-#define        BUBA            0xffff          /* Buffered UNIBUS Address */
- 
-/* Map Register, MR */
-#define        MRV             0x80000000      /* Map Register Valid */
-#define        BO              0x2000000       /* Byte Offset Bit */
-#define        DPDB            0x1e00000       /* Data Path Designator Field */
-#define        SBIPFN          0xfffff         /* SBI Page Address Field */

 
 /*
 
 /*

- * Unibus maps
+ * Flags to UBA map/bdp allocation routines

  */
  */

-#ifdef KERNEL
-#define        UAMSIZ 50
+#define        UBA_NEEDBDP     0x01            /* transfer needs a bdp */
+#define        UBA_CANTWAIT    0x02            /* don't block me */
+#define        UBA_NEED16      0x04            /* need 16 bit addresses only */
+#define        UBA_HAVEBDP     0x08            /* use bdp specified in high bits */

 
 

-struct map ubamap[UAMSIZ];
-char   bdpwant;                /* someone is waiting for buffered data path */ 
-#if VAX==780
-#define        NUBABDP 15
-#else
-#define        NUBABDP 3
-#endif
+/*
+ * Macros to bust return word from map allocation routines.
+ */
+#define        UBAI_BDP(i)     ((int)(((unsigned)(i))>>28))
+#define        UBAI_NMR(i)     ((int)((i)>>18)&0x3ff)
+#define        UBAI_MR(i)      ((int)((i)>>9)&0x1ff)
+#define        UBAI_BOFF(i)    ((int)((i)&0x1ff))

 
 

-struct map bdpmap[NUBABDP];
-char   umrwant;                /* ... for unibus map registers */
-#endif
+#ifndef LOCORE
+#ifdef KERNEL
+/*
+ * UBA related kernel variables
+ */
+int    numuba;                                 /* number of uba's */
+struct uba_hd uba_hd[];

 
 /*
 
 /*

- * UBA registers
+ * Ubminit and ubdinit initialize the mass storage controller and
+ * device tables specifying possible devices.

  */
  */

+extern struct  uba_ctlr ubminit[];
+extern struct  uba_device ubdinit[];

 
 

-struct uba_regs
-{
-       int     uba_cnfgr;
-       int     uba_cr;
-       int     uba_sr;
-       int     uba_dcr;
-       int     uba_fmer;
-       int     uba_fubar;
-       int     pad1[2];
-       int     uba_brsvr[4];
-       int     uba_brrvr[4];
-       int     uba_dpr[16];
-       int     pad2[480];
-       struct  pte uba_map[496];
-};
+/*
+ * UNIbus device address space is mapped by UMEMmap
+ * into virtual address umem[][].
+ */
+extern struct pte UMEMmap[][512];      /* uba device addr pte's */
+extern char umem[][512*NBPG];          /* uba device addr space */

 
 

-union  ub_info {
-       struct ub_Info {
-       unsigned int    Ub_off:18,
-                       Ub_npf:10,
-                       Ub_bdp:4;
-       } ub_I;
-       int     ub_word;
-};
+/*
+ * Since some VAXen vector their first (and only) unibus interrupt
+ * vector just adjacent to the system control block, we must
+ * allocate space there when running on ``any'' cpu.  This space is
+ * used for the vector for uba0 on all cpu's.
+ */
+extern int (*UNIvec[])();                      /* unibus vec for uba0 */

 
 

-#define        ub_off  ub_I.Ub_off
-#define        ub_npf  ub_I.Ub_npf
-#define        ub_bdp  ub_I.Ub_bdp
+#if VAX780
+/*
+ * On 780's, we must set the scb vectors for the nexus of the
+ * UNIbus adaptors to vector to locore unibus adaptor interrupt dispatchers
+ * which make 780's look like the other VAXen.
+ */
+extern Xua0int(), Xua1int(), Xua2int(), Xua3int();
+#endif VAX780
+#endif KERNEL
+#endif !LOCORE