+apxctr(apx)
+ register struct apx_softc *apx;
+{
+ APX_WCSR(apx, axr_ccr, 0xB0); /* select ctr 2, write lsb+msb, mode 0 */
+ APX_WCSR(apx, axr_cnt2, 0x1);
+ APX_WCSR(apx, axr_cnt2, 0x0);
+ DELAY(50);
+ APX_WCSR(apx, axr_ccr, 0xE8); /* latch status, ctr 2; */
+ return (APX_RCSR(apx, axr_cnt2));
+}
+
+void
+apxtest(apx)
+ register struct apx_softc *apx;
+{
+ int i = 0;
+
+ if ((apx->apx_if.if_unit & 1) == 0 && (i = apxctr(apx)) == 0)
+ apxerror(apx, "no response from timer chip", 0);
+ if (SG_RCSR(apx, 1) & 0x8000)
+ SG_WCSR(apx, 1, 0x8040);
+ SG_WCSR(apx, 4, apx->apx_csr4);
+ SG_WCSR(apx, 5, 0x08); /* Set DTR mode in SGS thompson chip */
+ if (((i = SG_RCSR(apx, 5)) & 0xff08) != 0x08)
+ apxerror(apx, "no mk5025, csr5 high bits are", i);
+ else
+ apx->apx_flags |= APXF_CHIPHERE;
+ (void) apx_uprim(apx, SG_STOP, "stop after probing");
+}
+