fix to silo and bk bug

[unix-history] / usr / src / sys / vax / uba / ubareg.h

diff --git a/usr/src/sys/vax/uba/ubareg.h b/usr/src/sys/vax/uba/ubareg.h
index bd363b0..ab28c7b 100644 (file)
--- a/usr/src/sys/vax/uba/ubareg.h
+++ b/usr/src/sys/vax/uba/ubareg.h
@@ -1,113 +1,132 @@
-/*     ubareg.h        3.2     %H%     */
+/*     ubareg.h        4.22    81/04/03        */

 
 /*
 
 /*

- * Unibus adapter
+ * VAX UNIBUS adapter registers

  */
  */

+#ifndef LOCORE
+/*
+ * UBA hardware registers
+ */
+struct uba_regs
+{
+       int     uba_cnfgr;              /* configuration register */
+       int     uba_cr;                 /* control register */
+       int     uba_sr;                 /* status register */
+       int     uba_dcr;                /* diagnostic control register */
+       int     uba_fmer;               /* failed map entry register */
+       int     uba_fubar;              /* failed UNIBUS address register */
+       int     pad1[2];
+       int     uba_brsvr[4];
+       int     uba_brrvr[4];           /* receive vector registers */
+       int     uba_dpr[16];            /* buffered data path register */
+       int     pad2[480];
+       struct  pte uba_map[496];       /* unibus map register */
+       int     pad3[16];               /* no maps for device address space */
+};
+#endif

 
 

-#define        UBA0            0x80060000      /* sys virt i/o for UBA 0 */
-#define        UBA0_DEV (UBA0+0x2000-0160000)  /* sys virt of device regs */
+#if VAX780
+/* uba_cnfgr */
+#define        UBACNFGR_UBINIT 0x00040000      /* unibus init asserted */
+#define        UBACNFGR_UBPDN  0x00020000      /* unibus power down */
+#define        UBACNFGR_UBIC   0x00010000      /* unibus init complete */

 
 

-#define        UNIBASE 0760000                 /* UNIBUS phys base of i/o reg's */
+/* uba_cr */
+#define        UBACR_MRD16     0x40000000      /* map reg disable bit 4 */
+#define        UBACR_MRD8      0x20000000      /* map reg disable bit 3 */
+#define        UBACR_MRD4      0x10000000      /* map reg disable bit 2 */
+#define        UBACR_MRD2      0x08000000      /* map reg disable bit 1 */
+#define        UBACR_MRD1      0x04000000      /* map reg disable bit 0 */
+#define        UBACR_IFS       0x00000040      /* interrupt field switch */
+#define        UBACR_BRIE      0x00000020      /* BR interrupt enable */
+#define        UBACR_USEFIE    0x00000010      /* UNIBUS to SBI error field IE */
+#define        UBACR_SUEFIE    0x00000008      /* SBI to UNIBUS error field IE */
+#define        UBACR_CNFIE     0x00000004      /* configuration IE */
+#define        UBACR_UPF       0x00000002      /* UNIBUS power fail */
+#define        UBACR_ADINIT    0x00000001      /* adapter init */

 
 

-/* UBA Configuration Register, CNFGR */
-#define        PARFLT          0x80000000      /* SBI Parity Fault */
-#define        WSQFLT          0x40000000      /* SBI Write Sequence Fault */
-#define        URDFLT          0x20000000      /* SBI Unexpected Read Fault */
-#define        ISQFLT          0x10000000      /* SBI Interlock Sequence Fault */
-#define        MXTFLT          0x8000000       /* SBI Multiple Transmitter Fault */
-#define        XMTFLT          0x4000000       /* UBA is transmit faulter */
-#define        ADPDN           0x800000        /* Adapter Power Down */
-#define        ADPUP           0x400000        /* Adapter Power Up */
-#define        UBINIT          0x40000         /* UNIBUS INIT is asserted */
-#define        UBPDN           0x20000         /* UNIBUS Power Down */
-#define        UBIC            0x10000         /* UNIBUS Initialization */
-                                       /* UNIBUS Ready */
-#define        UBACOD          0xff            /* UBA Code bits */
- 
-/* UBA Control Register, UBACR */
- 
-#define        MRD16           0x40000000      /* Map Reg Disable Bit 4 */
-#define        MRD8            0x20000000      /* Map Reg Disable Bit 3 */
-#define        MRD4            0x10000000      /* Map Reg Disable Bit 2 */
-#define        MRD2            0x8000000       /* Map Reg Disable Bit 1 */
-#define        MRD1            0x4000000       /* Map Reg Disable Bit 0 */
-#define        IFS             0x40            /* Interrupt Field Switch */
-#define        BRIE            0x20            /* BR Interrupt Enable */
-#define        USEFIE          0x10            /* UNIBUS to SBI Error Field IE */
-#define        SUEFIE          0x8             /* SBI to UNIBUS Error Field IE */
-#define        CNFIE           0x4             /* Configuration IE */
-#define        UPF             0x2             /* UNIBUS Power Fail */
-#define        ADINIT          0x1             /* Adapter Init */
- 
-/* UBA Status Register, UASR */
-#define        BR7FULL         0x8000000       /* BR7 Receive Vector Rg Full */
-#define        BR6FULL         0x4000000       /* BR6 Receive Vector Reg Full */
-#define        BR5FULL         0x2000000       /* BR5 Receive Vector Reg Full */
-#define        BR4FULL         0x1000000       /* BR4 Receive Vector Reg Full */
-#define        RDTO            0x400           /* UNIBUS to SBI Read Data Timeout */
-#define        RDS             0x200           /* Read Data Substitute */
-#define        CRD             0x100           /* Corrected Read Data */
-#define        CXTER           0x80            /* Command Transmit Error */
-#define        CXTMO           0x40            /* Command Transmit Timeout */
-#define        DPPE            0x20            /* Data Path Parity Error */
-#define        IVMR            0x10            /* Invalid Map Register */
-#define        MRPF            0x8             /* Map Register Parity Failure */
-#define        LEB             0x4             /* Lost Error */
-#define        UBSTO           0x2             /* UNIBUS Select Timeout */
-#define        UBSSTO          0x1             /* UNIBUS Slave Sync Timeout */
- 
-/* Failed Map Entry Register, FMER */
- 
-#define        FMRN            0x1ff           /* Failed Map Reg. No. Field */
- 
-/* Failed UNIBUS Address Register, FUBAR */
-#define        FUA             0xffff          /* Failed UNIBUS Address Field */
- 
-/* BR Receive Vector register, BRRVR */
-#define        AIRI            0x80000000      /* Adapter Interrupt Request */
-#define        DIV             0xffff          /* Device Interrupt Vector Field */
+/* uba_sr */
+#define        UBASR_BR7FULL   0x08000000      /* BR7 receive vector reg full */
+#define        UBASR_BR6FULL   0x04000000      /* BR6 receive vector reg full */
+#define        UBASR_BR5FULL   0x02000000      /* BR5 receive vector reg full */
+#define        UBASR_BR4FULL   0x01000000      /* BR4 receive vector reg full */
+#define        UBASR_RDTO      0x00000400      /* UNIBUS to SBI read data timeout */
+#define        UBASR_RDS       0x00000200      /* read data substitute */
+#define        UBASR_CRD       0x00000100      /* corrected read data */
+#define        UBASR_CXTER     0x00000080      /* command transmit error */
+#define        UBASR_CXTMO     0x00000040      /* command transmit timeout */
+#define        UBASR_DPPE      0x00000020      /* data path parity error */
+#define        UBASR_IVMR      0x00000010      /* invalid map register */
+#define        UBASR_MRPF      0x00000008      /* map register parity failure */
+#define        UBASR_LEB       0x00000004      /* lost error */
+#define        UBASR_UBSTO     0x00000002      /* UNIBUS select timeout */
+#define        UBASR_UBSSYNTO  0x00000001      /* UNIBUS slave sync timeout */
+
+#define        UBASR_BITS \
+"\20\13RDTO\12RDS\11CRD\10CXTER\7CXTMO\6DPPE\5IVMR\4MRPF\3LEB\2UBSTO\1UBSSYNTO"
+
+/* uba_brrvr[] */
+#define        UBABRRVR_AIRI   0x80000000      /* adapter interrupt request */
+#define        UBABRRVR_DIV    0x0000ffff      /* device interrupt vector field */
+#endif VAX780

  
  

-/* Data Path Register, DPR */
-#define        BNE             0x80000000      /* Buffer Not Empty - Purge */
-#define        BTE             0x40000000      /* Buffer Transfer Error */
-#define        DPF             0x20000000      /* DP Function (RO) */
-#define        BS              0x7f0000        /* Buffer State Field */
-#define        BUBA            0xffff          /* Buffered UNIBUS Address */
+/* uba_dpr */
+#if VAX780
+#define        UBADPR_BNE      0x80000000      /* buffer not empty - purge */
+#define        UBADPR_BTE      0x40000000      /* buffer transfer error */
+#define        UBADPR_DPF      0x20000000      /* DP function (RO) */
+#define        UBADPR_BS       0x007f0000      /* buffer state field */
+#define        UBADPR_BUBA     0x0000ffff      /* buffered UNIBUS address */
+#endif VAX780
+#if VAX750
+#define        UBADPR_ERROR    0x80000000      /* error occurred */
+#define        UBADPR_NXM      0x40000000      /* nxm from memory */
+#define        UBADPR_UCE      0x20000000      /* uncorrectable error */
+#define        UBADPR_PURGE    0x00000001      /* purge bdp */
+#endif VAX750

  
  

-/* Map Register, MR */
-#define        MRV             0x80000000      /* Map Register Valid */
-#define        BO              0x2000000               /* Byte Offset Bit */
-#define        DPDB            0x1e00000               /* Data Path Designator Field */
-#define        SBIPFN          0xfffff                 /* SBI Page Address Field */
+/* uba_mr[] */
+#define        UBAMR_MRV       0x80000000      /* map register valid */
+#define        UBAMR_BO        0x02000000      /* byte offset bit */
+#define        UBAMR_DPDB      0x01e00000      /* data path designator field */
+#define        UBAMR_SBIPFN    0x000fffff      /* SBI page address field */
+
+#define        UBAMR_DPSHIFT   21              /* shift to data path designator */
+
+/*
+ * Number of UNIBUS map registers.  We can't use the last 8k of UNIBUS
+ * address space for i/o transfers since it is used by the devices,
+ * hence have slightly less than 256K of UNIBUS address space.
+ */
+#define        NUBMREG 496

 
 /*
 
 /*

- * Unibus maps
+ * Number of unibus buffered data paths and possible uba's per cpu type.

  */
  */

-#ifdef KERNEL
-#define        UAMSIZ 50
+#define        NBDP780 15
+#define        NBDP750 3
+#define        NBDP7ZZ 0
+#define        MAXNBDP 15

 
 

-struct map ubamap[UAMSIZ];
-char   bdpwant;                /* someone is waiting for buffered data path */ 
-struct map bdpmap[15];
-char   umrwant;                /* ... for unibus map registers */
+#define        NUBA780 4
+#define        NUBA750 1
+#define        NUBA7ZZ 1
+#if VAX780
+#define        MAXNUBA 4
+#else
+#define        MAXNUBA 1

 #endif
 
 /*
 #endif
 
 /*

- * UBA registers
+ * Formulas for locations of the last 8k of UNIBUS memory
+ * for each possible uba.

  */
  */

-
-struct uba_regs
-{
-       int     uba_cnfgr;
-       int     uba_cr;
-       int     uba_sr;
-       int     uba_dcr;
-       int     uba_fmer;
-       int     uba_fubar;
-       int     pad1[2];
-       int     uba_brsvr[4];
-       int     uba_brrvr[4];
-       int     uba_dpr[16];
-       int     pad2[480];
-       struct  pte uba_map[496];
-};
+#if VAX7ZZ
+#define        UMEM7ZZ         ((u_short *)(0xffe000))
+#endif
+#if VAX750
+#define        UMEM750(i)      ((u_short *)(0xffe000-(i)*0x40000))
+#endif
+#if VAX780
+#define        UMEM780(i)      ((u_short *)(0x2013e000+(i)*0x40000))
+#endif