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1 | /* |
2 | * Copyright 2010-2017 Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License, version 2, | |
6 | * as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | * | |
13 | * Disclaimer: The codes contained in these modules may be specific to | |
14 | * the Intel Software Development Platform codenamed Knights Ferry, | |
15 | * and the Intel product codenamed Knights Corner, and are not backward | |
16 | * compatible with other Intel products. Additionally, Intel will NOT | |
17 | * support the codes or instruction set in future products. | |
18 | * | |
19 | * Intel offers no warranty of any kind regarding the code. This code is | |
20 | * licensed on an "AS IS" basis and Intel is not obligated to provide | |
21 | * any support, assistance, installation, training, or other services | |
22 | * of any kind. Intel is also not obligated to provide any updates, | |
23 | * enhancements or extensions. Intel specifically disclaims any warranty | |
24 | * of merchantability, non-infringement, fitness for any particular | |
25 | * purpose, and any other warranty. | |
26 | * | |
27 | * Further, Intel disclaims all liability of any kind, including but | |
28 | * not limited to liability for infringement of any proprietary rights, | |
29 | * relating to the use of the code, even if Intel is notified of the | |
30 | * possibility of such liability. Except as expressly stated in an Intel | |
31 | * license agreement provided with this code and agreed upon with Intel, | |
32 | * no license, express or implied, by estoppel or otherwise, to any | |
33 | * intellectual property rights is granted herein. | |
34 | */ | |
35 | ||
36 | /* "Raw" register offsets & bit specifications for MIC */ | |
37 | #ifndef _MIC_MICBASEDEFINE_REGISTERS_H_ | |
38 | #define _MIC_MICBASEDEFINE_REGISTERS_H_ | |
39 | ||
40 | #define COMMON_MMIO_BOX_SIZE (1<<16) | |
41 | ||
42 | /* CBOX register base defines */ | |
43 | #define CBOX_BASE 0x0000000000ULL | |
44 | ||
45 | /* TXS register base defines */ | |
46 | #define TXS0_BASE 0x0800780000ULL | |
47 | #define TXS1_BASE 0x0800770000ULL | |
48 | #define TXS2_BASE 0x0800760000ULL | |
49 | #define TXS3_BASE 0x0800750000ULL | |
50 | #define TXS4_BASE 0x0800740000ULL | |
51 | #define TXS5_BASE 0x0800730000ULL | |
52 | #define TXS6_BASE 0x0800720000ULL | |
53 | #define TXS7_BASE 0x0800710000ULL | |
54 | #define TXS8_BASE 0x08006E0000ULL | |
55 | ||
56 | /* GBOX register base defines */ | |
57 | #define GBOX0_BASE 0x08007A0000ULL | |
58 | #define GBOX1_BASE 0x0800790000ULL | |
59 | #define GBOX2_BASE 0x0800700000ULL | |
60 | #define GBOX3_BASE 0x08006F0000ULL | |
61 | ||
62 | #define GBOX_CHANNEL0_BASE 0x00000000 | |
63 | #define GBOX_CHANNEL1_BASE 0x00000800 | |
64 | #define GBOX_CHANNEL2_BASE 0x00001000 | |
65 | ||
66 | /* VBOX register base defines */ | |
67 | #define VBOX_BASE 0x08007B0000ULL | |
68 | ||
69 | /* DBOX register base defines */ | |
70 | #define DBOX_BASE 0x08007C0000ULL | |
71 | ||
72 | /* SBOX register base defines */ | |
73 | #define SBOX_BASE 0x08007D0000ULL | |
74 | ||
75 | #define MIC_GTT_BASE 0x0800800000ULL | |
76 | #define MIC_GTT_TOP 0x080083FFFFULL | |
77 | #define MIC_GTT_SIZE (MIC_GTT_TOP - MIC_GTT_BASE + 1) | |
78 | ||
79 | /* Aperture defines */ | |
80 | #define MIC_APERTURE_BASE 0x0900000000ULL | |
81 | #define MIC_APERTURE_TOP 0x090FFFFFFFULL | |
82 | #define MIC_APERTURE_SIZE (MIC_APERTURE_TOP - MIC_APERTURE_BASE + 1) | |
83 | ||
84 | /* SPI flash defines */ | |
85 | #define MIC_SPI_BOOTLOADER_BASE 0x0FFFFF0000ULL | |
86 | #define MIC_SPI_BOOTLOADER_TOP 0x0FFFFFFFFFULL | |
87 | #define MIC_SPI_BOOTLOADER_SIZE (MIC_SPI_BOOTLOADER_TOP - MIC_SPI_BOOTLOADER_BASE + 1) | |
88 | #define MIC_SPI_2ND_STAGE_BASE 0x0FFFFE0000ULL | |
89 | #define MIC_SPI_2ND_STAGE_TOP 0x0FFFFEFFFFULL | |
90 | #define MIC_SPI_2ND_STAGE_SIZE (MIC_SPI_2ND_STAGE_TOP - MIC_SPI_2ND_STAGE_BASE + 1) | |
91 | #define MIC_SPI_PARAMETER_BASE 0x0FFFFDC000ULL | |
92 | #define MIC_SPI_PARAMETER_TOP 0x0FFFFDFFFFULL | |
93 | #define MIC_SPI_PARAMETER_SIZE (MIC_SPI_PARAMETER_TOP - MIC_SPI_PARAMETER_BASE + 1) | |
94 | ||
95 | /* remote defines */ | |
96 | #define MIC_REMOTE_BASE 0x1000000000ULL | |
97 | #define MIC_REMOTE_TOP 0x7FFFFFFFFFULL | |
98 | #define MIC_REMOTE_SIZE (MIC_REMOTE_TOP - MIC_REMOTE_BASE + 1) | |
99 | ||
100 | /* system defines */ | |
101 | #define MIC_SYSTEM_BASE 0x8000000000ULL | |
102 | #define MIC_SYSTEM_TOP 0xFFFFFFFFFFULL | |
103 | #define MIC_SYSTEM_PAGE_SIZE 0x0400000000ULL | |
104 | #define MIC_SYSTEM_SIZE (MIC_SYSTEM_TOP - MIC_SYSTEM_BASE + 1) | |
105 | ||
106 | #define MIC_PHYSICAL_ADDRESS_BITS 40 | |
107 | #define MIC_PHYSICAL_ADDRESS_SPACE_SIZE ( 1ULL << MIC_PHYSICAL_ADDRESS_BITS ) | |
108 | ||
109 | #define MIC_HOST_MMIO_BASE DBOX_BASE | |
110 | ||
111 | #endif |