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1 | /* |
2 | * Copyright 2010-2017 Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License, version 2, | |
6 | * as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | * | |
13 | * Disclaimer: The codes contained in these modules may be specific to | |
14 | * the Intel Software Development Platform codenamed Knights Ferry, | |
15 | * and the Intel product codenamed Knights Corner, and are not backward | |
16 | * compatible with other Intel products. Additionally, Intel will NOT | |
17 | * support the codes or instruction set in future products. | |
18 | * | |
19 | * Intel offers no warranty of any kind regarding the code. This code is | |
20 | * licensed on an "AS IS" basis and Intel is not obligated to provide | |
21 | * any support, assistance, installation, training, or other services | |
22 | * of any kind. Intel is also not obligated to provide any updates, | |
23 | * enhancements or extensions. Intel specifically disclaims any warranty | |
24 | * of merchantability, non-infringement, fitness for any particular | |
25 | * purpose, and any other warranty. | |
26 | * | |
27 | * Further, Intel disclaims all liability of any kind, including but | |
28 | * not limited to liability for infringement of any proprietary rights, | |
29 | * relating to the use of the code, even if Intel is notified of the | |
30 | * possibility of such liability. Except as expressly stated in an Intel | |
31 | * license agreement provided with this code and agreed upon with Intel, | |
32 | * no license, express or implied, by estoppel or otherwise, to any | |
33 | * intellectual property rights is granted herein. | |
34 | */ | |
35 | ||
36 | /* common power management specific header defines for host and card */ | |
37 | ||
38 | #include "io_interface.h" | |
39 | ||
40 | #if !defined(__MIC_PM_H) | |
41 | #define __MIC_PM_H | |
42 | ||
43 | #define PC6_TIMER 10 | |
44 | ||
45 | #define IOCTL_PM_SendIoctl _IOC(_IOC_READ|_IOC_WRITE, 'l', 2, 0) | |
46 | ||
47 | #define MAX_HW_IDLE_WAIT_COUNT 100 | |
48 | #define PC3_EXIT_WAIT_COUNT 1000 | |
49 | #define PM_SEND_MODE SCIF_SEND_BLOCK | |
50 | #define PM_RECV_MODE SCIF_RECV_BLOCK | |
51 | #define SET_VID_RETRY_COUNT 3 | |
52 | ||
53 | #define PM_NODE_MAGIC_BIT 31 | |
54 | #define PM_NODE_IDLE (1 << PM_NODE_MAGIC_BIT) | |
55 | ||
56 | #define PM_PRINT(fmt, ...) printk("[ %s : %d ]:"fmt, \ | |
57 | __func__, __LINE__, ##__VA_ARGS__) | |
58 | ||
59 | #define PM_DEBUG(fmt, ...) pr_debug("[ %s : %d ]:"fmt, \ | |
60 | __func__, __LINE__, ##__VA_ARGS__) | |
61 | ||
62 | #define PM_ENTRY PM_DEBUG("==> %s\n", __func__) | |
63 | #define PM_EXIT PM_DEBUG("<== %s\n", __func__) | |
64 | #define PM_MAJOR_VERSION 1 | |
65 | #define PM_MINOR_VERSION 0 | |
66 | ||
67 | ||
68 | typedef enum _PM_MESSAGE { | |
69 | PM_MESSAGE_PC3READY, | |
70 | PM_MESSAGE_OPEN, | |
71 | PM_MESSAGE_OPEN_ACK, | |
72 | PM_MESSAGE_CLOSE, | |
73 | PM_MESSAGE_CLOSE_ACK, | |
74 | PM_MESSAGE_TEST, | |
75 | PM_MESSAGE_MAX, | |
76 | } PM_MESSAGE; | |
77 | ||
78 | typedef enum _PM_IDLE_STATE { | |
79 | PM_IDLE_STATE_PC0, | |
80 | PM_IDLE_STATE_PC3_READY, | |
81 | PM_IDLE_STATE_PC3, | |
82 | PM_IDLE_STATE_PC6, | |
83 | PM_IDLE_STATE_LOST, | |
84 | PM_IDLE_STATE_MAX, | |
85 | } PM_IDLE_STATE; | |
86 | ||
87 | #ifndef _MIC_SCIF_ | |
88 | typedef enum { | |
89 | IOCTL_pm_send, | |
90 | IOCTL_pm_recv, | |
91 | IOCTL_pm_send_check, | |
92 | IOCTL_pm_get_idle_state, | |
93 | IOCTL_pm_exit_idle_state, | |
94 | // For emulator testing | |
95 | IOCTL_pmemu_pc3_entry, | |
96 | IOCTL_pmemu_pc3_exit, | |
97 | IOCTL_pmemu_pc6_entry, | |
98 | IOCTL_pmemu_pc6_exit, | |
99 | IOCTL_pmemu_dpc3_entry, | |
100 | IOCTL_pmemu_dpc3_exit, | |
101 | IOCTL_get_dependency_graph, | |
102 | IOCTL_get_dependency_set, | |
103 | IOCTL_pm_toggle_connection, | |
104 | IOCTL_pm_idlestate_exit, | |
105 | IOCTL_pm_enable_dpc3_testing, | |
106 | IOCTL_pm_device_restart, | |
107 | } PM_IOCTL_TYPE; | |
108 | ||
109 | struct pm_ioctl_header { | |
110 | uint32_t node; | |
111 | PM_IOCTL_TYPE opcode; | |
112 | uint64_t arglen; | |
113 | }; | |
114 | #define PM_TEST_MSG_BODY "PM Test Message" | |
115 | #endif | |
116 | ||
117 | //Generic PM Header. Has message type and length of message. | |
118 | typedef struct _pm_msg_header { | |
119 | PM_MESSAGE opcode; | |
120 | uint32_t len; | |
121 | } pm_msg_header; | |
122 | ||
123 | typedef struct _pm_msg_unit_test | |
124 | { | |
125 | pm_msg_header header; | |
126 | void * buf; | |
127 | } pm_msg_unit_test; | |
128 | ||
129 | typedef struct _pm_version | |
130 | { | |
131 | uint16_t major_version; | |
132 | uint16_t minor_version; | |
133 | ||
134 | } pm_version; | |
135 | ||
136 | typedef struct _pm_msg_pm_options | |
137 | { | |
138 | uint8_t pc3_enabled; | |
139 | uint8_t pc6_enabled; | |
140 | pm_version version; | |
141 | } pm_msg_pm_options; | |
142 | ||
143 | #ifndef _MIC_SCIF_ | |
144 | // PM IOCTLs | |
145 | struct pm_scif_send { | |
146 | struct pm_ioctl_header header; | |
147 | uint32_t length; | |
148 | void *buf; | |
149 | }; | |
150 | ||
151 | struct pm_scif_recv { | |
152 | struct pm_ioctl_header header; | |
153 | uint32_t length; | |
154 | void *buf; | |
155 | }; | |
156 | ||
157 | struct pm_scif_send_check { | |
158 | struct pm_ioctl_header header; | |
159 | uint32_t length; | |
160 | void *buf; | |
161 | }; | |
162 | ||
163 | typedef struct pm_get_idle_state { | |
164 | struct pm_ioctl_header header; | |
165 | PM_IDLE_STATE *idle_state; | |
166 | } pm_get_idle_state_t; | |
167 | ||
168 | typedef struct pm_exit_idle_state { | |
169 | struct pm_ioctl_header header; | |
170 | PM_IDLE_STATE idle_state; | |
171 | }pm_exit_idlestate_t; | |
172 | ||
173 | typedef struct dependency_graph { | |
174 | struct pm_ioctl_header header; | |
175 | uint32_t** depmtrx; | |
176 | } dependency_graph_t; | |
177 | ||
178 | struct io_dependency_set { | |
179 | struct pm_ioctl_header header; | |
180 | int is_active_set; | |
181 | uint64_t dep_set; | |
182 | }; | |
183 | ||
184 | struct io_enable_dpc3_test { | |
185 | struct pm_ioctl_header header; | |
186 | uint32_t enable_test; | |
187 | uint32_t state; | |
188 | }; | |
189 | ||
190 | typedef struct _pm_status { | |
191 | uint32_t hoststate_reg; | |
192 | uint32_t cardstate_reg; | |
193 | uint32_t c3waketimer_reg; | |
194 | uint32_t pcucontrol_reg; | |
195 | uint32_t uos_pcucontrol_reg; | |
196 | uint32_t corevolt_reg; | |
197 | uint32_t gpmctrl_reg; | |
198 | uint32_t idle_state; | |
199 | uint32_t board_id; | |
200 | } pm_status_t; | |
201 | ||
202 | typedef struct _test_msg_ctrl { | |
203 | uint32_t action; | |
204 | } test_msg_ctrl_t; | |
205 | ||
206 | typedef struct _connection_info { | |
207 | int32_t conn_state; | |
208 | int32_t local_port; | |
209 | int32_t local_node; | |
210 | int32_t remote_port; | |
211 | int32_t remote_node; | |
212 | int32_t num_messages_queued; | |
213 | } connection_info_t; | |
214 | ||
215 | #endif //_MIC_SCIF_ | |
216 | ||
217 | #if defined(CONFIG_MK1OM) | |
218 | ||
219 | #define SBOX_SVID_CONTROL 0x00004110 | |
220 | #define SBOX_PCU_CONTROL 0x00004114 | |
221 | #define SBOX_HOST_PMSTATE 0x00004118 | |
222 | #define SBOX_UOS_PMSTATE 0x0000411c | |
223 | #define SBOX_C3WAKEUP_TIMER 0x00004120 | |
224 | #define GBOX_PM_CTRL 0x0000413C | |
225 | #define SBOX_UOS_PCUCONTROL 0x0000412C | |
226 | ||
227 | #elif defined(CONFIG_ML1OM) || defined(WINDOWS) | |
228 | ||
229 | #define DBOX_SWFOX1 0x00002414 | |
230 | #define DBOX_SWFOX2 0x00002418 | |
231 | #define DBOX_SWFOX3 0x0000241C | |
232 | #define DBOX_SWFOX4 0x00002420 | |
233 | #define DBOX_SWFOX5 0x00002424 | |
234 | #define DBOX_SWFOX6 0x00002428 | |
235 | #define DBOX_SWFOX7 0x0000242C | |
236 | #define DBOX_SWF0X8 0x00002430 | |
237 | ||
238 | #define SBOX_SVID_CONTROL DBOX_SWFOX1 | |
239 | #define SBOX_PCU_CONTROL DBOX_SWFOX2 | |
240 | #define SBOX_HOST_PMSTATE DBOX_SWFOX3 | |
241 | #define SBOX_UOS_PMSTATE DBOX_SWFOX4 | |
242 | #define SBOX_C3WAKEUP_TIMER DBOX_SWFOX5 | |
243 | #define GBOX_PM_CTRL DBOX_SWFOX6 | |
244 | #define SBOX_UOS_PCUCONTROL DBOX_SWFOX7 | |
245 | ||
246 | #else | |
247 | #error Neither CONFIG_ML1OM nor CONFIG_MK1OM defined | |
248 | #endif | |
249 | ||
250 | #define SBOX_SVIDCTRL_SVID_DOUT(x) ((x) & 0x1ff) | |
251 | #define SBOX_SVIDCTRL_SVID_DOUT_BITS(x) ((x) & 0x1ff) | |
252 | #define SBOX_SVIDCTRL_SVID_CMD(x) (((x) >> 9) & 0x1ff) | |
253 | #define SBOX_SVIDCTRL_SVID_CMD_BITS(x) (((x) & 0x1ff) << 9) | |
254 | #define SBOX_SVIDCTRL_SVID_DIN(x) (((x) >> 18) & 0x3ff) | |
255 | #define SBOX_SVIDCTRL_SVID_ERROR(x) (((x) >> 29) & 0x1) | |
256 | #define SBOX_SVIDCTRL_SVID_IDLE(x) (((x) >> 30) & 0x1) | |
257 | #define SBOX_SVIDCTRL_CMD_START(x) (((x) >> 31) & 0x1) | |
258 | #define SBOX_SVIDCTRL_CMD_START_BITS(x) (((x) & 0x1) << 31) | |
259 | // This is not a register field, but we need to check these bits to determine parity error | |
260 | #define SBOX_SVIDCTRL_ACK1ACK0(x) (((x) >> 27) & 0x11) | |
261 | ||
262 | #define SBOX_PCUCTRL_ENABLE_MCLK_SHUTDWN(x) ((x) & 0x1) | |
263 | #define SBOX_PCUCTRL_ENABLE_MCLK_SHUTDWN_BITS(x) ((x) & 0x1) | |
264 | #define SBOX_PCUCTRL_RING_ACTIVE(x) (((x) >> 2) & 0x1) | |
265 | #define SBOX_PCUCTRL_RING_ACTIVE_BITS(x) (((x) & 0x1) << 2) | |
266 | #define SBOX_PCUCTRL_PREVENT_AUTOC3_EXIT(x) (((x) >> 3) & 0x1) | |
267 | #define SBOX_PCUCTRL_PREVENT_AUTOC3_EXIT_BITS(x) (((x) & 0x1) << 3) | |
268 | #define SBOX_PCUCTRL_PWRGOOD_MASK(x) (((x) >> 17) & 0x1) | |
269 | #define SBOX_PCUCTRL_PWRGOOD_MASK_BITS(x) (((x) & 0x1) << 17) | |
270 | #define SBOX_PCUCTRL_MCLK_PLL_LCK(x) (((x) >> 16) & 0x1) | |
271 | #define SBOX_THERMAL_STS_ALERT_LOG(x) (((x) >> 3) & 0x1) | |
272 | #define SBOX_THERMAL_STS_ALERT_LOG_BITS(x) (((x) & 0x1) << 3) | |
273 | ||
274 | // used by host to communicate card idle state to uos | |
275 | #define SBOX_HPMSTATE_STATUS(x) ((x) & 0xff) | |
276 | #define SBOX_HPMSTATE_STATUS_BITS(x) ((x) & 0xff) | |
277 | #define SBOX_HPMSTATE_MINVID(x) (((x) >> 8) & 0xff) | |
278 | #define SBOX_HPMSTATE_TDPVID(x) (((x) >> 16) & 0xff) | |
279 | // used by uos to communicate card idle state to host | |
280 | #define SBOX_UPMSTATE_STATUS(x) ((x) & 0xff) | |
281 | #define SBOX_UPMSTATE_STATUS_BITS(x) ((x) & 0xff) | |
282 | ||
283 | #define SBOX_C3WAKEUP_TIME(x) ((x) & 0xffff) | |
284 | #define SBOX_C3WAKEUP_TIME_BITS(x) ((x) & 0xffff) | |
285 | ||
286 | #define IN_PCKGC6_BITS(x) (((x) & 0x1) << 1) | |
287 | #define KNC_SVID_ADDR 0 | |
288 | #define KNC_SETVID_FAST 1 | |
289 | #define KNC_SETVID_SLOW 2 | |
290 | #define KNC_SETVID_ATTEMPTS 50 | |
291 | ||
292 | ||
293 | typedef union _sbox_pcu_ctrl { | |
294 | uint32_t value; | |
295 | struct { | |
296 | uint32_t enable_mclk_pl_shutdown :1; | |
297 | uint32_t mclk_enabled :1; | |
298 | uint32_t ring_active :1; | |
299 | uint32_t prevent_auto_c3_exit :1; | |
300 | uint32_t ghost_active :1; | |
301 | uint32_t tcu_active :1; | |
302 | uint32_t itp_scllk_gate_disable :1; | |
303 | uint32_t itp_pkg_c3_disable :1; | |
304 | uint32_t scratch :1; | |
305 | uint32_t unallocated_1 :1; | |
306 | uint32_t sysint_active :1; | |
307 | uint32_t sclk_grid_off_disable :1; | |
308 | uint32_t icc_dvo_ssc_cg_enable :1; | |
309 | uint32_t icc_core_ref_clk_cg_enable :1; | |
310 | uint32_t icc_gddr_ssc_cg_enable :1; | |
311 | uint32_t icc_pll_disable :1; | |
312 | uint32_t mclk_pll_lock :1; | |
313 | uint32_t grpB_pwrgood_mask :1; | |
314 | uint32_t unallocated_2 :14; | |
315 | } bits; | |
316 | ||
317 | } sbox_pcu_ctrl_t; | |
318 | ||
319 | typedef union _sbox_host_pm_state { | |
320 | uint32_t value; | |
321 | struct { | |
322 | uint32_t host_pm_state :7; | |
323 | uint32_t abort_not_processed :1; | |
324 | uint32_t min_vid :8; | |
325 | uint32_t tdp_vid :8; | |
326 | uint32_t unallocated :8; | |
327 | } bits; | |
328 | ||
329 | } sbox_host_pm_state_t; | |
330 | ||
331 | typedef union _sbox_uos_pm_state { | |
332 | uint32_t value; | |
333 | struct { | |
334 | uint32_t uos_pm_state :8; | |
335 | uint32_t unallocated :24; | |
336 | }bits; | |
337 | ||
338 | } sbox_uos_pm_state_t; | |
339 | ||
340 | typedef union _c3_wakeup_timer { | |
341 | uint32_t value; | |
342 | struct { | |
343 | uint32_t c3_wake_time :16; | |
344 | uint32_t unallocated_1 :1; | |
345 | uint32_t c3_wake_timeout :1; | |
346 | uint32_t unallocated_2 :14; | |
347 | } bits; | |
348 | ||
349 | } c3_wakeup_timer_t; | |
350 | ||
351 | typedef union _sbox_svid_control { | |
352 | uint32_t value; | |
353 | struct { | |
354 | uint32_t svid_dout :9; | |
355 | uint32_t svid_cmd :9; | |
356 | uint32_t svid_din :11; | |
357 | uint32_t svid_error :1; | |
358 | uint32_t svid_idle :1; | |
359 | uint32_t cmd_start :1; | |
360 | } bits; | |
361 | ||
362 | } sbox_svid_control; | |
363 | ||
364 | typedef union _gbox_pm_control { | |
365 | uint32_t value; | |
366 | struct { | |
367 | uint32_t c6_disable :1; | |
368 | uint32_t in_pckgc6 :1; | |
369 | uint32_t gbox_inM3 :2; | |
370 | uint32_t unallocated :28; | |
371 | } bits; | |
372 | ||
373 | } gbox_pm_control; | |
374 | ||
375 | typedef union _sbox_thermal_sts_interrupt { | |
376 | uint32_t value; | |
377 | struct { | |
378 | uint32_t mclk_ratio_status :1; | |
379 | uint32_t mclk_ratio_log :1; | |
380 | uint32_t alert_status :1; | |
381 | uint32_t alert_log :1; | |
382 | uint32_t gpu_hot_status :1; | |
383 | uint32_t gpu_hot_log :1; | |
384 | uint32_t pwr_alert_status :1; | |
385 | uint32_t pwr_alert_log :1; | |
386 | uint32_t pmu_status :1; | |
387 | uint32_t pmu_log :1; | |
388 | uint32_t etc_freeze :1; | |
389 | uint32_t unallocated :21; | |
390 | }bits; | |
391 | ||
392 | } sbox_thermal_sts_interrupt; | |
393 | ||
394 | typedef union _sboxUosPcucontrolReg | |
395 | { | |
396 | uint32_t value; | |
397 | struct | |
398 | { | |
399 | uint32_t c3_wakeuptimer_enable :1; | |
400 | uint32_t enable_mclk_pll_shutdown :1; | |
401 | uint32_t spi_clk_disable :1; | |
402 | uint32_t unallocated :29; | |
403 | } bits; | |
404 | ||
405 | } sbox_uos_pcu_ctrl_t; | |
406 | ||
407 | typedef union _sboxCorefreqReg | |
408 | { | |
409 | uint32_t value; | |
410 | struct | |
411 | { | |
412 | uint32_t ratio :12; // bit 0-11 Ratio | |
413 | uint32_t rsvd0 : 3; // bit 12-14 | |
414 | uint32_t fuseratio : 1; // bit 15 If overclocking is enabled, setting this bit will default the goal ratio to the fuse value. | |
415 | uint32_t asyncmode : 1; // bit 16 Async Mode Bit 16, Reserved Bits 20:17 used to be ExtClkFreq, | |
416 | uint32_t rsvd1 : 9; // bit 17-25 | |
417 | uint32_t ratiostep : 4; // bit 26-29 Power throttle ratio-step | |
418 | uint32_t jumpratio : 1; // bit 30 Power throttle jump at once | |
419 | uint32_t booted : 1; // bit 31 Booted: This bit selects between the default MCLK Ratio (600MHz) and the programmable MCLK ratio. 0=default 1=programmable. | |
420 | } bits; | |
421 | ||
422 | } sbox_core_freq_t; | |
423 | ||
424 | typedef union _sboxCoreVoltReg | |
425 | { | |
426 | uint32_t value; | |
427 | struct | |
428 | { | |
429 | uint32_t vid :8; | |
430 | uint32_t unallocated :24; | |
431 | } bits; | |
432 | ||
433 | } sbox_core_volt_t; | |
434 | ||
435 | typedef enum _PM_CONNECTION_STATE { | |
436 | PM_CONNECTING, | |
437 | PM_CONNECTED, | |
438 | PM_DISCONNECTING, | |
439 | PM_DISCONNECTED | |
440 | } PM_CONNECTION_STATE; | |
441 | ||
442 | #endif //__MIC_PM_H |