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1 | /* |
2 | * Copyright 2010-2017 Intel Corporation. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License, version 2, | |
6 | * as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
11 | * General Public License for more details. | |
12 | * | |
13 | * Disclaimer: The codes contained in these modules may be specific to | |
14 | * the Intel Software Development Platform codenamed Knights Ferry, | |
15 | * and the Intel product codenamed Knights Corner, and are not backward | |
16 | * compatible with other Intel products. Additionally, Intel will NOT | |
17 | * support the codes or instruction set in future products. | |
18 | * | |
19 | * Intel offers no warranty of any kind regarding the code. This code is | |
20 | * licensed on an "AS IS" basis and Intel is not obligated to provide | |
21 | * any support, assistance, installation, training, or other services | |
22 | * of any kind. Intel is also not obligated to provide any updates, | |
23 | * enhancements or extensions. Intel specifically disclaims any warranty | |
24 | * of merchantability, non-infringement, fitness for any particular | |
25 | * purpose, and any other warranty. | |
26 | * | |
27 | * Further, Intel disclaims all liability of any kind, including but | |
28 | * not limited to liability for infringement of any proprietary rights, | |
29 | * relating to the use of the code, even if Intel is notified of the | |
30 | * possibility of such liability. Except as expressly stated in an Intel | |
31 | * license agreement provided with this code and agreed upon with Intel, | |
32 | * no license, express or implied, by estoppel or otherwise, to any | |
33 | * intellectual property rights is granted herein. | |
34 | */ | |
35 | ||
36 | #ifndef _SCIF_RING_BUFFER_DEFINE | |
37 | #define _SCIF_RING_BUFFER_DEFINE | |
38 | ||
39 | /* | |
40 | * This describes a general purpose, byte based | |
41 | * ring buffer. It handles multiple readers or | |
42 | * writers using a lock -- it is lockless between | |
43 | * producer and consumer (so it can handle being | |
44 | * used across the PCIe bus). | |
45 | */ | |
46 | #include <linux/errno.h> | |
47 | #include <linux/hardirq.h> | |
48 | #include <linux/types.h> | |
49 | #include <linux/capability.h> | |
50 | #include <linux/slab.h> | |
51 | #include <linux/string.h> | |
52 | #include <linux/gfp.h> | |
53 | #include <linux/vmalloc.h> | |
54 | #include <asm/io.h> | |
55 | #include <linux/kernel.h> | |
56 | #include <linux/mm_types.h> | |
57 | #include <linux/jiffies.h> | |
58 | #include <linux/timer.h> | |
59 | #include <linux/irqflags.h> | |
60 | #include <linux/time.h> | |
61 | #include <linux/spinlock.h> | |
62 | #include <linux/mutex.h> | |
63 | #include <linux/semaphore.h> | |
64 | #include <linux/kthread.h> | |
65 | #include <linux/sched.h> | |
66 | #include <linux/delay.h> | |
67 | #include <linux/wait.h> | |
68 | #include <asm/bug.h> | |
69 | #include <linux/pci.h> | |
70 | #include <linux/device.h> | |
71 | #include <linux/fs.h> | |
72 | #include <linux/list.h> | |
73 | #include <linux/workqueue.h> | |
74 | #include <linux/interrupt.h> | |
75 | #include <asm/atomic.h> | |
76 | #include <linux/netdevice.h> | |
77 | #include <linux/debugfs.h> | |
78 | ||
79 | /** | |
80 | * This version is used to ensure component compatibility between the host and | |
81 | * card driver modules that use the ring buffer functions. This version should | |
82 | * be incremented whenever there is a change to the ring buffer module that | |
83 | * affects the functionality of the ring buffer. | |
84 | */ | |
85 | #define RING_BUFFER_VERSION 1 | |
86 | ||
87 | /* Two of these actually form a single queue -- one on each side of the PCIe | |
88 | * bus | |
89 | * | |
90 | * NOTE! This only works if the queue (pointed to at rb_base) exists in the | |
91 | * consumer's memory. The code does not do any wbinvd after writing to the | |
92 | * buffer, which assumes that the memory is not cached on the writers side. | |
93 | * | |
94 | * If this structure were to be used across the PCIe bus with the buffer | |
95 | * living on the other side of the bus, it wouldn't work (would require a | |
96 | * wbinvd or use the linux dma streaming buffer API) | |
97 | */ | |
98 | struct micscif_rb { | |
99 | volatile void *rb_base; | |
100 | volatile uint32_t *read_ptr; /* Points to the read offset */ | |
101 | volatile uint32_t *write_ptr; /* Points to the write offset */ | |
102 | uint32_t size; | |
103 | uint32_t current_read_offset; /* cache it to improve performance */ | |
104 | uint32_t current_write_offset; /* cache it to improve performance */ | |
105 | uint32_t old_current_read_offset; | |
106 | uint32_t old_current_write_offset; | |
107 | }; | |
108 | ||
109 | /** | |
110 | * methods used by both | |
111 | */ | |
112 | void micscif_rb_init(struct micscif_rb *rb, volatile uint32_t *read_ptr, | |
113 | volatile uint32_t *write_ptr, volatile void *rb_base, | |
114 | const uint32_t size); | |
115 | ||
116 | /** | |
117 | * writer-only methods | |
118 | */ | |
119 | /* | |
120 | * write a new command, then micscif_rb_commit() | |
121 | */ | |
122 | int micscif_rb_write(struct micscif_rb *rb, void *msg, uint32_t size); | |
123 | /* | |
124 | * After write(), then micscif_rb_commit() | |
125 | */ | |
126 | void micscif_rb_commit(struct micscif_rb *rb); | |
127 | /* | |
128 | * used on power state change to reset cached pointers | |
129 | */ | |
130 | void micscif_rb_reset(struct micscif_rb *rb); | |
131 | ||
132 | /* | |
133 | * Query space available for writing to a RB. | |
134 | */ | |
135 | int micscif_rb_space(struct micscif_rb *rb); | |
136 | /** | |
137 | * reader-only methods | |
138 | */ | |
139 | /* | |
140 | * uses (updates) the cached read pointer to get the next command, | |
141 | * so writer doesnt see the command as consumed. | |
142 | * | |
143 | * Returns number of bytes read | |
144 | * | |
145 | * Size is IN -- the caller passes in a size (the max size that | |
146 | * the function will read out) | |
147 | * | |
148 | * msg is OUT, but the caller is responsible for allocating space to | |
149 | * read into. The max size this function will read is what is passed | |
150 | * into by size, so the buffer pointer to by msg MUST be at least size | |
151 | * bytes long. | |
152 | */ | |
153 | int micscif_rb_get_next (struct micscif_rb *rb, void *msg, uint32_t size); | |
154 | ||
155 | /* | |
156 | * updates the control block read pointer, | |
157 | * which will be visible to the writer so it can re-use the space | |
158 | */ | |
159 | void micscif_rb_update_read_ptr(struct micscif_rb *rb); | |
160 | ||
161 | /* | |
162 | * Count the number of empty slots in the RB | |
163 | */ | |
164 | uint32_t micscif_rb_count(struct micscif_rb *rb, uint32_t size); | |
165 | ||
166 | /** | |
167 | * Return the ring buffer module version. | |
168 | */ | |
169 | uint16_t micscif_rb_get_version(void); | |
170 | #endif |