[OpenSPARC-T2-DV] / design / fpga / opencores / raminfr.v

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  raminfr.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  Inferrable Distributed RAM for FIFOs                        ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None                .                                       ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing so far.                                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////                                                              ////
////  Created:        2002/07/22                                  ////
////  Last Updated:   2002/07/22                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: raminfr.v,v $
// Revision 1.2  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//

//Following is the Verilog code for a dual-port RAM with asynchronous read.

module raminfr(clk, we, a, dpra, di, dpo);

	parameter		addr_width	= 4;
	parameter		data_width	= 8;
	parameter		depth		= 16;

	input			clk;
	input			we;
	input	[(addr_width - 1):0]
				a;
	input	[(addr_width - 1):0]
				dpra;
	input	[(data_width - 1):0]
				di;
	output	[(data_width - 1):0]
				dpo;

	reg	[(data_width - 1):0]
				ram[(depth - 1):0];

	assign dpo = ram[dpra];

	always @(posedge clk) begin
	  if (we) begin
	    ram[a] <= di;
	  end
	end
endmodule
Commit	Line	Data
86530b38 AT	1	//////////////////////////////////////////////////////////////////////
	2	//// ////
	3	//// raminfr.v ////
	4	//// ////
	5	//// ////
	6	//// This file is part of the "UART 16550 compatible" project ////
	7	//// http://www.opencores.org/cores/uart16550/ ////
	8	//// ////
	9	//// Documentation related to this project: ////
	10	//// - http://www.opencores.org/cores/uart16550/ ////
	11	//// ////
	12	//// Projects compatibility: ////
	13	//// - WISHBONE ////
	14	//// RS232 Protocol ////
	15	//// 16550D uart (mostly supported) ////
	16	//// ////
	17	//// Overview (main Features): ////
	18	//// Inferrable Distributed RAM for FIFOs ////
	19	//// ////
	20	//// Known problems (limits): ////
	21	//// None . ////
	22	//// ////
	23	//// To Do: ////
	24	//// Nothing so far. ////
	25	//// ////
	26	//// Author(s): ////
	27	//// - gorban@opencores.org ////
	28	//// - Jacob Gorban ////
	29	//// ////
	30	//// Created: 2002/07/22 ////
	31	//// Last Updated: 2002/07/22 ////
	32	//// (See log for the revision history) ////
	33	//// ////
	34	//// ////
	35	//////////////////////////////////////////////////////////////////////
	36	//// ////
	37	//// Copyright (C) 2000, 2001 Authors ////
	38	//// ////
	39	//// This source file may be used and distributed without ////
	40	//// restriction provided that this copyright statement is not ////
	41	//// removed from the file and that any derivative work contains ////
	42	//// the original copyright notice and the associated disclaimer. ////
	43	//// ////
	44	//// This source file is free software; you can redistribute it ////
	45	//// and/or modify it under the terms of the GNU Lesser General ////
	46	//// Public License as published by the Free Software Foundation; ////
	47	//// either version 2.1 of the License, or (at your option) any ////
	48	//// later version. ////
	49	//// ////
	50	//// This source is distributed in the hope that it will be ////
	51	//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
	52	//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
	53	//// PURPOSE. See the GNU Lesser General Public License for more ////
	54	//// details. ////
	55	//// ////
	56	//// You should have received a copy of the GNU Lesser General ////
	57	//// Public License along with this source; if not, download it ////
	58	//// from http://www.opencores.org/lgpl.shtml ////
	59	//// ////
	60	//////////////////////////////////////////////////////////////////////
	61	//
	62	// CVS Revision History
	63	//
	64	// $Log: raminfr.v,v $
65	// Revision 1.2 2002/07/29 21:16:18 gorban
66	// The uart_defines.v file is included again in sources.
67	//
68	// Revision 1.1 2002/07/22 23:02:23 gorban
69	// Bug Fixes:
70	// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
71	// Problem reported by Kenny.Tung.
72	// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
73	//
74	// Improvements:
75	// * Made FIFO's as general inferrable memory where possible.
76	// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
77	// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
78	//
79	// * Added optional baudrate output (baud_o).
80	// This is identical to BAUDOUT* signal on 16550 chip.
81	// It outputs 16xbit_clock_rate - the divided clock.
82	// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
83	//
84
85	//Following is the Verilog code for a dual-port RAM with asynchronous read.
86
87	module raminfr(clk, we, a, dpra, di, dpo);
88
89	parameter addr_width = 4;
90	parameter data_width = 8;
91	parameter depth = 16;
92
93	input clk;
94	input we;
95	input [(addr_width - 1):0]
96	a;
97	input [(addr_width - 1):0]
98	dpra;
99	input [(data_width - 1):0]
100	di;
101	output [(data_width - 1):0]
102	dpo;
103
104	reg [(data_width - 1):0]
105	ram[(depth - 1):0];
106
107	assign dpo = ram[dpra];
108
109	always @(posedge clk) begin
110	if (we) begin
111	ram[a] <= di;
112	end
113	end
114	endmodule