[OpenSPARC-T2-DV] / design / fpga / opencores / uart_sync_flops.v

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_sync_flops.v                                             ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core receiver logic                                    ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None known                                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Thourough testing.                                          ////
////                                                              ////
////  Author(s):                                                  ////
////      - Andrej Erzen (andreje@flextronics.si)                 ////
////      - Tadej Markovic (tadejm@flextronics.si)                ////
////                                                              ////
////  Created:        2004/05/20                                  ////
////  Last Updated:   2004/05/20                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_sync_flops.v,v $
// Revision 1.1  2004/05/21 11:43:25  tadejm
// Added to synchronize RX input to Wishbone clock.
//
//

`timescale 1 ns / 10 ps
module uart_sync_flops(rst_i, clk_i, stage1_rst_i, stage1_clk_en_i, async_dat_i,
	sync_dat_o);

	parameter		Tp		= 1;
	parameter		width		= 1;
	parameter		init_value	= 1'b0;

	input			rst_i;
	input			clk_i;
	input			stage1_rst_i;
	input			stage1_clk_en_i;
	input	[(width - 1):0]	async_dat_i;
	output	[(width - 1):0]	sync_dat_o;

	reg	[(width - 1):0]	sync_dat_o;
	reg	[(width - 1):0]	flop_0;

	always @(posedge clk_i or posedge rst_i) begin
	  if (rst_i) begin
	    flop_0 <= #(Tp) {width {init_value}};
	  end
	  else begin
	    flop_0 <= #(Tp) async_dat_i;
	  end
	end
	always @(posedge clk_i or posedge rst_i) begin
	  if (rst_i) begin
	    sync_dat_o <= #(Tp) {width {init_value}};
	  end
	  else if (stage1_rst_i) begin
	    sync_dat_o <= #(Tp) {width {init_value}};
	  end
	  else if (stage1_clk_en_i) begin
	    sync_dat_o <= #(Tp) flop_0;
	  end
	end
endmodule
Commit	Line	Data
86530b38 AT	1	//////////////////////////////////////////////////////////////////////
	2	//// ////
	3	//// uart_sync_flops.v ////
	4	//// ////
	5	//// ////
	6	//// This file is part of the "UART 16550 compatible" project ////
	7	//// http://www.opencores.org/cores/uart16550/ ////
	8	//// ////
	9	//// Documentation related to this project: ////
	10	//// - http://www.opencores.org/cores/uart16550/ ////
	11	//// ////
	12	//// Projects compatibility: ////
	13	//// - WISHBONE ////
	14	//// RS232 Protocol ////
	15	//// 16550D uart (mostly supported) ////
	16	//// ////
	17	//// Overview (main Features): ////
	18	//// UART core receiver logic ////
	19	//// ////
	20	//// Known problems (limits): ////
	21	//// None known ////
	22	//// ////
	23	//// To Do: ////
	24	//// Thourough testing. ////
	25	//// ////
	26	//// Author(s): ////
	27	//// - Andrej Erzen (andreje@flextronics.si) ////
	28	//// - Tadej Markovic (tadejm@flextronics.si) ////
	29	//// ////
	30	//// Created: 2004/05/20 ////
	31	//// Last Updated: 2004/05/20 ////
	32	//// (See log for the revision history) ////
	33	//// ////
	34	//// ////
	35	//////////////////////////////////////////////////////////////////////
	36	//// ////
	37	//// Copyright (C) 2000, 2001 Authors ////
	38	//// ////
	39	//// This source file may be used and distributed without ////
	40	//// restriction provided that this copyright statement is not ////
	41	//// removed from the file and that any derivative work contains ////
	42	//// the original copyright notice and the associated disclaimer. ////
	43	//// ////
	44	//// This source file is free software; you can redistribute it ////
	45	//// and/or modify it under the terms of the GNU Lesser General ////
	46	//// Public License as published by the Free Software Foundation; ////
	47	//// either version 2.1 of the License, or (at your option) any ////
	48	//// later version. ////
	49	//// ////
	50	//// This source is distributed in the hope that it will be ////
	51	//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
	52	//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
	53	//// PURPOSE. See the GNU Lesser General Public License for more ////
	54	//// details. ////
	55	//// ////
	56	//// You should have received a copy of the GNU Lesser General ////
	57	//// Public License along with this source; if not, download it ////
	58	//// from http://www.opencores.org/lgpl.shtml ////
	59	//// ////
	60	//////////////////////////////////////////////////////////////////////
	61	//
	62	// CVS Revision History
	63	//
	64	// $Log: uart_sync_flops.v,v $
65	// Revision 1.1 2004/05/21 11:43:25 tadejm
66	// Added to synchronize RX input to Wishbone clock.
67	//
68	//
69
70	`timescale 1 ns / 10 ps
71	module uart_sync_flops(rst_i, clk_i, stage1_rst_i, stage1_clk_en_i, async_dat_i,
72	sync_dat_o);
73
74	parameter Tp = 1;
75	parameter width = 1;
76	parameter init_value = 1'b0;
77
78	input rst_i;
79	input clk_i;
80	input stage1_rst_i;
81	input stage1_clk_en_i;
82	input [(width - 1):0] async_dat_i;
83	output [(width - 1):0] sync_dat_o;
84
85	reg [(width - 1):0] sync_dat_o;
86	reg [(width - 1):0] flop_0;
87
88	always @(posedge clk_i or posedge rst_i) begin
89	if (rst_i) begin
90	flop_0 <= #(Tp) {width {init_value}};
91	end
92	else begin
93	flop_0 <= #(Tp) async_dat_i;
94	end
95	end
96	always @(posedge clk_i or posedge rst_i) begin
97	if (rst_i) begin
98	sync_dat_o <= #(Tp) {width {init_value}};
99	end
100	else if (stage1_rst_i) begin
101	sync_dat_o <= #(Tp) {width {init_value}};
102	end
103	else if (stage1_clk_en_i) begin
104	sync_dat_o <= #(Tp) flop_0;
105	end
106	end
107	endmodule