[OpenSPARC-T2-DV] / design / fpga / opencores / uart_tfifo.v

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_tfifo.v                                                ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  UART core transmitter FIFO                                  ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2002/07/22                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: uart_tfifo.v,v $
// Revision 1.2  2002/07/29 21:16:18  gorban
// The uart_defines.v file is included again in sources.
//
// Revision 1.1  2002/07/22 23:02:23  gorban
// Bug Fixes:
//  * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
//   Problem reported by Kenny.Tung.
//  * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
//
// Improvements:
//  * Made FIFO's as general inferrable memory where possible.
//  So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
//  This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
//
//  * Added optional baudrate output (baud_o).
//  This is identical to BAUDOUT* signal on 16550 chip.
//  It outputs 16xbit_clock_rate - the divided clock.
//  It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
//
// Revision 1.16  2001/12/20 13:25:46  mohor
// rx push changed to be only one cycle wide.
//
// Revision 1.15  2001/12/18 09:01:07  mohor
// Bug that was entered in the last update fixed (rx state machine).
//
// Revision 1.14  2001/12/17 14:46:48  mohor
// overrun signal was moved to separate block because many sequential lsr
// reads were preventing data from being written to rx fifo.
// underrun signal was not used and was removed from the project.
//
// Revision 1.13  2001/11/26 21:38:54  gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.12  2001/11/08 14:54:23  mohor
// Comments in Slovene language deleted, few small fixes for better work of
// old tools. IRQs need to be fix.
//
// Revision 1.11  2001/11/07 17:51:52  gorban
// Heavily rewritten interrupt and LSR subsystems.
// Many bugs hopefully squashed.
//
// Revision 1.10  2001/10/20 09:58:40  gorban
// Small synopsis fixes
//
// Revision 1.9  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.8  2001/08/24 08:48:10  mohor
// FIFO was not cleared after the data was read bug fixed.
//
// Revision 1.7  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.3  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.3  2001/05/27 17:37:48  gorban
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
//
// Revision 1.2  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:12+02  jacob
// Initial revision
//
//

`timescale 1 ns / 10 ps
module uart_tfifo(clk, wb_rst_i, data_in, data_out, push, pop, overrun, count, 
	fifo_reset, reset_status);

	parameter		fifo_width	= 8;
	parameter		fifo_depth	= 16;
	parameter		fifo_pointer_w	= 4;
	parameter		fifo_counter_w	= 5;

	input			clk;
	input			wb_rst_i;
	input			push;
	input			pop;
	input	[(fifo_width - 1):0]
				data_in;
	input			fifo_reset;
	input			reset_status;
	output	[(fifo_width - 1):0]
				data_out;
	output			overrun;
	output	[(fifo_counter_w - 1):0]
				count;

	reg	[(fifo_pointer_w - 1):0]
				top;
	reg	[(fifo_pointer_w - 1):0]
				bottom;
	reg			overrun;
	reg	[(fifo_counter_w - 1):0]
				count;
	wire	[(fifo_pointer_w - 1):0]
				top_plus_1 = (top + 1'b1);


	raminfr #(fifo_pointer_w, fifo_width, fifo_depth) tfifo(
		.clk				(clk), 
		.we				(push), 
		.a				(top), 
		.dpra				(bottom), 
		.di				(data_in), 
		.dpo				(data_out));

	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    top <= #(1) 0;
	    bottom <= #(1) 1'b0;
	    count <= #(1) 0;
	  end
	  else if (fifo_reset) begin
	    top <= #(1) 0;
	    bottom <= #(1) 1'b0;
	    count <= #(1) 0;
	  end
	  else
	    begin
	      case ({push, pop})
		2'b10:
		  if (count < fifo_depth) begin
		    top <= #(1) top_plus_1;
		    count <= #(1) (count + 1'b1);
		  end
		2'b1:
		  if (count > 0) begin
		    bottom <= #(1) (bottom + 1'b1);
		    count <= #(1) (count - 1'b1);
		  end
		2'b11: begin
		  bottom <= #(1) (bottom + 1'b1);
		  top <= #(1) top_plus_1;
		end
		default:
		  ;
	      endcase
	    end
	end
	always @(posedge clk or posedge wb_rst_i) begin
	  if (wb_rst_i) begin
	    overrun <= #(1) 1'b0;
	  end
	  else if (fifo_reset | reset_status) begin
	    overrun <= #(1) 1'b0;
	  end
	  else if (push & (count == fifo_depth)) begin
	    overrun <= #(1) 1'b1;
	  end
	end
endmodule
Commit	Line	Data
86530b38 AT	1	//////////////////////////////////////////////////////////////////////
	2	//// ////
	3	//// uart_tfifo.v ////
	4	//// ////
	5	//// ////
	6	//// This file is part of the "UART 16550 compatible" project ////
	7	//// http://www.opencores.org/cores/uart16550/ ////
	8	//// ////
	9	//// Documentation related to this project: ////
	10	//// - http://www.opencores.org/cores/uart16550/ ////
	11	//// ////
	12	//// Projects compatibility: ////
	13	//// - WISHBONE ////
	14	//// RS232 Protocol ////
	15	//// 16550D uart (mostly supported) ////
	16	//// ////
	17	//// Overview (main Features): ////
	18	//// UART core transmitter FIFO ////
	19	//// ////
	20	//// To Do: ////
	21	//// Nothing. ////
	22	//// ////
	23	//// Author(s): ////
	24	//// - gorban@opencores.org ////
	25	//// - Jacob Gorban ////
	26	//// - Igor Mohor (igorm@opencores.org) ////
	27	//// ////
	28	//// Created: 2001/05/12 ////
	29	//// Last Updated: 2002/07/22 ////
	30	//// (See log for the revision history) ////
	31	//// ////
	32	//// ////
	33	//////////////////////////////////////////////////////////////////////
	34	//// ////
	35	//// Copyright (C) 2000, 2001 Authors ////
	36	//// ////
	37	//// This source file may be used and distributed without ////
	38	//// restriction provided that this copyright statement is not ////
	39	//// removed from the file and that any derivative work contains ////
	40	//// the original copyright notice and the associated disclaimer. ////
	41	//// ////
	42	//// This source file is free software; you can redistribute it ////
	43	//// and/or modify it under the terms of the GNU Lesser General ////
	44	//// Public License as published by the Free Software Foundation; ////
	45	//// either version 2.1 of the License, or (at your option) any ////
	46	//// later version. ////
	47	//// ////
	48	//// This source is distributed in the hope that it will be ////
	49	//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
	50	//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
	51	//// PURPOSE. See the GNU Lesser General Public License for more ////
	52	//// details. ////
	53	//// ////
	54	//// You should have received a copy of the GNU Lesser General ////
	55	//// Public License along with this source; if not, download it ////
	56	//// from http://www.opencores.org/lgpl.shtml ////
	57	//// ////
	58	//////////////////////////////////////////////////////////////////////
	59	//
	60	// CVS Revision History
	61	//
	62	// $Log: uart_tfifo.v,v $
	63	// Revision 1.2 2002/07/29 21:16:18 gorban
	64	// The uart_defines.v file is included again in sources.
65	//
66	// Revision 1.1 2002/07/22 23:02:23 gorban
67	// Bug Fixes:
68	// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
69	// Problem reported by Kenny.Tung.
70	// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
71	//
72	// Improvements:
73	// * Made FIFO's as general inferrable memory where possible.
74	// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
75	// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
76	//
77	// * Added optional baudrate output (baud_o).
78	// This is identical to BAUDOUT* signal on 16550 chip.
79	// It outputs 16xbit_clock_rate - the divided clock.
80	// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
81	//
82	// Revision 1.16 2001/12/20 13:25:46 mohor
83	// rx push changed to be only one cycle wide.
84	//
85	// Revision 1.15 2001/12/18 09:01:07 mohor
86	// Bug that was entered in the last update fixed (rx state machine).
87	//
88	// Revision 1.14 2001/12/17 14:46:48 mohor
89	// overrun signal was moved to separate block because many sequential lsr
90	// reads were preventing data from being written to rx fifo.
91	// underrun signal was not used and was removed from the project.
92	//
93	// Revision 1.13 2001/11/26 21:38:54 gorban
94	// Lots of fixes:
95	// Break condition wasn't handled correctly at all.
96	// LSR bits could lose their values.
97	// LSR value after reset was wrong.
98	// Timing of THRE interrupt signal corrected.
99	// LSR bit 0 timing corrected.
100	//
101	// Revision 1.12 2001/11/08 14:54:23 mohor
102	// Comments in Slovene language deleted, few small fixes for better work of
103	// old tools. IRQs need to be fix.
104	//
105	// Revision 1.11 2001/11/07 17:51:52 gorban
106	// Heavily rewritten interrupt and LSR subsystems.
107	// Many bugs hopefully squashed.
108	//
109	// Revision 1.10 2001/10/20 09:58:40 gorban
110	// Small synopsis fixes
111	//
112	// Revision 1.9 2001/08/24 21:01:12 mohor
113	// Things connected to parity changed.
114	// Clock devider changed.
115	//
116	// Revision 1.8 2001/08/24 08:48:10 mohor
117	// FIFO was not cleared after the data was read bug fixed.
118	//
119	// Revision 1.7 2001/08/23 16:05:05 mohor
120	// Stop bit bug fixed.
121	// Parity bug fixed.
122	// WISHBONE read cycle bug fixed,
123	// OE indicator (Overrun Error) bug fixed.
124	// PE indicator (Parity Error) bug fixed.
125	// Register read bug fixed.
126	//
127	// Revision 1.3 2001/05/31 20:08:01 gorban
128	// FIFO changes and other corrections.
129	//
130	// Revision 1.3 2001/05/27 17:37:48 gorban
131	// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
132	//
133	// Revision 1.2 2001/05/17 18:34:18 gorban
134	// First 'stable' release. Should be sythesizable now. Also added new header.
135	//
136	// Revision 1.0 2001-05-17 21:27:12+02 jacob
137	// Initial revision
138	//
139	//
140
141	`timescale 1 ns / 10 ps
142	module uart_tfifo(clk, wb_rst_i, data_in, data_out, push, pop, overrun, count,
143	fifo_reset, reset_status);
144
145	parameter fifo_width = 8;
146	parameter fifo_depth = 16;
147	parameter fifo_pointer_w = 4;
148	parameter fifo_counter_w = 5;
149
150	input clk;
151	input wb_rst_i;
152	input push;
153	input pop;
154	input [(fifo_width - 1):0]
155	data_in;
156	input fifo_reset;
157	input reset_status;
158	output [(fifo_width - 1):0]
159	data_out;
160	output overrun;
161	output [(fifo_counter_w - 1):0]
162	count;
163
164	reg [(fifo_pointer_w - 1):0]
165	top;
166	reg [(fifo_pointer_w - 1):0]
167	bottom;
168	reg overrun;
169	reg [(fifo_counter_w - 1):0]
170	count;
171	wire [(fifo_pointer_w - 1):0]
172	top_plus_1 = (top + 1'b1);
173
174
175	raminfr #(fifo_pointer_w, fifo_width, fifo_depth) tfifo(
176	.clk (clk),
177	.we (push),
178	.a (top),
179	.dpra (bottom),
180	.di (data_in),
181	.dpo (data_out));
182
183	always @(posedge clk or posedge wb_rst_i) begin
184	if (wb_rst_i) begin
185	top <= #(1) 0;
186	bottom <= #(1) 1'b0;
187	count <= #(1) 0;
188	end
189	else if (fifo_reset) begin
190	top <= #(1) 0;
191	bottom <= #(1) 1'b0;
192	count <= #(1) 0;
193	end
194	else
195	begin
196	case ({push, pop})
197	2'b10:
198	if (count < fifo_depth) begin
199	top <= #(1) top_plus_1;
200	count <= #(1) (count + 1'b1);
201	end
202	2'b1:
203	if (count > 0) begin
204	bottom <= #(1) (bottom + 1'b1);
205	count <= #(1) (count - 1'b1);
206	end
207	2'b11: begin
208	bottom <= #(1) (bottom + 1'b1);
209	top <= #(1) top_plus_1;
210	end
211	default:
212	;
213	endcase
214	end
215	end
216	always @(posedge clk or posedge wb_rst_i) begin
217	if (wb_rst_i) begin
218	overrun <= #(1) 1'b0;
219	end
220	else if (fifo_reset \| reset_status) begin
221	overrun <= #(1) 1'b0;
222	end
223	else if (push & (count == fifo_depth)) begin
224	overrun <= #(1) 1'b1;
225	end
226	end
227	endmodule