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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ccu_io_rstgen.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ccu_io_rstgen ( | |
36 | iol2clk, | |
37 | csr_ucb_rst_n, | |
38 | tcu_atpg_mode, | |
39 | csr_rst_n, | |
40 | ucb_rst_n | |
41 | ); | |
42 | ||
43 | // port def | |
44 | ||
45 | input iol2clk; | |
46 | input csr_ucb_rst_n; | |
47 | input tcu_atpg_mode; | |
48 | output csr_rst_n; | |
49 | output ucb_rst_n; | |
50 | ||
51 | ||
52 | // external wire/reg def | |
53 | ||
54 | wire iol2clk; | |
55 | wire csr_ucb_rst_n; | |
56 | wire tcu_atpg_mode; | |
57 | wire csr_rst_n; | |
58 | wire ucb_rst_n; | |
59 | ||
60 | ||
61 | // internal wire/reg def | |
62 | ||
63 | wire io_csr_ucb_rst_n; | |
64 | wire pre_io_csr_ucb_rst_n; | |
65 | ||
66 | // | |
67 | // async active-low reset assertion, sync deassertion | |
68 | // | |
69 | assign io_csr_ucb_rst_n = pre_io_csr_ucb_rst_n & csr_ucb_rst_n; | |
70 | ||
71 | cl_a1_clksyncff_4x csr_ucb_rst_syncff ( | |
72 | .l1clk (l1clk), .d (csr_ucb_rst_n), .q(pre_io_csr_ucb_rst_n), | |
73 | .si(1'b0), .siclk(1'b0), .soclk (1'b0), .so() | |
74 | ); | |
75 | ||
76 | ||
77 | assign ucb_rst_n = io_csr_ucb_rst_n; // no gating needed since drives sync flops | |
78 | assign csr_rst_n = io_csr_ucb_rst_n | tcu_atpg_mode; // drives async flops | |
79 | ||
80 | ||
81 | // *********************************************************** | |
82 | // L1 header - iol2 clk | |
83 | // *********************************************************** | |
84 | // | |
85 | cl_a1_l1hdr_8x header_iol2clk ( | |
86 | .l2clk(iol2clk), | |
87 | .l1clk(l1clk), | |
88 | .pce(1'b1), | |
89 | .se(1'b0), | |
90 | .pce_ov(1'b1), | |
91 | .stop(1'b0) | |
92 | ); | |
93 | ||
94 | endmodule |