design/sys/iop/ccu/rtl/ccu_io_rstgen.v

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ccu_io_rstgen.v
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module ccu_io_rstgen (
        iol2clk,
        csr_ucb_rst_n,
        tcu_atpg_mode,
        csr_rst_n,
        ucb_rst_n
);

// port def

input iol2clk;
input csr_ucb_rst_n;
input tcu_atpg_mode;
output csr_rst_n;
output ucb_rst_n;


// external wire/reg def

wire iol2clk;
wire csr_ucb_rst_n;
wire tcu_atpg_mode;
wire csr_rst_n;
wire ucb_rst_n;


// internal wire/reg def

wire io_csr_ucb_rst_n;
wire pre_io_csr_ucb_rst_n;

//
// async active-low reset assertion, sync deassertion
//
assign io_csr_ucb_rst_n = pre_io_csr_ucb_rst_n & csr_ucb_rst_n;

cl_a1_clksyncff_4x csr_ucb_rst_syncff (
        .l1clk (l1clk), .d (csr_ucb_rst_n), .q(pre_io_csr_ucb_rst_n),
        .si(1'b0), .siclk(1'b0), .soclk (1'b0), .so()
);


assign ucb_rst_n = io_csr_ucb_rst_n;  // no gating needed since drives sync flops
assign csr_rst_n = io_csr_ucb_rst_n  |  tcu_atpg_mode;  // drives async flops


// ***********************************************************
// L1 header - iol2 clk
// ***********************************************************
//
cl_a1_l1hdr_8x header_iol2clk (
    .l2clk(iol2clk),
    .l1clk(l1clk),
    .pce(1'b1),
    .se(1'b0),
    .pce_ov(1'b1),
    .stop(1'b0)
);

endmodule