[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_clu_ctm_datactlfsm.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_clu_ctm_datactlfsm.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
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// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
// For the avoidance of doubt, and except that if any non-GPL license 
// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
// software where a choice of GPL license versions is made 
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// have any questions. 
// 
// ========== Copyright Header End ============================================
module dmu_clu_ctm_datactlfsm 
  (
   // clock/reset
   clk,
   rst_l,
   
   // fsm inputs
   icr_fifo_empty,
   icr_grnt,
   nxt_tag_avail,
   mwr_vld,
   eqwr_vld,
   mdo_vld,
   pio16_vld,
   pio64_vld,
   null_vld,
   mwr_err,
   eqwr_err,
   diu_dma_empty,
   diu_pio_empty,
   
   // fsm outputs
   diu_dma_bufmgmt_bsy,
   diu_eqw_bufmgmt_bsy,
   diu_typ_sel,
   inc_dma_blk_addr,
   inc_pio_blk_addr,
   inc_eqw_blk_addr,
   inc_mdo_blk_addr,
   ld_diu_addr,
   inc_diu_row_ptr,
   dpath_sel,
   ld_diu_data,
   
   // debug port
   datactlfsm_state,
   
   // idle checker port
   datactlfsm_idle
   );
  
  // synopsys sync_set_reset "rst_l"
  
  // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
  
  // --------------------------------------------------------
  // State Number
  // --------------------------------------------------------
  
  parameter STATE_NUM = 21;
  
  // --------------------------------------------------------
  // State Declarations
  // --------------------------------------------------------
  
  parameter // summit enum cur_enum
	    IDLE      = 0,
	    DMA_DATA1 = 1,
	    DMA_DATA2 = 2,
	    DMA_DATA3 = 3,
	    DMA_STALL = 4,
	    EQW_DATA1 = 5,
	    EQW_DATA2 = 6,
	    EQW_DATA3 = 7,
	    EQW_STALL = 8,
	    MDO_DATA1 = 9,
	    MDO_DATA2 = 10,
	    MDO_DATA3 = 11,
	    MDO_STALL = 12,
	    P16_DATA1 = 13,
	    P16_WAIT1 = 14,
	    P16_WAIT2 = 15,
	    P16_STALL = 16,
	    P64_DATA1 = 17,
	    P64_DATA2 = 18,
	    P64_DATA3 = 19,
	    P64_STALL = 20;
  
  // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
  
  // --------------------------------------------------------
  // Clock/Reset Signals
  // --------------------------------------------------------
  
  input clk;
  input rst_l;
  
  // --------------------------------------------------------
  // FSM Inputs
  // --------------------------------------------------------
  
  input icr_fifo_empty;
  input icr_grnt;
  input nxt_tag_avail;
  input mwr_vld;
  input eqwr_vld;
  input mdo_vld;
  input pio16_vld;
  input pio64_vld;
  input null_vld;
  input mwr_err;
  input eqwr_err;
  input diu_dma_empty;
  input diu_pio_empty;
  
  // --------------------------------------------------------
  // FSM Outputs
  // --------------------------------------------------------
  
  output       diu_dma_bufmgmt_bsy;
  output       diu_eqw_bufmgmt_bsy;
  output [1:0] diu_typ_sel;
  output       inc_dma_blk_addr;
  output       inc_pio_blk_addr;
  output       inc_eqw_blk_addr;
  output       inc_mdo_blk_addr;
  output       ld_diu_addr;
  output       inc_diu_row_ptr;
  output       dpath_sel;
  output       ld_diu_data;
  
  // debug port
  output [4:0] datactlfsm_state;
  
  // idle checker port
  output       datactlfsm_idle;
  
  // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
  
  // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  
  // ********** Flops **********
  
  reg [(STATE_NUM - 1):0] cur_state;
  reg dpath_sel_s0;
  reg dpath_sel_s1;
  reg dpath_sel_s2;
  
  // ********** Non-Flops ******
  
  reg [(STATE_NUM - 1):0] nxt_state;
  reg [4:0] 		  enc_state;
  reg [1:0] 		  diu_typ_sel;
  
  // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  
  wire 			  proc_mwr;
  wire 			  proc_p16;
  wire 			  proc_p64;
  wire 			  eqw_bufrel;
  wire 			  dmaw_bufrel;
  
  // >>>>>>>>>>>>>>>>>>>>>>>>> 0-in Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
  
  // 0in one_hot -var cur_state
  
  ///// STATE TRANSITION CHECKER //////////////////////////////////////////////
  
  // ----- IDLE ---------------------------------------------------------------
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << IDLE)
     -next (21'b1 << IDLE)
           (21'b1 << DMA_DATA1)
           (21'b1 << EQW_DATA1)
           (21'b1 << MDO_DATA1)
           (21'b1 << P16_DATA1)
           (21'b1 << P64_DATA1)
     -match_by_cycle
  */
  
  // ----- DMA ----------------------------------------------------------------
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << DMA_DATA1)
     -next (21'b1 << DMA_DATA2)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << DMA_DATA2)
     -next (21'b1 << DMA_DATA3)
           (21'b1 << DMA_STALL)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << DMA_DATA3)
     -next (21'b1 << IDLE)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << DMA_STALL)
     -next (21'b1 << DMA_DATA3)
           (21'b1 << DMA_STALL)
     -match_by_cycle
  */
  
  // ----- EQW ----------------------------------------------------------------
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << EQW_DATA1)
     -next (21'b1 << EQW_DATA2)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << EQW_DATA2)
     -next (21'b1 << EQW_DATA3)
           (21'b1 << EQW_STALL)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << EQW_DATA3)
     -next (21'b1 << IDLE)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << EQW_STALL)
     -next (21'b1 << EQW_DATA3)
           (21'b1 << EQW_STALL)
     -match_by_cycle
  */
  
  // ----- MDO ----------------------------------------------------------------
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << MDO_DATA1)
     -next (21'b1 << MDO_DATA2)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << MDO_DATA2)
     -next (21'b1 << MDO_DATA3)
           (21'b1 << MDO_STALL)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << MDO_DATA3)
     -next (21'b1 << IDLE)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << MDO_STALL)
     -next (21'b1 << MDO_DATA3)
           (21'b1 << MDO_STALL)
     -match_by_cycle
  */
  
  // ----- P16 ----------------------------------------------------------------
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << P16_DATA1)
     -next (21'b1 << P16_WAIT1)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << P16_WAIT1)
     -next (21'b1 << P16_WAIT2)
           (21'b1 << P16_STALL)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << P16_WAIT2)
     -next (21'b1 << IDLE)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << P16_STALL)
     -next (21'b1 << P16_WAIT2)
           (21'b1 << P16_STALL)
     -match_by_cycle
  */
  
  // ----- P64 ----------------------------------------------------------------
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << P64_DATA1)
     -next (21'b1 << P64_DATA2)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << P64_DATA2)
     -next (21'b1 << P64_DATA3)
           (21'b1 << P64_STALL)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << P64_DATA3)
     -next (21'b1 << IDLE)
     -match_by_cycle
  */
  
  /* 0in state
     -var  cur_state
     -val  (21'b1 << P64_STALL)
     -next (21'b1 << P64_DATA3)
           (21'b1 << P64_STALL)
     -match_by_cycle
  */
  
  // >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
  
  // --------------------------------------------------------
  // IDLE Checker
  // --------------------------------------------------------
  
  assign datactlfsm_idle = cur_state[IDLE];
  
  // --------------------------------------------------------
  // Debug Port Logic
  // --------------------------------------------------------
  
  // encode one-hot current_state vector for debug port
  always @(cur_state[(STATE_NUM - 1):1])
    begin
      enc_state[0] = (cur_state[1]  | cur_state[3]  | cur_state[5]  |
                      cur_state[7]  | cur_state[9]  | cur_state[11] |
                      cur_state[13] | cur_state[15] | cur_state[17] |
		      cur_state[19]);
      
      enc_state[1] = (cur_state[2]  | cur_state[3]  | cur_state[6]  |
                      cur_state[7]  | cur_state[10] | cur_state[11] |
                      cur_state[14] | cur_state[15] | cur_state[18] |
		      cur_state[19]);
      
      enc_state[2] = (cur_state[4]  | cur_state[5]  | cur_state[6]  |
                      cur_state[7]  | cur_state[12] | cur_state[13] |
                      cur_state[14] | cur_state[15] | cur_state[20]);
      
      enc_state[3] = (cur_state[8]  | cur_state[9]  | cur_state[10] |
                      cur_state[11] | cur_state[12] | cur_state[13] |
                      cur_state[14] | cur_state[15]);
      
      enc_state[4] = (cur_state[16] | cur_state[17] | cur_state[18] |
                      cur_state[19] | cur_state[20]);
      
    end
  
  // output datactlfsm debug bus
  assign datactlfsm_state = enc_state;
  
  // --------------------------------------------------------
  // FSM Control Decode
  // --------------------------------------------------------
  
  assign proc_mwr = mwr_vld & ~diu_dma_empty;
  assign proc_p16 = pio16_vld & ~diu_pio_empty;
  assign proc_p64 = pio64_vld & ~diu_pio_empty;
  
  // --------------------------------------------------------
  // FSM Next State
  // --------------------------------------------------------
  
  // next state assignment
  always @(cur_state or icr_grnt or icr_fifo_empty or proc_p16 or proc_p64 or
	   proc_mwr or eqwr_vld or mdo_vld or nxt_tag_avail)
    begin
      
      // initialization
      nxt_state = {STATE_NUM{1'b0}};
      
      case (1'b1) // synopsys parallel_case
	
	// 0in < case -full
	
	///////////////////////////////////////////////////////////////////////
	
	// IDLE State
	cur_state[IDLE] :
	  casez ({icr_fifo_empty, proc_mwr, eqwr_vld, mdo_vld, proc_p16,
		  proc_p64})
	    
	    // 0in < case -parallel -full
	    
	    6'b1_zzzzz,
	    6'b0_00000 : nxt_state[IDLE]      = 1'b1;
	    6'b0_10000 : nxt_state[DMA_DATA1] = 1'b1;
	    6'b0_01000 : nxt_state[EQW_DATA1] = 1'b1;
	    6'b0_00100 : nxt_state[MDO_DATA1] = 1'b1;
	    6'b0_00010 : nxt_state[P16_DATA1] = 1'b1;
	    6'b0_00001 : nxt_state[P64_DATA1] = 1'b1;
	  endcase
	
	///////////////////////////////////////////////////////////////////////
	
	// ---------- DMA WR ----------------------------------------
	
	// DMA_DATA1 State
	cur_state[DMA_DATA1] :
	  nxt_state[DMA_DATA2] = 1'b1;
	
	// DMA_DATA2 State
	cur_state[DMA_DATA2] :
	  casez ({icr_grnt, nxt_tag_avail})
	    
	    // 0in < case -parallel -full
	    
	    2'b0z,
	    2'b10 : nxt_state[DMA_STALL] = 1'b1;
	    2'b11 : nxt_state[DMA_DATA3] = 1'b1;
	  endcase
	
	// DMA_DATA3 State
	cur_state[DMA_DATA3] :
	  nxt_state[IDLE] = 1'b1;
	
	// DMA_STALL State
	cur_state[DMA_STALL] :
	  casez ({icr_grnt, nxt_tag_avail})
	    
	    // 0in < case -parallel -full
	    
	    2'b0z,
	    2'b10 : nxt_state[DMA_STALL] = 1'b1;
	    2'b11 : nxt_state[DMA_DATA3] = 1'b1;
	  endcase
	
	///////////////////////////////////////////////////////////////////////
	
	// ---------- EQ WR -----------------------------------------
	
	// EQW_DATA1 State
	cur_state[EQW_DATA1] :
	  nxt_state[EQW_DATA2] = 1'b1;
	
	// EQW_DATA2 State
	cur_state[EQW_DATA2] :
	  casez ({icr_grnt, nxt_tag_avail})
	    
	    // 0in < case -parallel -full
	    
	    2'b0z,
	    2'b10 : nxt_state[EQW_STALL] = 1'b1;
	    2'b11 : nxt_state[EQW_DATA3] = 1'b1;
	  endcase
	
	// EQW_DATA3 State
	cur_state[EQW_DATA3] :
	  nxt_state[IDLE] = 1'b1;
	
	// EQW_STALL State
	cur_state[EQW_STALL] :
	  casez ({icr_grnt, nxt_tag_avail})
	    
	    // 0in < case -parallel -full
	    
	    2'b0z,
	    2'b10 : nxt_state[EQW_STALL] = 1'b1;
	    2'b11 : nxt_state[EQW_DATA3] = 1'b1;
	  endcase
	
	///////////////////////////////////////////////////////////////////////
	
	// ---------- MDO -------------------------------------------
	
	// MDO_DATA1 State
	cur_state[MDO_DATA1] :
	  nxt_state[MDO_DATA2] = 1'b1;
	
	// MDO_DATA2 State
	cur_state[MDO_DATA2] :
	  casez ({icr_grnt, nxt_tag_avail})
	    
	    // 0in < case -parallel -full
	    
	    2'b0z,
	    2'b10 : nxt_state[MDO_STALL] = 1'b1;
	    2'b11 : nxt_state[MDO_DATA3] = 1'b1;
	  endcase
	
	// MDO_DATA3 State
	cur_state[MDO_DATA3] :
	  nxt_state[IDLE] = 1'b1;
	
	// MDO_STALL State
	cur_state[MDO_STALL] :
	  casez ({icr_grnt, nxt_tag_avail})
	    
	    // 0in < case -parallel -full
	    
	    2'b0z,
	    2'b10 : nxt_state[MDO_STALL] = 1'b1;
	    2'b11 : nxt_state[MDO_DATA3] = 1'b1;
	  endcase
	
	///////////////////////////////////////////////////////////////////////
	
	// ---------- PIO 16 CPL ------------------------------------
	
	// P16_DATA1 State
	cur_state[P16_DATA1] :
	  nxt_state[P16_WAIT1] = 1'b1;
	
	// P16_WAIT1 State
	cur_state[P16_WAIT1] :
	  if (icr_grnt)
	    nxt_state[P16_WAIT2] = 1'b1;
	  else
	    nxt_state[P16_STALL] = 1'b1;
	
	// P16_WAIT2 State
	cur_state[P16_WAIT2] :
	  nxt_state[IDLE] = 1'b1;
	
	// P16_STALL State
	cur_state[P16_STALL] :
	  if (icr_grnt)
	    nxt_state[P16_WAIT2] = 1'b1;
	  else
	    nxt_state[P16_STALL] = 1'b1;
	
	///////////////////////////////////////////////////////////////////////
	
	// ---------- PIO 64 CPL ------------------------------------
	
	// P64_DATA1 State
	cur_state[P64_DATA1] :
	  nxt_state[P64_DATA2] = 1'b1;
	
	// P64_DATA2 State
	cur_state[P64_DATA2] :
	  if (icr_grnt)
	    nxt_state[P64_DATA3] = 1'b1;
	  else
	    nxt_state[P64_STALL] = 1'b1;
	
	// P64_DATA3 State
	cur_state[P64_DATA3] :
	  nxt_state[IDLE] = 1'b1;
	
	// P64_STALL State
	cur_state[P64_STALL] :
	  if (icr_grnt)
	    nxt_state[P64_DATA3] = 1'b1;
	  else
	    nxt_state[P64_STALL] = 1'b1;
	
	///////////////////////////////////////////////////////////////////////
	
      endcase
    end
  
  // --------------------------------------------------------
  // FSM Current State
  // --------------------------------------------------------
  
  // summit state_vector cur_state enum cur_enum
  
  // current state assignment
  always @(posedge clk)
    if (~rst_l)
      begin
	cur_state       <= {STATE_NUM{1'b0}};
	cur_state[IDLE] <= 1'b1;
      end
    else
      cur_state         <= nxt_state;
  
  // --------------------------------------------------------
  // FSM Output Generation
  // --------------------------------------------------------
  
  // ----- data path control --------------------------------------------------
  
  // generate data path select
  always @(posedge clk)
    if (~rst_l)
      begin
	dpath_sel_s0 <= 1'b0;
	dpath_sel_s1 <= 1'b0;
	dpath_sel_s2 <= 1'b0;
      end
//    else if (nxt_state[EQW_DATA3] | nxt_state[MDO_DATA3])	// BP n2 10-25-04, MDO is now 1 data beat
    else if (nxt_state[EQW_DATA3] )
      begin
	dpath_sel_s0 <= 1'b1;
	dpath_sel_s1 <= 1'b1;
	dpath_sel_s2 <= 1'b1;
      end
    else
      begin
	dpath_sel_s0 <= 1'b0;
	dpath_sel_s1 <= dpath_sel_s0;
	dpath_sel_s2 <= dpath_sel_s1;
      end
  
  // output data path select
  assign dpath_sel = dpath_sel_s2;
  
  // generate data pipe load
  assign ld_diu_data = ~(cur_state[MDO_STALL] | cur_state[EQW_STALL] |
			 cur_state[DMA_STALL] | cur_state[P64_STALL] |
			 cur_state[P16_STALL]);
  
  // ----- diu buffer management control --------------------------------------
  
  // block address segment select
  always @(nxt_state)
    begin
      if (nxt_state[DMA_DATA1])
	diu_typ_sel = 2'b00;
      else if (nxt_state[P16_DATA1] | nxt_state[P64_DATA1])
	diu_typ_sel = 2'b01;
      else if (nxt_state[EQW_DATA1])
	diu_typ_sel = 2'b10;
      else if (nxt_state[MDO_DATA1])
	diu_typ_sel = 2'b11;
      else
	diu_typ_sel = 2'b00;
    end
  
  // dma buffer busy
  assign diu_dma_bufmgmt_bsy = (nxt_state[DMA_DATA1] | cur_state[DMA_DATA1] |
				cur_state[DMA_DATA2] | cur_state[DMA_DATA3]);
  
  // eqw buffer busy
  assign diu_eqw_bufmgmt_bsy = nxt_state[EQW_DATA1];
  
  // buffer release for dmaw_err, eqw_err & null
  assign dmaw_bufrel = ~icr_fifo_empty & ~diu_dma_bufmgmt_bsy & mwr_err;
  assign eqw_bufrel  = (~icr_fifo_empty & ~diu_eqw_bufmgmt_bsy &
			(eqwr_err | null_vld));
  
  // buffer block address increment
  assign inc_dma_blk_addr = nxt_state[DMA_DATA3] | dmaw_bufrel;
  assign inc_eqw_blk_addr = nxt_state[EQW_DATA3] | eqw_bufrel;
  assign inc_mdo_blk_addr = nxt_state[MDO_DATA3];
  assign inc_pio_blk_addr = nxt_state[P16_WAIT2] | nxt_state[P64_DATA3];
  
  // buffer read address load
  assign ld_diu_addr = (nxt_state[DMA_DATA1] | nxt_state[EQW_DATA1] |
			nxt_state[MDO_DATA1] | nxt_state[P16_DATA1] |
			nxt_state[P64_DATA1]);
  
  // buffer row address increment
  assign inc_diu_row_ptr = (cur_state[DMA_DATA1] | cur_state[DMA_DATA3] |
			    cur_state[P64_DATA1] | cur_state[P64_DATA3] |
			    ((cur_state[DMA_DATA2] | cur_state[DMA_STALL]) &
			     nxt_state[DMA_DATA3]) |
			    ((cur_state[P64_DATA2] | cur_state[P64_STALL]) &
			     nxt_state[P64_DATA3]));
  
endmodule // dmu_clu_ctm_datactlfsm
Commit	Line	Data
86530b38 AT	1	// ========== Copyright Header Begin ==========================================
	2	//
	3	// OpenSPARC T2 Processor File: dmu_clu_ctm_datactlfsm.v
	4	// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	5	// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	6	//
	7	// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	8	//
	9	// This program is free software; you can redistribute it and/or modify
	10	// it under the terms of the GNU General Public License as published by
	11	// the Free Software Foundation; version 2 of the License.
	12	//
	13	// This program is distributed in the hope that it will be useful,
	14	// but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	// GNU General Public License for more details.
	17	//
	18	// You should have received a copy of the GNU General Public License
	19	// along with this program; if not, write to the Free Software
	20	// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	//
	22	// For the avoidance of doubt, and except that if any non-GPL license
	23	// choice is available it will apply instead, Sun elects to use only
	24	// the General Public License version 2 (GPLv2) at this time for any
	25	// software where a choice of GPL license versions is made
	26	// available with the language indicating that GPLv2 or any later version
	27	// may be used, or where a choice of which version of the GPL is applied is
	28	// otherwise unspecified.
	29	//
	30	// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	31	// CA 95054 USA or visit www.sun.com if you need additional information or
	32	// have any questions.
	33	//
	34	// ========== Copyright Header End ============================================
	35	module dmu_clu_ctm_datactlfsm
	36	(
	37	// clock/reset
	38	clk,
	39	rst_l,
	40
	41	// fsm inputs
	42	icr_fifo_empty,
	43	icr_grnt,
	44	nxt_tag_avail,
	45	mwr_vld,
	46	eqwr_vld,
	47	mdo_vld,
	48	pio16_vld,
	49	pio64_vld,
	50	null_vld,
	51	mwr_err,
	52	eqwr_err,
	53	diu_dma_empty,
	54	diu_pio_empty,
	55
	56	// fsm outputs
	57	diu_dma_bufmgmt_bsy,
	58	diu_eqw_bufmgmt_bsy,
	59	diu_typ_sel,
	60	inc_dma_blk_addr,
	61	inc_pio_blk_addr,
	62	inc_eqw_blk_addr,
	63	inc_mdo_blk_addr,
	64	ld_diu_addr,
65	inc_diu_row_ptr,
66	dpath_sel,
67	ld_diu_data,
68
69	// debug port
70	datactlfsm_state,
71
72	// idle checker port
73	datactlfsm_idle
74	);
75
76	// synopsys sync_set_reset "rst_l"
77
78	// >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
79
80	// --------------------------------------------------------
81	// State Number
82	// --------------------------------------------------------
83
84	parameter STATE_NUM = 21;
85
86	// --------------------------------------------------------
87	// State Declarations
88	// --------------------------------------------------------
89
90	parameter // summit enum cur_enum
91	IDLE = 0,
92	DMA_DATA1 = 1,
93	DMA_DATA2 = 2,
94	DMA_DATA3 = 3,
95	DMA_STALL = 4,
96	EQW_DATA1 = 5,
97	EQW_DATA2 = 6,
98	EQW_DATA3 = 7,
99	EQW_STALL = 8,
100	MDO_DATA1 = 9,
101	MDO_DATA2 = 10,
102	MDO_DATA3 = 11,
103	MDO_STALL = 12,
104	P16_DATA1 = 13,
105	P16_WAIT1 = 14,
106	P16_WAIT2 = 15,
107	P16_STALL = 16,
108	P64_DATA1 = 17,
109	P64_DATA2 = 18,
110	P64_DATA3 = 19,
111	P64_STALL = 20;
112
113	// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
114
115	// --------------------------------------------------------
116	// Clock/Reset Signals
117	// --------------------------------------------------------
118
119	input clk;
120	input rst_l;
121
122	// --------------------------------------------------------
123	// FSM Inputs
124	// --------------------------------------------------------
125
126	input icr_fifo_empty;
127	input icr_grnt;
128	input nxt_tag_avail;
129	input mwr_vld;
130	input eqwr_vld;
131	input mdo_vld;
132	input pio16_vld;
133	input pio64_vld;
134	input null_vld;
135	input mwr_err;
136	input eqwr_err;
137	input diu_dma_empty;
138	input diu_pio_empty;
139
140	// --------------------------------------------------------
141	// FSM Outputs
142	// --------------------------------------------------------
143
144	output diu_dma_bufmgmt_bsy;
145	output diu_eqw_bufmgmt_bsy;
146	output [1:0] diu_typ_sel;
147	output inc_dma_blk_addr;
148	output inc_pio_blk_addr;
149	output inc_eqw_blk_addr;
150	output inc_mdo_blk_addr;
151	output ld_diu_addr;
152	output inc_diu_row_ptr;
153	output dpath_sel;
154	output ld_diu_data;
155
156	// debug port
157	output [4:0] datactlfsm_state;
158
159	// idle checker port
160	output datactlfsm_idle;
161
162	// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
163
164	// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
165
166	// ******** Flops ********
167
168	reg [(STATE_NUM - 1):0] cur_state;
169	reg dpath_sel_s0;
170	reg dpath_sel_s1;
171	reg dpath_sel_s2;
172
173	// ******** Non-Flops ****
174
175	reg [(STATE_NUM - 1):0] nxt_state;
176	reg [4:0] enc_state;
177	reg [1:0] diu_typ_sel;
178
179	// ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
180
181	wire proc_mwr;
182	wire proc_p16;
183	wire proc_p64;
184	wire eqw_bufrel;
185	wire dmaw_bufrel;
186
187	// >>>>>>>>>>>>>>>>>>>>>>>>> 0-in Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
188
189	// 0in one_hot -var cur_state
190
191	///// STATE TRANSITION CHECKER //////////////////////////////////////////////
192
193	// ----- IDLE ---------------------------------------------------------------
194
195	/* 0in state
196	-var cur_state
197	-val (21'b1 << IDLE)
198	-next (21'b1 << IDLE)
199	(21'b1 << DMA_DATA1)
200	(21'b1 << EQW_DATA1)
201	(21'b1 << MDO_DATA1)
202	(21'b1 << P16_DATA1)
203	(21'b1 << P64_DATA1)
204	-match_by_cycle
205	*/
206
207	// ----- DMA ----------------------------------------------------------------
208
209	/* 0in state
210	-var cur_state
211	-val (21'b1 << DMA_DATA1)
212	-next (21'b1 << DMA_DATA2)
213	-match_by_cycle
214	*/
215
216	/* 0in state
217	-var cur_state
218	-val (21'b1 << DMA_DATA2)
219	-next (21'b1 << DMA_DATA3)
220	(21'b1 << DMA_STALL)
221	-match_by_cycle
222	*/
223
224	/* 0in state
225	-var cur_state
226	-val (21'b1 << DMA_DATA3)
227	-next (21'b1 << IDLE)
228	-match_by_cycle
229	*/
230
231	/* 0in state
232	-var cur_state
233	-val (21'b1 << DMA_STALL)
234	-next (21'b1 << DMA_DATA3)
235	(21'b1 << DMA_STALL)
236	-match_by_cycle
237	*/
238
239	// ----- EQW ----------------------------------------------------------------
240
241	/* 0in state
242	-var cur_state
243	-val (21'b1 << EQW_DATA1)
244	-next (21'b1 << EQW_DATA2)
245	-match_by_cycle
246	*/
247
248	/* 0in state
249	-var cur_state
250	-val (21'b1 << EQW_DATA2)
251	-next (21'b1 << EQW_DATA3)
252	(21'b1 << EQW_STALL)
253	-match_by_cycle
254	*/
255
256	/* 0in state
257	-var cur_state
258	-val (21'b1 << EQW_DATA3)
259	-next (21'b1 << IDLE)
260	-match_by_cycle
261	*/
262
263	/* 0in state
264	-var cur_state
265	-val (21'b1 << EQW_STALL)
266	-next (21'b1 << EQW_DATA3)
267	(21'b1 << EQW_STALL)
268	-match_by_cycle
269	*/
270
271	// ----- MDO ----------------------------------------------------------------
272
273	/* 0in state
274	-var cur_state
275	-val (21'b1 << MDO_DATA1)
276	-next (21'b1 << MDO_DATA2)
277	-match_by_cycle
278	*/
279
280	/* 0in state
281	-var cur_state
282	-val (21'b1 << MDO_DATA2)
283	-next (21'b1 << MDO_DATA3)
284	(21'b1 << MDO_STALL)
285	-match_by_cycle
286	*/
287
288	/* 0in state
289	-var cur_state
290	-val (21'b1 << MDO_DATA3)
291	-next (21'b1 << IDLE)
292	-match_by_cycle
293	*/
294
295	/* 0in state
296	-var cur_state
297	-val (21'b1 << MDO_STALL)
298	-next (21'b1 << MDO_DATA3)
299	(21'b1 << MDO_STALL)
300	-match_by_cycle
301	*/
302
303	// ----- P16 ----------------------------------------------------------------
304
305	/* 0in state
306	-var cur_state
307	-val (21'b1 << P16_DATA1)
308	-next (21'b1 << P16_WAIT1)
309	-match_by_cycle
310	*/
311
312	/* 0in state
313	-var cur_state
314	-val (21'b1 << P16_WAIT1)
315	-next (21'b1 << P16_WAIT2)
316	(21'b1 << P16_STALL)
317	-match_by_cycle
318	*/
319
320	/* 0in state
321	-var cur_state
322	-val (21'b1 << P16_WAIT2)
323	-next (21'b1 << IDLE)
324	-match_by_cycle
325	*/
326
327	/* 0in state
328	-var cur_state
329	-val (21'b1 << P16_STALL)
330	-next (21'b1 << P16_WAIT2)
331	(21'b1 << P16_STALL)
332	-match_by_cycle
333	*/
334
335	// ----- P64 ----------------------------------------------------------------
336
337	/* 0in state
338	-var cur_state
339	-val (21'b1 << P64_DATA1)
340	-next (21'b1 << P64_DATA2)
341	-match_by_cycle
342	*/
343
344	/* 0in state
345	-var cur_state
346	-val (21'b1 << P64_DATA2)
347	-next (21'b1 << P64_DATA3)
348	(21'b1 << P64_STALL)
349	-match_by_cycle
350	*/
351
352	/* 0in state
353	-var cur_state
354	-val (21'b1 << P64_DATA3)
355	-next (21'b1 << IDLE)
356	-match_by_cycle
357	*/
358
359	/* 0in state
360	-var cur_state
361	-val (21'b1 << P64_STALL)
362	-next (21'b1 << P64_DATA3)
363	(21'b1 << P64_STALL)
364	-match_by_cycle
365	*/
366
367	// >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
368
369	// --------------------------------------------------------
370	// IDLE Checker
371	// --------------------------------------------------------
372
373	assign datactlfsm_idle = cur_state[IDLE];
374
375	// --------------------------------------------------------
376	// Debug Port Logic
377	// --------------------------------------------------------
378
379	// encode one-hot current_state vector for debug port
380	always @(cur_state[(STATE_NUM - 1):1])
381	begin
382	enc_state[0] = (cur_state[1] \| cur_state[3] \| cur_state[5] \|
383	cur_state[7] \| cur_state[9] \| cur_state[11] \|
384	cur_state[13] \| cur_state[15] \| cur_state[17] \|
385	cur_state[19]);
386
387	enc_state[1] = (cur_state[2] \| cur_state[3] \| cur_state[6] \|
388	cur_state[7] \| cur_state[10] \| cur_state[11] \|
389	cur_state[14] \| cur_state[15] \| cur_state[18] \|
390	cur_state[19]);
391
392	enc_state[2] = (cur_state[4] \| cur_state[5] \| cur_state[6] \|
393	cur_state[7] \| cur_state[12] \| cur_state[13] \|
394	cur_state[14] \| cur_state[15] \| cur_state[20]);
395
396	enc_state[3] = (cur_state[8] \| cur_state[9] \| cur_state[10] \|
397	cur_state[11] \| cur_state[12] \| cur_state[13] \|
398	cur_state[14] \| cur_state[15]);
399
400	enc_state[4] = (cur_state[16] \| cur_state[17] \| cur_state[18] \|
401	cur_state[19] \| cur_state[20]);
402
403	end
404
405	// output datactlfsm debug bus
406	assign datactlfsm_state = enc_state;
407
408	// --------------------------------------------------------
409	// FSM Control Decode
410	// --------------------------------------------------------
411
412	assign proc_mwr = mwr_vld & ~diu_dma_empty;
413	assign proc_p16 = pio16_vld & ~diu_pio_empty;
414	assign proc_p64 = pio64_vld & ~diu_pio_empty;
415
416	// --------------------------------------------------------
417	// FSM Next State
418	// --------------------------------------------------------
419
420	// next state assignment
421	always @(cur_state or icr_grnt or icr_fifo_empty or proc_p16 or proc_p64 or
422	proc_mwr or eqwr_vld or mdo_vld or nxt_tag_avail)
423	begin
424
425	// initialization
426	nxt_state = {STATE_NUM{1'b0}};
427
428	case (1'b1) // synopsys parallel_case
429
430	// 0in < case -full
431
432	///////////////////////////////////////////////////////////////////////
433
434	// IDLE State
435	cur_state[IDLE] :
436	casez ({icr_fifo_empty, proc_mwr, eqwr_vld, mdo_vld, proc_p16,
437	proc_p64})
438
439	// 0in < case -parallel -full
440
441	6'b1_zzzzz,
442	6'b0_00000 : nxt_state[IDLE] = 1'b1;
443	6'b0_10000 : nxt_state[DMA_DATA1] = 1'b1;
444	6'b0_01000 : nxt_state[EQW_DATA1] = 1'b1;
445	6'b0_00100 : nxt_state[MDO_DATA1] = 1'b1;
446	6'b0_00010 : nxt_state[P16_DATA1] = 1'b1;
447	6'b0_00001 : nxt_state[P64_DATA1] = 1'b1;
448	endcase
449
450	///////////////////////////////////////////////////////////////////////
451
452	// ---------- DMA WR ----------------------------------------
453
454	// DMA_DATA1 State
455	cur_state[DMA_DATA1] :
456	nxt_state[DMA_DATA2] = 1'b1;
457
458	// DMA_DATA2 State
459	cur_state[DMA_DATA2] :
460	casez ({icr_grnt, nxt_tag_avail})
461
462	// 0in < case -parallel -full
463
464	2'b0z,
465	2'b10 : nxt_state[DMA_STALL] = 1'b1;
466	2'b11 : nxt_state[DMA_DATA3] = 1'b1;
467	endcase
468
469	// DMA_DATA3 State
470	cur_state[DMA_DATA3] :
471	nxt_state[IDLE] = 1'b1;
472
473	// DMA_STALL State
474	cur_state[DMA_STALL] :
475	casez ({icr_grnt, nxt_tag_avail})
476
477	// 0in < case -parallel -full
478
479	2'b0z,
480	2'b10 : nxt_state[DMA_STALL] = 1'b1;
481	2'b11 : nxt_state[DMA_DATA3] = 1'b1;
482	endcase
483
484	///////////////////////////////////////////////////////////////////////
485
486	// ---------- EQ WR -----------------------------------------
487
488	// EQW_DATA1 State
489	cur_state[EQW_DATA1] :
490	nxt_state[EQW_DATA2] = 1'b1;
491
492	// EQW_DATA2 State
493	cur_state[EQW_DATA2] :
494	casez ({icr_grnt, nxt_tag_avail})
495
496	// 0in < case -parallel -full
497
498	2'b0z,
499	2'b10 : nxt_state[EQW_STALL] = 1'b1;
500	2'b11 : nxt_state[EQW_DATA3] = 1'b1;
501	endcase
502
503	// EQW_DATA3 State
504	cur_state[EQW_DATA3] :
505	nxt_state[IDLE] = 1'b1;
506
507	// EQW_STALL State
508	cur_state[EQW_STALL] :
509	casez ({icr_grnt, nxt_tag_avail})
510
511	// 0in < case -parallel -full
512
513	2'b0z,
514	2'b10 : nxt_state[EQW_STALL] = 1'b1;
515	2'b11 : nxt_state[EQW_DATA3] = 1'b1;
516	endcase
517
518	///////////////////////////////////////////////////////////////////////
519
520	// ---------- MDO -------------------------------------------
521
522	// MDO_DATA1 State
523	cur_state[MDO_DATA1] :
524	nxt_state[MDO_DATA2] = 1'b1;
525
526	// MDO_DATA2 State
527	cur_state[MDO_DATA2] :
528	casez ({icr_grnt, nxt_tag_avail})
529
530	// 0in < case -parallel -full
531
532	2'b0z,
533	2'b10 : nxt_state[MDO_STALL] = 1'b1;
534	2'b11 : nxt_state[MDO_DATA3] = 1'b1;
535	endcase
536
537	// MDO_DATA3 State
538	cur_state[MDO_DATA3] :
539	nxt_state[IDLE] = 1'b1;
540
541	// MDO_STALL State
542	cur_state[MDO_STALL] :
543	casez ({icr_grnt, nxt_tag_avail})
544
545	// 0in < case -parallel -full
546
547	2'b0z,
548	2'b10 : nxt_state[MDO_STALL] = 1'b1;
549	2'b11 : nxt_state[MDO_DATA3] = 1'b1;
550	endcase
551
552	///////////////////////////////////////////////////////////////////////
553
554	// ---------- PIO 16 CPL ------------------------------------
555
556	// P16_DATA1 State
557	cur_state[P16_DATA1] :
558	nxt_state[P16_WAIT1] = 1'b1;
559
560	// P16_WAIT1 State
561	cur_state[P16_WAIT1] :
562	if (icr_grnt)
563	nxt_state[P16_WAIT2] = 1'b1;
564	else
565	nxt_state[P16_STALL] = 1'b1;
566
567	// P16_WAIT2 State
568	cur_state[P16_WAIT2] :
569	nxt_state[IDLE] = 1'b1;
570
571	// P16_STALL State
572	cur_state[P16_STALL] :
573	if (icr_grnt)
574	nxt_state[P16_WAIT2] = 1'b1;
575	else
576	nxt_state[P16_STALL] = 1'b1;
577
578	///////////////////////////////////////////////////////////////////////
579
580	// ---------- PIO 64 CPL ------------------------------------
581
582	// P64_DATA1 State
583	cur_state[P64_DATA1] :
584	nxt_state[P64_DATA2] = 1'b1;
585
586	// P64_DATA2 State
587	cur_state[P64_DATA2] :
588	if (icr_grnt)
589	nxt_state[P64_DATA3] = 1'b1;
590	else
591	nxt_state[P64_STALL] = 1'b1;
592
593	// P64_DATA3 State
594	cur_state[P64_DATA3] :
595	nxt_state[IDLE] = 1'b1;
596
597	// P64_STALL State
598	cur_state[P64_STALL] :
599	if (icr_grnt)
600	nxt_state[P64_DATA3] = 1'b1;
601	else
602	nxt_state[P64_STALL] = 1'b1;
603
604	///////////////////////////////////////////////////////////////////////
605
606	endcase
607	end
608
609	// --------------------------------------------------------
610	// FSM Current State
611	// --------------------------------------------------------
612
613	// summit state_vector cur_state enum cur_enum
614
615	// current state assignment
616	always @(posedge clk)
617	if (~rst_l)
618	begin
619	cur_state <= {STATE_NUM{1'b0}};
620	cur_state[IDLE] <= 1'b1;
621	end
622	else
623	cur_state <= nxt_state;
624
625	// --------------------------------------------------------
626	// FSM Output Generation
627	// --------------------------------------------------------
628
629	// ----- data path control --------------------------------------------------
630
631	// generate data path select
632	always @(posedge clk)
633	if (~rst_l)
634	begin
635	dpath_sel_s0 <= 1'b0;
636	dpath_sel_s1 <= 1'b0;
637	dpath_sel_s2 <= 1'b0;
638	end
639	// else if (nxt_state[EQW_DATA3] \| nxt_state[MDO_DATA3]) // BP n2 10-25-04, MDO is now 1 data beat
640	else if (nxt_state[EQW_DATA3] )
641	begin
642	dpath_sel_s0 <= 1'b1;
643	dpath_sel_s1 <= 1'b1;
644	dpath_sel_s2 <= 1'b1;
645	end
646	else
647	begin
648	dpath_sel_s0 <= 1'b0;
649	dpath_sel_s1 <= dpath_sel_s0;
650	dpath_sel_s2 <= dpath_sel_s1;
651	end
652
653	// output data path select
654	assign dpath_sel = dpath_sel_s2;
655
656	// generate data pipe load
657	assign ld_diu_data = ~(cur_state[MDO_STALL] \| cur_state[EQW_STALL] \|
658	cur_state[DMA_STALL] \| cur_state[P64_STALL] \|
659	cur_state[P16_STALL]);
660
661	// ----- diu buffer management control --------------------------------------
662
663	// block address segment select
664	always @(nxt_state)
665	begin
666	if (nxt_state[DMA_DATA1])
667	diu_typ_sel = 2'b00;
668	else if (nxt_state[P16_DATA1] \| nxt_state[P64_DATA1])
669	diu_typ_sel = 2'b01;
670	else if (nxt_state[EQW_DATA1])
671	diu_typ_sel = 2'b10;
672	else if (nxt_state[MDO_DATA1])
673	diu_typ_sel = 2'b11;
674	else
675	diu_typ_sel = 2'b00;
676	end
677
678	// dma buffer busy
679	assign diu_dma_bufmgmt_bsy = (nxt_state[DMA_DATA1] \| cur_state[DMA_DATA1] \|
680	cur_state[DMA_DATA2] \| cur_state[DMA_DATA3]);
681
682	// eqw buffer busy
683	assign diu_eqw_bufmgmt_bsy = nxt_state[EQW_DATA1];
684
685	// buffer release for dmaw_err, eqw_err & null
686	assign dmaw_bufrel = ~icr_fifo_empty & ~diu_dma_bufmgmt_bsy & mwr_err;
687	assign eqw_bufrel = (~icr_fifo_empty & ~diu_eqw_bufmgmt_bsy &
688	(eqwr_err \| null_vld));
689
690	// buffer block address increment
691	assign inc_dma_blk_addr = nxt_state[DMA_DATA3] \| dmaw_bufrel;
692	assign inc_eqw_blk_addr = nxt_state[EQW_DATA3] \| eqw_bufrel;
693	assign inc_mdo_blk_addr = nxt_state[MDO_DATA3];
694	assign inc_pio_blk_addr = nxt_state[P16_WAIT2] \| nxt_state[P64_DATA3];
695
696	// buffer read address load
697	assign ld_diu_addr = (nxt_state[DMA_DATA1] \| nxt_state[EQW_DATA1] \|
698	nxt_state[MDO_DATA1] \| nxt_state[P16_DATA1] \|
699	nxt_state[P64_DATA1]);
700
701	// buffer row address increment
702	assign inc_diu_row_ptr = (cur_state[DMA_DATA1] \| cur_state[DMA_DATA3] \|
703	cur_state[P64_DATA1] \| cur_state[P64_DATA3] \|
704	((cur_state[DMA_DATA2] \| cur_state[DMA_STALL]) &
705	nxt_state[DMA_DATA3]) \|
706	((cur_state[P64_DATA2] \| cur_state[P64_STALL]) &
707	nxt_state[P64_DATA3]));
708
709	endmodule // dmu_clu_ctm_datactlfsm