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// OpenSPARC T2 Processor File: dmu_clu_ctm_datactlfsm.v
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// ========== Copyright Header End ============================================
module dmu_clu_ctm_datactlfsm
// synopsys sync_set_reset "rst_l"
// >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------
// --------------------------------------------------------
parameter STATE_NUM = 21;
// --------------------------------------------------------
// --------------------------------------------------------
parameter // summit enum cur_enum
// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
output diu_dma_bufmgmt_bsy;
output diu_eqw_bufmgmt_bsy;
output [1:0] diu_typ_sel;
output [4:0] datactlfsm_state;
// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// ********** Flops **********
reg [(STATE_NUM - 1):0] cur_state;
// ********** Non-Flops ******
reg [(STATE_NUM - 1):0] nxt_state;
// ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// >>>>>>>>>>>>>>>>>>>>>>>>> 0-in Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// 0in one_hot -var cur_state
///// STATE TRANSITION CHECKER //////////////////////////////////////////////
// ----- IDLE ---------------------------------------------------------------
// ----- DMA ----------------------------------------------------------------
-val (21'b1 << DMA_DATA1)
-next (21'b1 << DMA_DATA2)
-val (21'b1 << DMA_DATA2)
-next (21'b1 << DMA_DATA3)
-val (21'b1 << DMA_DATA3)
-val (21'b1 << DMA_STALL)
-next (21'b1 << DMA_DATA3)
// ----- EQW ----------------------------------------------------------------
-val (21'b1 << EQW_DATA1)
-next (21'b1 << EQW_DATA2)
-val (21'b1 << EQW_DATA2)
-next (21'b1 << EQW_DATA3)
-val (21'b1 << EQW_DATA3)
-val (21'b1 << EQW_STALL)
-next (21'b1 << EQW_DATA3)
// ----- MDO ----------------------------------------------------------------
-val (21'b1 << MDO_DATA1)
-next (21'b1 << MDO_DATA2)
-val (21'b1 << MDO_DATA2)
-next (21'b1 << MDO_DATA3)
-val (21'b1 << MDO_DATA3)
-val (21'b1 << MDO_STALL)
-next (21'b1 << MDO_DATA3)
// ----- P16 ----------------------------------------------------------------
-val (21'b1 << P16_DATA1)
-next (21'b1 << P16_WAIT1)
-val (21'b1 << P16_WAIT1)
-next (21'b1 << P16_WAIT2)
-val (21'b1 << P16_WAIT2)
-val (21'b1 << P16_STALL)
-next (21'b1 << P16_WAIT2)
// ----- P64 ----------------------------------------------------------------
-val (21'b1 << P64_DATA1)
-next (21'b1 << P64_DATA2)
-val (21'b1 << P64_DATA2)
-next (21'b1 << P64_DATA3)
-val (21'b1 << P64_DATA3)
-val (21'b1 << P64_STALL)
-next (21'b1 << P64_DATA3)
// >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------
// --------------------------------------------------------
assign datactlfsm_idle = cur_state[IDLE];
// --------------------------------------------------------
// --------------------------------------------------------
// encode one-hot current_state vector for debug port
always @(cur_state[(STATE_NUM - 1):1])
enc_state[0] = (cur_state[1] | cur_state[3] | cur_state[5] |
cur_state[7] | cur_state[9] | cur_state[11] |
cur_state[13] | cur_state[15] | cur_state[17] |
enc_state[1] = (cur_state[2] | cur_state[3] | cur_state[6] |
cur_state[7] | cur_state[10] | cur_state[11] |
cur_state[14] | cur_state[15] | cur_state[18] |
enc_state[2] = (cur_state[4] | cur_state[5] | cur_state[6] |
cur_state[7] | cur_state[12] | cur_state[13] |
cur_state[14] | cur_state[15] | cur_state[20]);
enc_state[3] = (cur_state[8] | cur_state[9] | cur_state[10] |
cur_state[11] | cur_state[12] | cur_state[13] |
cur_state[14] | cur_state[15]);
enc_state[4] = (cur_state[16] | cur_state[17] | cur_state[18] |
cur_state[19] | cur_state[20]);
// output datactlfsm debug bus
assign datactlfsm_state = enc_state;
// --------------------------------------------------------
// --------------------------------------------------------
assign proc_mwr = mwr_vld & ~diu_dma_empty;
assign proc_p16 = pio16_vld & ~diu_pio_empty;
assign proc_p64 = pio64_vld & ~diu_pio_empty;
// --------------------------------------------------------
// --------------------------------------------------------
always @(cur_state or icr_grnt or icr_fifo_empty or proc_p16 or proc_p64 or
proc_mwr or eqwr_vld or mdo_vld or nxt_tag_avail)
nxt_state = {STATE_NUM{1'b0}};
case (1'b1) // synopsys parallel_case
///////////////////////////////////////////////////////////////////////
casez ({icr_fifo_empty, proc_mwr, eqwr_vld, mdo_vld, proc_p16,
// 0in < case -parallel -full
6'b0_00000 : nxt_state[IDLE] = 1'b1;
6'b0_10000 : nxt_state[DMA_DATA1] = 1'b1;
6'b0_01000 : nxt_state[EQW_DATA1] = 1'b1;
6'b0_00100 : nxt_state[MDO_DATA1] = 1'b1;
6'b0_00010 : nxt_state[P16_DATA1] = 1'b1;
6'b0_00001 : nxt_state[P64_DATA1] = 1'b1;
///////////////////////////////////////////////////////////////////////
// ---------- DMA WR ----------------------------------------
nxt_state[DMA_DATA2] = 1'b1;
casez ({icr_grnt, nxt_tag_avail})
// 0in < case -parallel -full
2'b10 : nxt_state[DMA_STALL] = 1'b1;
2'b11 : nxt_state[DMA_DATA3] = 1'b1;
casez ({icr_grnt, nxt_tag_avail})
// 0in < case -parallel -full
2'b10 : nxt_state[DMA_STALL] = 1'b1;
2'b11 : nxt_state[DMA_DATA3] = 1'b1;
///////////////////////////////////////////////////////////////////////
// ---------- EQ WR -----------------------------------------
nxt_state[EQW_DATA2] = 1'b1;
casez ({icr_grnt, nxt_tag_avail})
// 0in < case -parallel -full
2'b10 : nxt_state[EQW_STALL] = 1'b1;
2'b11 : nxt_state[EQW_DATA3] = 1'b1;
casez ({icr_grnt, nxt_tag_avail})
// 0in < case -parallel -full
2'b10 : nxt_state[EQW_STALL] = 1'b1;
2'b11 : nxt_state[EQW_DATA3] = 1'b1;
///////////////////////////////////////////////////////////////////////
// ---------- MDO -------------------------------------------
nxt_state[MDO_DATA2] = 1'b1;
casez ({icr_grnt, nxt_tag_avail})
// 0in < case -parallel -full
2'b10 : nxt_state[MDO_STALL] = 1'b1;
2'b11 : nxt_state[MDO_DATA3] = 1'b1;
casez ({icr_grnt, nxt_tag_avail})
// 0in < case -parallel -full
2'b10 : nxt_state[MDO_STALL] = 1'b1;
2'b11 : nxt_state[MDO_DATA3] = 1'b1;
///////////////////////////////////////////////////////////////////////
// ---------- PIO 16 CPL ------------------------------------
nxt_state[P16_WAIT1] = 1'b1;
nxt_state[P16_WAIT2] = 1'b1;
nxt_state[P16_STALL] = 1'b1;
nxt_state[P16_WAIT2] = 1'b1;
nxt_state[P16_STALL] = 1'b1;
///////////////////////////////////////////////////////////////////////
// ---------- PIO 64 CPL ------------------------------------
nxt_state[P64_DATA2] = 1'b1;
nxt_state[P64_DATA3] = 1'b1;
nxt_state[P64_STALL] = 1'b1;
nxt_state[P64_DATA3] = 1'b1;
nxt_state[P64_STALL] = 1'b1;
///////////////////////////////////////////////////////////////////////
// --------------------------------------------------------
// --------------------------------------------------------
// summit state_vector cur_state enum cur_enum
// current state assignment
cur_state <= {STATE_NUM{1'b0}};
// --------------------------------------------------------
// --------------------------------------------------------
// ----- data path control --------------------------------------------------
// generate data path select
// else if (nxt_state[EQW_DATA3] | nxt_state[MDO_DATA3]) // BP n2 10-25-04, MDO is now 1 data beat
else if (nxt_state[EQW_DATA3] )
dpath_sel_s1 <= dpath_sel_s0;
dpath_sel_s2 <= dpath_sel_s1;
// output data path select
assign dpath_sel = dpath_sel_s2;
// generate data pipe load
assign ld_diu_data = ~(cur_state[MDO_STALL] | cur_state[EQW_STALL] |
cur_state[DMA_STALL] | cur_state[P64_STALL] |
// ----- diu buffer management control --------------------------------------
// block address segment select
if (nxt_state[DMA_DATA1])
else if (nxt_state[P16_DATA1] | nxt_state[P64_DATA1])
else if (nxt_state[EQW_DATA1])
else if (nxt_state[MDO_DATA1])
assign diu_dma_bufmgmt_bsy = (nxt_state[DMA_DATA1] | cur_state[DMA_DATA1] |
cur_state[DMA_DATA2] | cur_state[DMA_DATA3]);
assign diu_eqw_bufmgmt_bsy = nxt_state[EQW_DATA1];
// buffer release for dmaw_err, eqw_err & null
assign dmaw_bufrel = ~icr_fifo_empty & ~diu_dma_bufmgmt_bsy & mwr_err;
assign eqw_bufrel = (~icr_fifo_empty & ~diu_eqw_bufmgmt_bsy &
// buffer block address increment
assign inc_dma_blk_addr = nxt_state[DMA_DATA3] | dmaw_bufrel;
assign inc_eqw_blk_addr = nxt_state[EQW_DATA3] | eqw_bufrel;
assign inc_mdo_blk_addr = nxt_state[MDO_DATA3];
assign inc_pio_blk_addr = nxt_state[P16_WAIT2] | nxt_state[P64_DATA3];
// buffer read address load
assign ld_diu_addr = (nxt_state[DMA_DATA1] | nxt_state[EQW_DATA1] |
nxt_state[MDO_DATA1] | nxt_state[P16_DATA1] |
// buffer row address increment
assign inc_diu_row_ptr = (cur_state[DMA_DATA1] | cur_state[DMA_DATA3] |
cur_state[P64_DATA1] | cur_state[P64_DATA3] |
((cur_state[DMA_DATA2] | cur_state[DMA_STALL]) &
((cur_state[P64_DATA2] | cur_state[P64_STALL]) &
endmodule // dmu_clu_ctm_datactlfsm