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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_ilu_isb.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_ilu_isb ( | |
36 | clk, | |
37 | rst_l, | |
38 | eil2isb_log, | |
39 | eil2isb_tag, | |
40 | eil2isb_low_addr, | |
41 | iil2isb_clr, | |
42 | iil2isb_tag, | |
43 | isb2iil_vld, | |
44 | isb2iil_low_addr, | |
45 | ||
46 | // debug | |
47 | low_dbg_sel_a, | |
48 | low_dbg_sel_b, | |
49 | isb_dbg_a, | |
50 | isb_dbg_b, | |
51 | ||
52 | // idle check | |
53 | isb_is_idle ); | |
54 | ||
55 | //synopsys sync_set_reset "my_rst_l" | |
56 | ||
57 | // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
58 | ||
59 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< | |
60 | ||
61 | input clk; // input clock | |
62 | input rst_l; // input reset | |
63 | ||
64 | input eil2isb_log; // turn the eil2isb_tag associated valid bit on | |
65 | input [4:0] eil2isb_tag; | |
66 | input [3:2] eil2isb_low_addr; | |
67 | ||
68 | input iil2isb_clr; // turn the iil2isb_tag associated valid bit off | |
69 | input [4:0] iil2isb_tag; | |
70 | output isb2iil_vld; | |
71 | output [3:2] isb2iil_low_addr; | |
72 | ||
73 | output isb_is_idle; | |
74 | ||
75 | //------------------------------------------------------------------------ | |
76 | // debug | |
77 | //------------------------------------------------------------------------ | |
78 | input [2:0] low_dbg_sel_a; | |
79 | input [2:0] low_dbg_sel_b; | |
80 | output [`FIRE_DBG_DATA_BITS] isb_dbg_a; | |
81 | output [`FIRE_DBG_DATA_BITS] isb_dbg_b; | |
82 | ||
83 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< | |
84 | ||
85 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
86 | reg [31:0] isb_pio_vld; // score board vector for non-posted outstanding PIOs | |
87 | reg [3:2] isb_pio_low_addr [0:31] ; | |
88 | ||
89 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
90 | ||
91 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
92 | reg [`FIRE_DBG_DATA_BITS] dbg_bus [0:1]; | |
93 | ||
94 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~ | |
95 | ||
96 | reg [`FIRE_DBG_DATA_BITS] nxt_dbg_bus [0:1]; | |
97 | reg [2:0] dbg_sel [0:1]; | |
98 | ||
99 | integer j; | |
100 | ||
101 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | |
102 | ||
103 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<< | |
104 | ||
105 | ||
106 | assign isb2iil_vld = isb_pio_vld[iil2isb_tag]; | |
107 | assign isb2iil_low_addr = isb_pio_low_addr[iil2isb_tag]; | |
108 | ||
109 | always @ (posedge clk) | |
110 | if (!rst_l) begin | |
111 | isb_pio_vld <= 32'b0; | |
112 | begin: addr_rst | |
113 | integer i; | |
114 | for (i = 0; i < 32; i = i + 1) begin | |
115 | isb_pio_low_addr[i] <= {2{1'b0}}; | |
116 | end | |
117 | end | |
118 | end | |
119 | else begin | |
120 | if (iil2isb_clr) isb_pio_vld[iil2isb_tag] <= 1'b0; | |
121 | if (eil2isb_log) begin | |
122 | isb_pio_vld[eil2isb_tag] <= 1'b1; | |
123 | isb_pio_low_addr[eil2isb_tag] <= eil2isb_low_addr; | |
124 | end | |
125 | end | |
126 | ||
127 | //--------------------------------------------------------------------- | |
128 | // idle check output - when there is no PIO transaction pending, it's idle | |
129 | //--------------------------------------------------------------------- | |
130 | assign isb_is_idle = ~(|isb_pio_vld); | |
131 | ||
132 | //--------------------------------------------------------------------- | |
133 | // debug | |
134 | //--------------------------------------------------------------------- | |
135 | ||
136 | always @ (low_dbg_sel_a or low_dbg_sel_b) begin | |
137 | dbg_sel[0] = low_dbg_sel_a; | |
138 | dbg_sel[1] = low_dbg_sel_b; | |
139 | end | |
140 | ||
141 | always @ (dbg_sel[0] or dbg_sel[1] or | |
142 | eil2isb_log or | |
143 | eil2isb_tag or | |
144 | iil2isb_clr or | |
145 | iil2isb_tag or | |
146 | isb2iil_vld or | |
147 | isb_pio_vld ) begin : dbg_out | |
148 | integer i; | |
149 | for (i = 0; i < 2; i = i + 1) begin | |
150 | case (dbg_sel[i]) // synopsys infer_mux | |
151 | 3'b000: nxt_dbg_bus[i] = {2'b0, eil2isb_log, eil2isb_tag}; | |
152 | 3'b001: nxt_dbg_bus[i] = {1'b0, iil2isb_clr, iil2isb_tag, isb2iil_vld}; | |
153 | 3'b010: nxt_dbg_bus[i] = isb_pio_vld[31:24]; | |
154 | 3'b011: nxt_dbg_bus[i] = isb_pio_vld[23:16]; | |
155 | 3'b100: nxt_dbg_bus[i] = isb_pio_vld[15:8]; | |
156 | 3'b101: nxt_dbg_bus[i] = isb_pio_vld[7:0]; | |
157 | 3'b110: nxt_dbg_bus[i] = 8'b0; | |
158 | 3'b111: nxt_dbg_bus[i] = 8'b0; | |
159 | endcase | |
160 | end | |
161 | end | |
162 | ||
163 | assign isb_dbg_a = dbg_bus[0]; | |
164 | assign isb_dbg_b = dbg_bus[1]; | |
165 | ||
166 | always @ (posedge clk) | |
167 | if(~rst_l) begin : dbg_rst | |
168 | integer i; | |
169 | for (i = 0; i < 2; i = i + 1) begin | |
170 | dbg_bus[i] <= {8{1'b0}}; | |
171 | end | |
172 | end | |
173 | else begin | |
174 | for (j = 0; j < 2; j = j + 1) begin | |
175 | dbg_bus[j] <= nxt_dbg_bus[j]; | |
176 | end | |
177 | end | |
178 | ||
179 | ||
180 | ||
181 | ||
182 | endmodule // dmu_ilu_isb | |
183 |