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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: dmu_imu_eqs_csr_eq_base_address_entry.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module dmu_imu_eqs_csr_eq_base_address_entry | |
36 | ( | |
37 | // synopsys translate_off | |
38 | omni_ld, | |
39 | omni_data, | |
40 | // synopsys translate_on | |
41 | clk, | |
42 | rst_l, | |
43 | w_ld, | |
44 | csrbus_wr_data, | |
45 | eq_base_address_csrbus_read_data | |
46 | ); | |
47 | ||
48 | //==================================================================== | |
49 | // Polarity declarations | |
50 | //==================================================================== | |
51 | // synopsys translate_off | |
52 | input omni_ld; // Omni load | |
53 | // vlint flag_input_port_not_connected off | |
54 | input [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH - 1:0] omni_data; | |
55 | // Omni write data | |
56 | // synopsys translate_on | |
57 | // vlint flag_input_port_not_connected on | |
58 | input clk; // Clock signal | |
59 | input rst_l; // Reset signal | |
60 | input w_ld; // SW load | |
61 | // vlint flag_input_port_not_connected off | |
62 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
63 | // vlint flag_input_port_not_connected on | |
64 | output [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH-1:0] eq_base_address_csrbus_read_data; | |
65 | // SW read data | |
66 | ||
67 | //==================================================================== | |
68 | // Type declarations | |
69 | //==================================================================== | |
70 | // synopsys translate_off | |
71 | wire omni_ld; // Omni load | |
72 | // vlint flag_dangling_net_within_module off | |
73 | // vlint flag_net_has_no_load off | |
74 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH - 1:0] omni_data; | |
75 | // Omni write data | |
76 | // synopsys translate_on | |
77 | // vlint flag_dangling_net_within_module on | |
78 | // vlint flag_net_has_no_load on | |
79 | wire clk; // Clock signal | |
80 | wire rst_l; // Reset signal | |
81 | wire w_ld; // SW load | |
82 | // vlint flag_dangling_net_within_module off | |
83 | // vlint flag_net_has_no_load off | |
84 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data | |
85 | // vlint flag_dangling_net_within_module on | |
86 | // vlint flag_net_has_no_load on | |
87 | wire [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH-1:0] eq_base_address_csrbus_read_data; | |
88 | // SW read data | |
89 | ||
90 | //==================================================================== | |
91 | // Logic | |
92 | //==================================================================== | |
93 | ||
94 | //----- Reset values | |
95 | // verilint 531 off | |
96 | wire [44:0] reset_address = 45'h0; | |
97 | // verilint 531 on | |
98 | ||
99 | //----- Active high reset wires | |
100 | wire rst_l_active_high = ~rst_l; | |
101 | ||
102 | //==================================================== | |
103 | // Instantiation of flops | |
104 | //==================================================== | |
105 | ||
106 | assign eq_base_address_csrbus_read_data[0] = 1'b0; // bit 0 | |
107 | assign eq_base_address_csrbus_read_data[1] = 1'b0; // bit 1 | |
108 | assign eq_base_address_csrbus_read_data[2] = 1'b0; // bit 2 | |
109 | assign eq_base_address_csrbus_read_data[3] = 1'b0; // bit 3 | |
110 | assign eq_base_address_csrbus_read_data[4] = 1'b0; // bit 4 | |
111 | assign eq_base_address_csrbus_read_data[5] = 1'b0; // bit 5 | |
112 | assign eq_base_address_csrbus_read_data[6] = 1'b0; // bit 6 | |
113 | assign eq_base_address_csrbus_read_data[7] = 1'b0; // bit 7 | |
114 | assign eq_base_address_csrbus_read_data[8] = 1'b0; // bit 8 | |
115 | assign eq_base_address_csrbus_read_data[9] = 1'b0; // bit 9 | |
116 | assign eq_base_address_csrbus_read_data[10] = 1'b0; // bit 10 | |
117 | assign eq_base_address_csrbus_read_data[11] = 1'b0; // bit 11 | |
118 | assign eq_base_address_csrbus_read_data[12] = 1'b0; // bit 12 | |
119 | assign eq_base_address_csrbus_read_data[13] = 1'b0; // bit 13 | |
120 | assign eq_base_address_csrbus_read_data[14] = 1'b0; // bit 14 | |
121 | assign eq_base_address_csrbus_read_data[15] = 1'b0; // bit 15 | |
122 | assign eq_base_address_csrbus_read_data[16] = 1'b0; // bit 16 | |
123 | assign eq_base_address_csrbus_read_data[17] = 1'b0; // bit 17 | |
124 | assign eq_base_address_csrbus_read_data[18] = 1'b0; // bit 18 | |
125 | // bit 19 | |
126 | csr_sw csr_sw_19 | |
127 | ( | |
128 | // synopsys translate_off | |
129 | .omni_ld (omni_ld), | |
130 | .omni_data (omni_data[19]), | |
131 | .omni_rw_alias (1'b1), | |
132 | .omni_rw1c_alias (1'b0), | |
133 | .omni_rw1s_alias (1'b0), | |
134 | // synopsys translate_on | |
135 | .rst (rst_l_active_high), | |
136 | .rst_val (reset_address[0]), | |
137 | .csr_ld (w_ld), | |
138 | .csr_data (csrbus_wr_data[19]), | |
139 | .rw_alias (1'b1), | |
140 | .rw1c_alias (1'b0), | |
141 | .rw1s_alias (1'b0), | |
142 | .hw_ld (1'b0), | |
143 | .hw_data (1'b0), | |
144 | .cp (clk), | |
145 | .q (eq_base_address_csrbus_read_data[19]) | |
146 | ); | |
147 | ||
148 | // bit 20 | |
149 | csr_sw csr_sw_20 | |
150 | ( | |
151 | // synopsys translate_off | |
152 | .omni_ld (omni_ld), | |
153 | .omni_data (omni_data[20]), | |
154 | .omni_rw_alias (1'b1), | |
155 | .omni_rw1c_alias (1'b0), | |
156 | .omni_rw1s_alias (1'b0), | |
157 | // synopsys translate_on | |
158 | .rst (rst_l_active_high), | |
159 | .rst_val (reset_address[1]), | |
160 | .csr_ld (w_ld), | |
161 | .csr_data (csrbus_wr_data[20]), | |
162 | .rw_alias (1'b1), | |
163 | .rw1c_alias (1'b0), | |
164 | .rw1s_alias (1'b0), | |
165 | .hw_ld (1'b0), | |
166 | .hw_data (1'b0), | |
167 | .cp (clk), | |
168 | .q (eq_base_address_csrbus_read_data[20]) | |
169 | ); | |
170 | ||
171 | // bit 21 | |
172 | csr_sw csr_sw_21 | |
173 | ( | |
174 | // synopsys translate_off | |
175 | .omni_ld (omni_ld), | |
176 | .omni_data (omni_data[21]), | |
177 | .omni_rw_alias (1'b1), | |
178 | .omni_rw1c_alias (1'b0), | |
179 | .omni_rw1s_alias (1'b0), | |
180 | // synopsys translate_on | |
181 | .rst (rst_l_active_high), | |
182 | .rst_val (reset_address[2]), | |
183 | .csr_ld (w_ld), | |
184 | .csr_data (csrbus_wr_data[21]), | |
185 | .rw_alias (1'b1), | |
186 | .rw1c_alias (1'b0), | |
187 | .rw1s_alias (1'b0), | |
188 | .hw_ld (1'b0), | |
189 | .hw_data (1'b0), | |
190 | .cp (clk), | |
191 | .q (eq_base_address_csrbus_read_data[21]) | |
192 | ); | |
193 | ||
194 | // bit 22 | |
195 | csr_sw csr_sw_22 | |
196 | ( | |
197 | // synopsys translate_off | |
198 | .omni_ld (omni_ld), | |
199 | .omni_data (omni_data[22]), | |
200 | .omni_rw_alias (1'b1), | |
201 | .omni_rw1c_alias (1'b0), | |
202 | .omni_rw1s_alias (1'b0), | |
203 | // synopsys translate_on | |
204 | .rst (rst_l_active_high), | |
205 | .rst_val (reset_address[3]), | |
206 | .csr_ld (w_ld), | |
207 | .csr_data (csrbus_wr_data[22]), | |
208 | .rw_alias (1'b1), | |
209 | .rw1c_alias (1'b0), | |
210 | .rw1s_alias (1'b0), | |
211 | .hw_ld (1'b0), | |
212 | .hw_data (1'b0), | |
213 | .cp (clk), | |
214 | .q (eq_base_address_csrbus_read_data[22]) | |
215 | ); | |
216 | ||
217 | // bit 23 | |
218 | csr_sw csr_sw_23 | |
219 | ( | |
220 | // synopsys translate_off | |
221 | .omni_ld (omni_ld), | |
222 | .omni_data (omni_data[23]), | |
223 | .omni_rw_alias (1'b1), | |
224 | .omni_rw1c_alias (1'b0), | |
225 | .omni_rw1s_alias (1'b0), | |
226 | // synopsys translate_on | |
227 | .rst (rst_l_active_high), | |
228 | .rst_val (reset_address[4]), | |
229 | .csr_ld (w_ld), | |
230 | .csr_data (csrbus_wr_data[23]), | |
231 | .rw_alias (1'b1), | |
232 | .rw1c_alias (1'b0), | |
233 | .rw1s_alias (1'b0), | |
234 | .hw_ld (1'b0), | |
235 | .hw_data (1'b0), | |
236 | .cp (clk), | |
237 | .q (eq_base_address_csrbus_read_data[23]) | |
238 | ); | |
239 | ||
240 | // bit 24 | |
241 | csr_sw csr_sw_24 | |
242 | ( | |
243 | // synopsys translate_off | |
244 | .omni_ld (omni_ld), | |
245 | .omni_data (omni_data[24]), | |
246 | .omni_rw_alias (1'b1), | |
247 | .omni_rw1c_alias (1'b0), | |
248 | .omni_rw1s_alias (1'b0), | |
249 | // synopsys translate_on | |
250 | .rst (rst_l_active_high), | |
251 | .rst_val (reset_address[5]), | |
252 | .csr_ld (w_ld), | |
253 | .csr_data (csrbus_wr_data[24]), | |
254 | .rw_alias (1'b1), | |
255 | .rw1c_alias (1'b0), | |
256 | .rw1s_alias (1'b0), | |
257 | .hw_ld (1'b0), | |
258 | .hw_data (1'b0), | |
259 | .cp (clk), | |
260 | .q (eq_base_address_csrbus_read_data[24]) | |
261 | ); | |
262 | ||
263 | // bit 25 | |
264 | csr_sw csr_sw_25 | |
265 | ( | |
266 | // synopsys translate_off | |
267 | .omni_ld (omni_ld), | |
268 | .omni_data (omni_data[25]), | |
269 | .omni_rw_alias (1'b1), | |
270 | .omni_rw1c_alias (1'b0), | |
271 | .omni_rw1s_alias (1'b0), | |
272 | // synopsys translate_on | |
273 | .rst (rst_l_active_high), | |
274 | .rst_val (reset_address[6]), | |
275 | .csr_ld (w_ld), | |
276 | .csr_data (csrbus_wr_data[25]), | |
277 | .rw_alias (1'b1), | |
278 | .rw1c_alias (1'b0), | |
279 | .rw1s_alias (1'b0), | |
280 | .hw_ld (1'b0), | |
281 | .hw_data (1'b0), | |
282 | .cp (clk), | |
283 | .q (eq_base_address_csrbus_read_data[25]) | |
284 | ); | |
285 | ||
286 | // bit 26 | |
287 | csr_sw csr_sw_26 | |
288 | ( | |
289 | // synopsys translate_off | |
290 | .omni_ld (omni_ld), | |
291 | .omni_data (omni_data[26]), | |
292 | .omni_rw_alias (1'b1), | |
293 | .omni_rw1c_alias (1'b0), | |
294 | .omni_rw1s_alias (1'b0), | |
295 | // synopsys translate_on | |
296 | .rst (rst_l_active_high), | |
297 | .rst_val (reset_address[7]), | |
298 | .csr_ld (w_ld), | |
299 | .csr_data (csrbus_wr_data[26]), | |
300 | .rw_alias (1'b1), | |
301 | .rw1c_alias (1'b0), | |
302 | .rw1s_alias (1'b0), | |
303 | .hw_ld (1'b0), | |
304 | .hw_data (1'b0), | |
305 | .cp (clk), | |
306 | .q (eq_base_address_csrbus_read_data[26]) | |
307 | ); | |
308 | ||
309 | // bit 27 | |
310 | csr_sw csr_sw_27 | |
311 | ( | |
312 | // synopsys translate_off | |
313 | .omni_ld (omni_ld), | |
314 | .omni_data (omni_data[27]), | |
315 | .omni_rw_alias (1'b1), | |
316 | .omni_rw1c_alias (1'b0), | |
317 | .omni_rw1s_alias (1'b0), | |
318 | // synopsys translate_on | |
319 | .rst (rst_l_active_high), | |
320 | .rst_val (reset_address[8]), | |
321 | .csr_ld (w_ld), | |
322 | .csr_data (csrbus_wr_data[27]), | |
323 | .rw_alias (1'b1), | |
324 | .rw1c_alias (1'b0), | |
325 | .rw1s_alias (1'b0), | |
326 | .hw_ld (1'b0), | |
327 | .hw_data (1'b0), | |
328 | .cp (clk), | |
329 | .q (eq_base_address_csrbus_read_data[27]) | |
330 | ); | |
331 | ||
332 | // bit 28 | |
333 | csr_sw csr_sw_28 | |
334 | ( | |
335 | // synopsys translate_off | |
336 | .omni_ld (omni_ld), | |
337 | .omni_data (omni_data[28]), | |
338 | .omni_rw_alias (1'b1), | |
339 | .omni_rw1c_alias (1'b0), | |
340 | .omni_rw1s_alias (1'b0), | |
341 | // synopsys translate_on | |
342 | .rst (rst_l_active_high), | |
343 | .rst_val (reset_address[9]), | |
344 | .csr_ld (w_ld), | |
345 | .csr_data (csrbus_wr_data[28]), | |
346 | .rw_alias (1'b1), | |
347 | .rw1c_alias (1'b0), | |
348 | .rw1s_alias (1'b0), | |
349 | .hw_ld (1'b0), | |
350 | .hw_data (1'b0), | |
351 | .cp (clk), | |
352 | .q (eq_base_address_csrbus_read_data[28]) | |
353 | ); | |
354 | ||
355 | // bit 29 | |
356 | csr_sw csr_sw_29 | |
357 | ( | |
358 | // synopsys translate_off | |
359 | .omni_ld (omni_ld), | |
360 | .omni_data (omni_data[29]), | |
361 | .omni_rw_alias (1'b1), | |
362 | .omni_rw1c_alias (1'b0), | |
363 | .omni_rw1s_alias (1'b0), | |
364 | // synopsys translate_on | |
365 | .rst (rst_l_active_high), | |
366 | .rst_val (reset_address[10]), | |
367 | .csr_ld (w_ld), | |
368 | .csr_data (csrbus_wr_data[29]), | |
369 | .rw_alias (1'b1), | |
370 | .rw1c_alias (1'b0), | |
371 | .rw1s_alias (1'b0), | |
372 | .hw_ld (1'b0), | |
373 | .hw_data (1'b0), | |
374 | .cp (clk), | |
375 | .q (eq_base_address_csrbus_read_data[29]) | |
376 | ); | |
377 | ||
378 | // bit 30 | |
379 | csr_sw csr_sw_30 | |
380 | ( | |
381 | // synopsys translate_off | |
382 | .omni_ld (omni_ld), | |
383 | .omni_data (omni_data[30]), | |
384 | .omni_rw_alias (1'b1), | |
385 | .omni_rw1c_alias (1'b0), | |
386 | .omni_rw1s_alias (1'b0), | |
387 | // synopsys translate_on | |
388 | .rst (rst_l_active_high), | |
389 | .rst_val (reset_address[11]), | |
390 | .csr_ld (w_ld), | |
391 | .csr_data (csrbus_wr_data[30]), | |
392 | .rw_alias (1'b1), | |
393 | .rw1c_alias (1'b0), | |
394 | .rw1s_alias (1'b0), | |
395 | .hw_ld (1'b0), | |
396 | .hw_data (1'b0), | |
397 | .cp (clk), | |
398 | .q (eq_base_address_csrbus_read_data[30]) | |
399 | ); | |
400 | ||
401 | // bit 31 | |
402 | csr_sw csr_sw_31 | |
403 | ( | |
404 | // synopsys translate_off | |
405 | .omni_ld (omni_ld), | |
406 | .omni_data (omni_data[31]), | |
407 | .omni_rw_alias (1'b1), | |
408 | .omni_rw1c_alias (1'b0), | |
409 | .omni_rw1s_alias (1'b0), | |
410 | // synopsys translate_on | |
411 | .rst (rst_l_active_high), | |
412 | .rst_val (reset_address[12]), | |
413 | .csr_ld (w_ld), | |
414 | .csr_data (csrbus_wr_data[31]), | |
415 | .rw_alias (1'b1), | |
416 | .rw1c_alias (1'b0), | |
417 | .rw1s_alias (1'b0), | |
418 | .hw_ld (1'b0), | |
419 | .hw_data (1'b0), | |
420 | .cp (clk), | |
421 | .q (eq_base_address_csrbus_read_data[31]) | |
422 | ); | |
423 | ||
424 | // bit 32 | |
425 | csr_sw csr_sw_32 | |
426 | ( | |
427 | // synopsys translate_off | |
428 | .omni_ld (omni_ld), | |
429 | .omni_data (omni_data[32]), | |
430 | .omni_rw_alias (1'b1), | |
431 | .omni_rw1c_alias (1'b0), | |
432 | .omni_rw1s_alias (1'b0), | |
433 | // synopsys translate_on | |
434 | .rst (rst_l_active_high), | |
435 | .rst_val (reset_address[13]), | |
436 | .csr_ld (w_ld), | |
437 | .csr_data (csrbus_wr_data[32]), | |
438 | .rw_alias (1'b1), | |
439 | .rw1c_alias (1'b0), | |
440 | .rw1s_alias (1'b0), | |
441 | .hw_ld (1'b0), | |
442 | .hw_data (1'b0), | |
443 | .cp (clk), | |
444 | .q (eq_base_address_csrbus_read_data[32]) | |
445 | ); | |
446 | ||
447 | // bit 33 | |
448 | csr_sw csr_sw_33 | |
449 | ( | |
450 | // synopsys translate_off | |
451 | .omni_ld (omni_ld), | |
452 | .omni_data (omni_data[33]), | |
453 | .omni_rw_alias (1'b1), | |
454 | .omni_rw1c_alias (1'b0), | |
455 | .omni_rw1s_alias (1'b0), | |
456 | // synopsys translate_on | |
457 | .rst (rst_l_active_high), | |
458 | .rst_val (reset_address[14]), | |
459 | .csr_ld (w_ld), | |
460 | .csr_data (csrbus_wr_data[33]), | |
461 | .rw_alias (1'b1), | |
462 | .rw1c_alias (1'b0), | |
463 | .rw1s_alias (1'b0), | |
464 | .hw_ld (1'b0), | |
465 | .hw_data (1'b0), | |
466 | .cp (clk), | |
467 | .q (eq_base_address_csrbus_read_data[33]) | |
468 | ); | |
469 | ||
470 | // bit 34 | |
471 | csr_sw csr_sw_34 | |
472 | ( | |
473 | // synopsys translate_off | |
474 | .omni_ld (omni_ld), | |
475 | .omni_data (omni_data[34]), | |
476 | .omni_rw_alias (1'b1), | |
477 | .omni_rw1c_alias (1'b0), | |
478 | .omni_rw1s_alias (1'b0), | |
479 | // synopsys translate_on | |
480 | .rst (rst_l_active_high), | |
481 | .rst_val (reset_address[15]), | |
482 | .csr_ld (w_ld), | |
483 | .csr_data (csrbus_wr_data[34]), | |
484 | .rw_alias (1'b1), | |
485 | .rw1c_alias (1'b0), | |
486 | .rw1s_alias (1'b0), | |
487 | .hw_ld (1'b0), | |
488 | .hw_data (1'b0), | |
489 | .cp (clk), | |
490 | .q (eq_base_address_csrbus_read_data[34]) | |
491 | ); | |
492 | ||
493 | // bit 35 | |
494 | csr_sw csr_sw_35 | |
495 | ( | |
496 | // synopsys translate_off | |
497 | .omni_ld (omni_ld), | |
498 | .omni_data (omni_data[35]), | |
499 | .omni_rw_alias (1'b1), | |
500 | .omni_rw1c_alias (1'b0), | |
501 | .omni_rw1s_alias (1'b0), | |
502 | // synopsys translate_on | |
503 | .rst (rst_l_active_high), | |
504 | .rst_val (reset_address[16]), | |
505 | .csr_ld (w_ld), | |
506 | .csr_data (csrbus_wr_data[35]), | |
507 | .rw_alias (1'b1), | |
508 | .rw1c_alias (1'b0), | |
509 | .rw1s_alias (1'b0), | |
510 | .hw_ld (1'b0), | |
511 | .hw_data (1'b0), | |
512 | .cp (clk), | |
513 | .q (eq_base_address_csrbus_read_data[35]) | |
514 | ); | |
515 | ||
516 | // bit 36 | |
517 | csr_sw csr_sw_36 | |
518 | ( | |
519 | // synopsys translate_off | |
520 | .omni_ld (omni_ld), | |
521 | .omni_data (omni_data[36]), | |
522 | .omni_rw_alias (1'b1), | |
523 | .omni_rw1c_alias (1'b0), | |
524 | .omni_rw1s_alias (1'b0), | |
525 | // synopsys translate_on | |
526 | .rst (rst_l_active_high), | |
527 | .rst_val (reset_address[17]), | |
528 | .csr_ld (w_ld), | |
529 | .csr_data (csrbus_wr_data[36]), | |
530 | .rw_alias (1'b1), | |
531 | .rw1c_alias (1'b0), | |
532 | .rw1s_alias (1'b0), | |
533 | .hw_ld (1'b0), | |
534 | .hw_data (1'b0), | |
535 | .cp (clk), | |
536 | .q (eq_base_address_csrbus_read_data[36]) | |
537 | ); | |
538 | ||
539 | // bit 37 | |
540 | csr_sw csr_sw_37 | |
541 | ( | |
542 | // synopsys translate_off | |
543 | .omni_ld (omni_ld), | |
544 | .omni_data (omni_data[37]), | |
545 | .omni_rw_alias (1'b1), | |
546 | .omni_rw1c_alias (1'b0), | |
547 | .omni_rw1s_alias (1'b0), | |
548 | // synopsys translate_on | |
549 | .rst (rst_l_active_high), | |
550 | .rst_val (reset_address[18]), | |
551 | .csr_ld (w_ld), | |
552 | .csr_data (csrbus_wr_data[37]), | |
553 | .rw_alias (1'b1), | |
554 | .rw1c_alias (1'b0), | |
555 | .rw1s_alias (1'b0), | |
556 | .hw_ld (1'b0), | |
557 | .hw_data (1'b0), | |
558 | .cp (clk), | |
559 | .q (eq_base_address_csrbus_read_data[37]) | |
560 | ); | |
561 | ||
562 | // bit 38 | |
563 | csr_sw csr_sw_38 | |
564 | ( | |
565 | // synopsys translate_off | |
566 | .omni_ld (omni_ld), | |
567 | .omni_data (omni_data[38]), | |
568 | .omni_rw_alias (1'b1), | |
569 | .omni_rw1c_alias (1'b0), | |
570 | .omni_rw1s_alias (1'b0), | |
571 | // synopsys translate_on | |
572 | .rst (rst_l_active_high), | |
573 | .rst_val (reset_address[19]), | |
574 | .csr_ld (w_ld), | |
575 | .csr_data (csrbus_wr_data[38]), | |
576 | .rw_alias (1'b1), | |
577 | .rw1c_alias (1'b0), | |
578 | .rw1s_alias (1'b0), | |
579 | .hw_ld (1'b0), | |
580 | .hw_data (1'b0), | |
581 | .cp (clk), | |
582 | .q (eq_base_address_csrbus_read_data[38]) | |
583 | ); | |
584 | ||
585 | // bit 39 | |
586 | csr_sw csr_sw_39 | |
587 | ( | |
588 | // synopsys translate_off | |
589 | .omni_ld (omni_ld), | |
590 | .omni_data (omni_data[39]), | |
591 | .omni_rw_alias (1'b1), | |
592 | .omni_rw1c_alias (1'b0), | |
593 | .omni_rw1s_alias (1'b0), | |
594 | // synopsys translate_on | |
595 | .rst (rst_l_active_high), | |
596 | .rst_val (reset_address[20]), | |
597 | .csr_ld (w_ld), | |
598 | .csr_data (csrbus_wr_data[39]), | |
599 | .rw_alias (1'b1), | |
600 | .rw1c_alias (1'b0), | |
601 | .rw1s_alias (1'b0), | |
602 | .hw_ld (1'b0), | |
603 | .hw_data (1'b0), | |
604 | .cp (clk), | |
605 | .q (eq_base_address_csrbus_read_data[39]) | |
606 | ); | |
607 | ||
608 | // bit 40 | |
609 | csr_sw csr_sw_40 | |
610 | ( | |
611 | // synopsys translate_off | |
612 | .omni_ld (omni_ld), | |
613 | .omni_data (omni_data[40]), | |
614 | .omni_rw_alias (1'b1), | |
615 | .omni_rw1c_alias (1'b0), | |
616 | .omni_rw1s_alias (1'b0), | |
617 | // synopsys translate_on | |
618 | .rst (rst_l_active_high), | |
619 | .rst_val (reset_address[21]), | |
620 | .csr_ld (w_ld), | |
621 | .csr_data (csrbus_wr_data[40]), | |
622 | .rw_alias (1'b1), | |
623 | .rw1c_alias (1'b0), | |
624 | .rw1s_alias (1'b0), | |
625 | .hw_ld (1'b0), | |
626 | .hw_data (1'b0), | |
627 | .cp (clk), | |
628 | .q (eq_base_address_csrbus_read_data[40]) | |
629 | ); | |
630 | ||
631 | // bit 41 | |
632 | csr_sw csr_sw_41 | |
633 | ( | |
634 | // synopsys translate_off | |
635 | .omni_ld (omni_ld), | |
636 | .omni_data (omni_data[41]), | |
637 | .omni_rw_alias (1'b1), | |
638 | .omni_rw1c_alias (1'b0), | |
639 | .omni_rw1s_alias (1'b0), | |
640 | // synopsys translate_on | |
641 | .rst (rst_l_active_high), | |
642 | .rst_val (reset_address[22]), | |
643 | .csr_ld (w_ld), | |
644 | .csr_data (csrbus_wr_data[41]), | |
645 | .rw_alias (1'b1), | |
646 | .rw1c_alias (1'b0), | |
647 | .rw1s_alias (1'b0), | |
648 | .hw_ld (1'b0), | |
649 | .hw_data (1'b0), | |
650 | .cp (clk), | |
651 | .q (eq_base_address_csrbus_read_data[41]) | |
652 | ); | |
653 | ||
654 | // bit 42 | |
655 | csr_sw csr_sw_42 | |
656 | ( | |
657 | // synopsys translate_off | |
658 | .omni_ld (omni_ld), | |
659 | .omni_data (omni_data[42]), | |
660 | .omni_rw_alias (1'b1), | |
661 | .omni_rw1c_alias (1'b0), | |
662 | .omni_rw1s_alias (1'b0), | |
663 | // synopsys translate_on | |
664 | .rst (rst_l_active_high), | |
665 | .rst_val (reset_address[23]), | |
666 | .csr_ld (w_ld), | |
667 | .csr_data (csrbus_wr_data[42]), | |
668 | .rw_alias (1'b1), | |
669 | .rw1c_alias (1'b0), | |
670 | .rw1s_alias (1'b0), | |
671 | .hw_ld (1'b0), | |
672 | .hw_data (1'b0), | |
673 | .cp (clk), | |
674 | .q (eq_base_address_csrbus_read_data[42]) | |
675 | ); | |
676 | ||
677 | // bit 43 | |
678 | csr_sw csr_sw_43 | |
679 | ( | |
680 | // synopsys translate_off | |
681 | .omni_ld (omni_ld), | |
682 | .omni_data (omni_data[43]), | |
683 | .omni_rw_alias (1'b1), | |
684 | .omni_rw1c_alias (1'b0), | |
685 | .omni_rw1s_alias (1'b0), | |
686 | // synopsys translate_on | |
687 | .rst (rst_l_active_high), | |
688 | .rst_val (reset_address[24]), | |
689 | .csr_ld (w_ld), | |
690 | .csr_data (csrbus_wr_data[43]), | |
691 | .rw_alias (1'b1), | |
692 | .rw1c_alias (1'b0), | |
693 | .rw1s_alias (1'b0), | |
694 | .hw_ld (1'b0), | |
695 | .hw_data (1'b0), | |
696 | .cp (clk), | |
697 | .q (eq_base_address_csrbus_read_data[43]) | |
698 | ); | |
699 | ||
700 | // bit 44 | |
701 | csr_sw csr_sw_44 | |
702 | ( | |
703 | // synopsys translate_off | |
704 | .omni_ld (omni_ld), | |
705 | .omni_data (omni_data[44]), | |
706 | .omni_rw_alias (1'b1), | |
707 | .omni_rw1c_alias (1'b0), | |
708 | .omni_rw1s_alias (1'b0), | |
709 | // synopsys translate_on | |
710 | .rst (rst_l_active_high), | |
711 | .rst_val (reset_address[25]), | |
712 | .csr_ld (w_ld), | |
713 | .csr_data (csrbus_wr_data[44]), | |
714 | .rw_alias (1'b1), | |
715 | .rw1c_alias (1'b0), | |
716 | .rw1s_alias (1'b0), | |
717 | .hw_ld (1'b0), | |
718 | .hw_data (1'b0), | |
719 | .cp (clk), | |
720 | .q (eq_base_address_csrbus_read_data[44]) | |
721 | ); | |
722 | ||
723 | // bit 45 | |
724 | csr_sw csr_sw_45 | |
725 | ( | |
726 | // synopsys translate_off | |
727 | .omni_ld (omni_ld), | |
728 | .omni_data (omni_data[45]), | |
729 | .omni_rw_alias (1'b1), | |
730 | .omni_rw1c_alias (1'b0), | |
731 | .omni_rw1s_alias (1'b0), | |
732 | // synopsys translate_on | |
733 | .rst (rst_l_active_high), | |
734 | .rst_val (reset_address[26]), | |
735 | .csr_ld (w_ld), | |
736 | .csr_data (csrbus_wr_data[45]), | |
737 | .rw_alias (1'b1), | |
738 | .rw1c_alias (1'b0), | |
739 | .rw1s_alias (1'b0), | |
740 | .hw_ld (1'b0), | |
741 | .hw_data (1'b0), | |
742 | .cp (clk), | |
743 | .q (eq_base_address_csrbus_read_data[45]) | |
744 | ); | |
745 | ||
746 | // bit 46 | |
747 | csr_sw csr_sw_46 | |
748 | ( | |
749 | // synopsys translate_off | |
750 | .omni_ld (omni_ld), | |
751 | .omni_data (omni_data[46]), | |
752 | .omni_rw_alias (1'b1), | |
753 | .omni_rw1c_alias (1'b0), | |
754 | .omni_rw1s_alias (1'b0), | |
755 | // synopsys translate_on | |
756 | .rst (rst_l_active_high), | |
757 | .rst_val (reset_address[27]), | |
758 | .csr_ld (w_ld), | |
759 | .csr_data (csrbus_wr_data[46]), | |
760 | .rw_alias (1'b1), | |
761 | .rw1c_alias (1'b0), | |
762 | .rw1s_alias (1'b0), | |
763 | .hw_ld (1'b0), | |
764 | .hw_data (1'b0), | |
765 | .cp (clk), | |
766 | .q (eq_base_address_csrbus_read_data[46]) | |
767 | ); | |
768 | ||
769 | // bit 47 | |
770 | csr_sw csr_sw_47 | |
771 | ( | |
772 | // synopsys translate_off | |
773 | .omni_ld (omni_ld), | |
774 | .omni_data (omni_data[47]), | |
775 | .omni_rw_alias (1'b1), | |
776 | .omni_rw1c_alias (1'b0), | |
777 | .omni_rw1s_alias (1'b0), | |
778 | // synopsys translate_on | |
779 | .rst (rst_l_active_high), | |
780 | .rst_val (reset_address[28]), | |
781 | .csr_ld (w_ld), | |
782 | .csr_data (csrbus_wr_data[47]), | |
783 | .rw_alias (1'b1), | |
784 | .rw1c_alias (1'b0), | |
785 | .rw1s_alias (1'b0), | |
786 | .hw_ld (1'b0), | |
787 | .hw_data (1'b0), | |
788 | .cp (clk), | |
789 | .q (eq_base_address_csrbus_read_data[47]) | |
790 | ); | |
791 | ||
792 | // bit 48 | |
793 | csr_sw csr_sw_48 | |
794 | ( | |
795 | // synopsys translate_off | |
796 | .omni_ld (omni_ld), | |
797 | .omni_data (omni_data[48]), | |
798 | .omni_rw_alias (1'b1), | |
799 | .omni_rw1c_alias (1'b0), | |
800 | .omni_rw1s_alias (1'b0), | |
801 | // synopsys translate_on | |
802 | .rst (rst_l_active_high), | |
803 | .rst_val (reset_address[29]), | |
804 | .csr_ld (w_ld), | |
805 | .csr_data (csrbus_wr_data[48]), | |
806 | .rw_alias (1'b1), | |
807 | .rw1c_alias (1'b0), | |
808 | .rw1s_alias (1'b0), | |
809 | .hw_ld (1'b0), | |
810 | .hw_data (1'b0), | |
811 | .cp (clk), | |
812 | .q (eq_base_address_csrbus_read_data[48]) | |
813 | ); | |
814 | ||
815 | // bit 49 | |
816 | csr_sw csr_sw_49 | |
817 | ( | |
818 | // synopsys translate_off | |
819 | .omni_ld (omni_ld), | |
820 | .omni_data (omni_data[49]), | |
821 | .omni_rw_alias (1'b1), | |
822 | .omni_rw1c_alias (1'b0), | |
823 | .omni_rw1s_alias (1'b0), | |
824 | // synopsys translate_on | |
825 | .rst (rst_l_active_high), | |
826 | .rst_val (reset_address[30]), | |
827 | .csr_ld (w_ld), | |
828 | .csr_data (csrbus_wr_data[49]), | |
829 | .rw_alias (1'b1), | |
830 | .rw1c_alias (1'b0), | |
831 | .rw1s_alias (1'b0), | |
832 | .hw_ld (1'b0), | |
833 | .hw_data (1'b0), | |
834 | .cp (clk), | |
835 | .q (eq_base_address_csrbus_read_data[49]) | |
836 | ); | |
837 | ||
838 | // bit 50 | |
839 | csr_sw csr_sw_50 | |
840 | ( | |
841 | // synopsys translate_off | |
842 | .omni_ld (omni_ld), | |
843 | .omni_data (omni_data[50]), | |
844 | .omni_rw_alias (1'b1), | |
845 | .omni_rw1c_alias (1'b0), | |
846 | .omni_rw1s_alias (1'b0), | |
847 | // synopsys translate_on | |
848 | .rst (rst_l_active_high), | |
849 | .rst_val (reset_address[31]), | |
850 | .csr_ld (w_ld), | |
851 | .csr_data (csrbus_wr_data[50]), | |
852 | .rw_alias (1'b1), | |
853 | .rw1c_alias (1'b0), | |
854 | .rw1s_alias (1'b0), | |
855 | .hw_ld (1'b0), | |
856 | .hw_data (1'b0), | |
857 | .cp (clk), | |
858 | .q (eq_base_address_csrbus_read_data[50]) | |
859 | ); | |
860 | ||
861 | // bit 51 | |
862 | csr_sw csr_sw_51 | |
863 | ( | |
864 | // synopsys translate_off | |
865 | .omni_ld (omni_ld), | |
866 | .omni_data (omni_data[51]), | |
867 | .omni_rw_alias (1'b1), | |
868 | .omni_rw1c_alias (1'b0), | |
869 | .omni_rw1s_alias (1'b0), | |
870 | // synopsys translate_on | |
871 | .rst (rst_l_active_high), | |
872 | .rst_val (reset_address[32]), | |
873 | .csr_ld (w_ld), | |
874 | .csr_data (csrbus_wr_data[51]), | |
875 | .rw_alias (1'b1), | |
876 | .rw1c_alias (1'b0), | |
877 | .rw1s_alias (1'b0), | |
878 | .hw_ld (1'b0), | |
879 | .hw_data (1'b0), | |
880 | .cp (clk), | |
881 | .q (eq_base_address_csrbus_read_data[51]) | |
882 | ); | |
883 | ||
884 | // bit 52 | |
885 | csr_sw csr_sw_52 | |
886 | ( | |
887 | // synopsys translate_off | |
888 | .omni_ld (omni_ld), | |
889 | .omni_data (omni_data[52]), | |
890 | .omni_rw_alias (1'b1), | |
891 | .omni_rw1c_alias (1'b0), | |
892 | .omni_rw1s_alias (1'b0), | |
893 | // synopsys translate_on | |
894 | .rst (rst_l_active_high), | |
895 | .rst_val (reset_address[33]), | |
896 | .csr_ld (w_ld), | |
897 | .csr_data (csrbus_wr_data[52]), | |
898 | .rw_alias (1'b1), | |
899 | .rw1c_alias (1'b0), | |
900 | .rw1s_alias (1'b0), | |
901 | .hw_ld (1'b0), | |
902 | .hw_data (1'b0), | |
903 | .cp (clk), | |
904 | .q (eq_base_address_csrbus_read_data[52]) | |
905 | ); | |
906 | ||
907 | // bit 53 | |
908 | csr_sw csr_sw_53 | |
909 | ( | |
910 | // synopsys translate_off | |
911 | .omni_ld (omni_ld), | |
912 | .omni_data (omni_data[53]), | |
913 | .omni_rw_alias (1'b1), | |
914 | .omni_rw1c_alias (1'b0), | |
915 | .omni_rw1s_alias (1'b0), | |
916 | // synopsys translate_on | |
917 | .rst (rst_l_active_high), | |
918 | .rst_val (reset_address[34]), | |
919 | .csr_ld (w_ld), | |
920 | .csr_data (csrbus_wr_data[53]), | |
921 | .rw_alias (1'b1), | |
922 | .rw1c_alias (1'b0), | |
923 | .rw1s_alias (1'b0), | |
924 | .hw_ld (1'b0), | |
925 | .hw_data (1'b0), | |
926 | .cp (clk), | |
927 | .q (eq_base_address_csrbus_read_data[53]) | |
928 | ); | |
929 | ||
930 | // bit 54 | |
931 | csr_sw csr_sw_54 | |
932 | ( | |
933 | // synopsys translate_off | |
934 | .omni_ld (omni_ld), | |
935 | .omni_data (omni_data[54]), | |
936 | .omni_rw_alias (1'b1), | |
937 | .omni_rw1c_alias (1'b0), | |
938 | .omni_rw1s_alias (1'b0), | |
939 | // synopsys translate_on | |
940 | .rst (rst_l_active_high), | |
941 | .rst_val (reset_address[35]), | |
942 | .csr_ld (w_ld), | |
943 | .csr_data (csrbus_wr_data[54]), | |
944 | .rw_alias (1'b1), | |
945 | .rw1c_alias (1'b0), | |
946 | .rw1s_alias (1'b0), | |
947 | .hw_ld (1'b0), | |
948 | .hw_data (1'b0), | |
949 | .cp (clk), | |
950 | .q (eq_base_address_csrbus_read_data[54]) | |
951 | ); | |
952 | ||
953 | // bit 55 | |
954 | csr_sw csr_sw_55 | |
955 | ( | |
956 | // synopsys translate_off | |
957 | .omni_ld (omni_ld), | |
958 | .omni_data (omni_data[55]), | |
959 | .omni_rw_alias (1'b1), | |
960 | .omni_rw1c_alias (1'b0), | |
961 | .omni_rw1s_alias (1'b0), | |
962 | // synopsys translate_on | |
963 | .rst (rst_l_active_high), | |
964 | .rst_val (reset_address[36]), | |
965 | .csr_ld (w_ld), | |
966 | .csr_data (csrbus_wr_data[55]), | |
967 | .rw_alias (1'b1), | |
968 | .rw1c_alias (1'b0), | |
969 | .rw1s_alias (1'b0), | |
970 | .hw_ld (1'b0), | |
971 | .hw_data (1'b0), | |
972 | .cp (clk), | |
973 | .q (eq_base_address_csrbus_read_data[55]) | |
974 | ); | |
975 | ||
976 | // bit 56 | |
977 | csr_sw csr_sw_56 | |
978 | ( | |
979 | // synopsys translate_off | |
980 | .omni_ld (omni_ld), | |
981 | .omni_data (omni_data[56]), | |
982 | .omni_rw_alias (1'b1), | |
983 | .omni_rw1c_alias (1'b0), | |
984 | .omni_rw1s_alias (1'b0), | |
985 | // synopsys translate_on | |
986 | .rst (rst_l_active_high), | |
987 | .rst_val (reset_address[37]), | |
988 | .csr_ld (w_ld), | |
989 | .csr_data (csrbus_wr_data[56]), | |
990 | .rw_alias (1'b1), | |
991 | .rw1c_alias (1'b0), | |
992 | .rw1s_alias (1'b0), | |
993 | .hw_ld (1'b0), | |
994 | .hw_data (1'b0), | |
995 | .cp (clk), | |
996 | .q (eq_base_address_csrbus_read_data[56]) | |
997 | ); | |
998 | ||
999 | // bit 57 | |
1000 | csr_sw csr_sw_57 | |
1001 | ( | |
1002 | // synopsys translate_off | |
1003 | .omni_ld (omni_ld), | |
1004 | .omni_data (omni_data[57]), | |
1005 | .omni_rw_alias (1'b1), | |
1006 | .omni_rw1c_alias (1'b0), | |
1007 | .omni_rw1s_alias (1'b0), | |
1008 | // synopsys translate_on | |
1009 | .rst (rst_l_active_high), | |
1010 | .rst_val (reset_address[38]), | |
1011 | .csr_ld (w_ld), | |
1012 | .csr_data (csrbus_wr_data[57]), | |
1013 | .rw_alias (1'b1), | |
1014 | .rw1c_alias (1'b0), | |
1015 | .rw1s_alias (1'b0), | |
1016 | .hw_ld (1'b0), | |
1017 | .hw_data (1'b0), | |
1018 | .cp (clk), | |
1019 | .q (eq_base_address_csrbus_read_data[57]) | |
1020 | ); | |
1021 | ||
1022 | // bit 58 | |
1023 | csr_sw csr_sw_58 | |
1024 | ( | |
1025 | // synopsys translate_off | |
1026 | .omni_ld (omni_ld), | |
1027 | .omni_data (omni_data[58]), | |
1028 | .omni_rw_alias (1'b1), | |
1029 | .omni_rw1c_alias (1'b0), | |
1030 | .omni_rw1s_alias (1'b0), | |
1031 | // synopsys translate_on | |
1032 | .rst (rst_l_active_high), | |
1033 | .rst_val (reset_address[39]), | |
1034 | .csr_ld (w_ld), | |
1035 | .csr_data (csrbus_wr_data[58]), | |
1036 | .rw_alias (1'b1), | |
1037 | .rw1c_alias (1'b0), | |
1038 | .rw1s_alias (1'b0), | |
1039 | .hw_ld (1'b0), | |
1040 | .hw_data (1'b0), | |
1041 | .cp (clk), | |
1042 | .q (eq_base_address_csrbus_read_data[58]) | |
1043 | ); | |
1044 | ||
1045 | // bit 59 | |
1046 | csr_sw csr_sw_59 | |
1047 | ( | |
1048 | // synopsys translate_off | |
1049 | .omni_ld (omni_ld), | |
1050 | .omni_data (omni_data[59]), | |
1051 | .omni_rw_alias (1'b1), | |
1052 | .omni_rw1c_alias (1'b0), | |
1053 | .omni_rw1s_alias (1'b0), | |
1054 | // synopsys translate_on | |
1055 | .rst (rst_l_active_high), | |
1056 | .rst_val (reset_address[40]), | |
1057 | .csr_ld (w_ld), | |
1058 | .csr_data (csrbus_wr_data[59]), | |
1059 | .rw_alias (1'b1), | |
1060 | .rw1c_alias (1'b0), | |
1061 | .rw1s_alias (1'b0), | |
1062 | .hw_ld (1'b0), | |
1063 | .hw_data (1'b0), | |
1064 | .cp (clk), | |
1065 | .q (eq_base_address_csrbus_read_data[59]) | |
1066 | ); | |
1067 | ||
1068 | // bit 60 | |
1069 | csr_sw csr_sw_60 | |
1070 | ( | |
1071 | // synopsys translate_off | |
1072 | .omni_ld (omni_ld), | |
1073 | .omni_data (omni_data[60]), | |
1074 | .omni_rw_alias (1'b1), | |
1075 | .omni_rw1c_alias (1'b0), | |
1076 | .omni_rw1s_alias (1'b0), | |
1077 | // synopsys translate_on | |
1078 | .rst (rst_l_active_high), | |
1079 | .rst_val (reset_address[41]), | |
1080 | .csr_ld (w_ld), | |
1081 | .csr_data (csrbus_wr_data[60]), | |
1082 | .rw_alias (1'b1), | |
1083 | .rw1c_alias (1'b0), | |
1084 | .rw1s_alias (1'b0), | |
1085 | .hw_ld (1'b0), | |
1086 | .hw_data (1'b0), | |
1087 | .cp (clk), | |
1088 | .q (eq_base_address_csrbus_read_data[60]) | |
1089 | ); | |
1090 | ||
1091 | // bit 61 | |
1092 | csr_sw csr_sw_61 | |
1093 | ( | |
1094 | // synopsys translate_off | |
1095 | .omni_ld (omni_ld), | |
1096 | .omni_data (omni_data[61]), | |
1097 | .omni_rw_alias (1'b1), | |
1098 | .omni_rw1c_alias (1'b0), | |
1099 | .omni_rw1s_alias (1'b0), | |
1100 | // synopsys translate_on | |
1101 | .rst (rst_l_active_high), | |
1102 | .rst_val (reset_address[42]), | |
1103 | .csr_ld (w_ld), | |
1104 | .csr_data (csrbus_wr_data[61]), | |
1105 | .rw_alias (1'b1), | |
1106 | .rw1c_alias (1'b0), | |
1107 | .rw1s_alias (1'b0), | |
1108 | .hw_ld (1'b0), | |
1109 | .hw_data (1'b0), | |
1110 | .cp (clk), | |
1111 | .q (eq_base_address_csrbus_read_data[61]) | |
1112 | ); | |
1113 | ||
1114 | // bit 62 | |
1115 | csr_sw csr_sw_62 | |
1116 | ( | |
1117 | // synopsys translate_off | |
1118 | .omni_ld (omni_ld), | |
1119 | .omni_data (omni_data[62]), | |
1120 | .omni_rw_alias (1'b1), | |
1121 | .omni_rw1c_alias (1'b0), | |
1122 | .omni_rw1s_alias (1'b0), | |
1123 | // synopsys translate_on | |
1124 | .rst (rst_l_active_high), | |
1125 | .rst_val (reset_address[43]), | |
1126 | .csr_ld (w_ld), | |
1127 | .csr_data (csrbus_wr_data[62]), | |
1128 | .rw_alias (1'b1), | |
1129 | .rw1c_alias (1'b0), | |
1130 | .rw1s_alias (1'b0), | |
1131 | .hw_ld (1'b0), | |
1132 | .hw_data (1'b0), | |
1133 | .cp (clk), | |
1134 | .q (eq_base_address_csrbus_read_data[62]) | |
1135 | ); | |
1136 | ||
1137 | // bit 63 | |
1138 | csr_sw csr_sw_63 | |
1139 | ( | |
1140 | // synopsys translate_off | |
1141 | .omni_ld (omni_ld), | |
1142 | .omni_data (omni_data[63]), | |
1143 | .omni_rw_alias (1'b1), | |
1144 | .omni_rw1c_alias (1'b0), | |
1145 | .omni_rw1s_alias (1'b0), | |
1146 | // synopsys translate_on | |
1147 | .rst (rst_l_active_high), | |
1148 | .rst_val (reset_address[44]), | |
1149 | .csr_ld (w_ld), | |
1150 | .csr_data (csrbus_wr_data[63]), | |
1151 | .rw_alias (1'b1), | |
1152 | .rw1c_alias (1'b0), | |
1153 | .rw1s_alias (1'b0), | |
1154 | .hw_ld (1'b0), | |
1155 | .hw_data (1'b0), | |
1156 | .cp (clk), | |
1157 | .q (eq_base_address_csrbus_read_data[63]) | |
1158 | ); | |
1159 | ||
1160 | ||
1161 | endmodule // dmu_imu_eqs_csr_eq_base_address_entry |