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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_eqs_csr_eq_base_address_entry.v
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: dmu_imu_eqs_csr_eq_base_address_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
module dmu_imu_eqs_csr_eq_base_address_entry
(
// synopsys translate_off
omni_ld,
omni_data,
// synopsys translate_on
clk,
rst_l,
w_ld,
csrbus_wr_data,
eq_base_address_csrbus_read_data
);
//====================================================================
// Polarity declarations
//====================================================================
// synopsys translate_off
input omni_ld; // Omni load
// vlint flag_input_port_not_connected off
input [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH - 1:0] omni_data;
// Omni write data
// synopsys translate_on
// vlint flag_input_port_not_connected on
input clk; // Clock signal
input rst_l; // Reset signal
input w_ld; // SW load
// vlint flag_input_port_not_connected off
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH-1:0] eq_base_address_csrbus_read_data;
// SW read data
//====================================================================
// Type declarations
//====================================================================
// synopsys translate_off
wire omni_ld; // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH - 1:0] omni_data;
// Omni write data
// synopsys translate_on
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk; // Clock signal
wire rst_l; // Reset signal
wire w_ld; // SW load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH-1:0] eq_base_address_csrbus_read_data;
// SW read data
//====================================================================
// Logic
//====================================================================
//----- Reset values
// verilint 531 off
wire [44:0] reset_address = 45'h0;
// verilint 531 on
//----- Active high reset wires
wire rst_l_active_high = ~rst_l;
//====================================================
// Instantiation of flops
//====================================================
assign eq_base_address_csrbus_read_data[0] = 1'b0; // bit 0
assign eq_base_address_csrbus_read_data[1] = 1'b0; // bit 1
assign eq_base_address_csrbus_read_data[2] = 1'b0; // bit 2
assign eq_base_address_csrbus_read_data[3] = 1'b0; // bit 3
assign eq_base_address_csrbus_read_data[4] = 1'b0; // bit 4
assign eq_base_address_csrbus_read_data[5] = 1'b0; // bit 5
assign eq_base_address_csrbus_read_data[6] = 1'b0; // bit 6
assign eq_base_address_csrbus_read_data[7] = 1'b0; // bit 7
assign eq_base_address_csrbus_read_data[8] = 1'b0; // bit 8
assign eq_base_address_csrbus_read_data[9] = 1'b0; // bit 9
assign eq_base_address_csrbus_read_data[10] = 1'b0; // bit 10
assign eq_base_address_csrbus_read_data[11] = 1'b0; // bit 11
assign eq_base_address_csrbus_read_data[12] = 1'b0; // bit 12
assign eq_base_address_csrbus_read_data[13] = 1'b0; // bit 13
assign eq_base_address_csrbus_read_data[14] = 1'b0; // bit 14
assign eq_base_address_csrbus_read_data[15] = 1'b0; // bit 15
assign eq_base_address_csrbus_read_data[16] = 1'b0; // bit 16
assign eq_base_address_csrbus_read_data[17] = 1'b0; // bit 17
assign eq_base_address_csrbus_read_data[18] = 1'b0; // bit 18
// bit 19
csr_sw csr_sw_19
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[19]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[0]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[19]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[19])
);
// bit 20
csr_sw csr_sw_20
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[20]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[1]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[20]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[20])
);
// bit 21
csr_sw csr_sw_21
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[21]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[2]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[21]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[21])
);
// bit 22
csr_sw csr_sw_22
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[22]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[3]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[22]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[22])
);
// bit 23
csr_sw csr_sw_23
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[23]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[4]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[23]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[23])
);
// bit 24
csr_sw csr_sw_24
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[24]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[5]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[24]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[24])
);
// bit 25
csr_sw csr_sw_25
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[25]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[6]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[25]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[25])
);
// bit 26
csr_sw csr_sw_26
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[26]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[7]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[26]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[26])
);
// bit 27
csr_sw csr_sw_27
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[27]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[8]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[27]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[27])
);
// bit 28
csr_sw csr_sw_28
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[28]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[9]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[28]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[28])
);
// bit 29
csr_sw csr_sw_29
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[29]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[10]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[29]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[29])
);
// bit 30
csr_sw csr_sw_30
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[30]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[11]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[30]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[30])
);
// bit 31
csr_sw csr_sw_31
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[31]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[12]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[31]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[31])
);
// bit 32
csr_sw csr_sw_32
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[32]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[13]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[32]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[32])
);
// bit 33
csr_sw csr_sw_33
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[33]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[14]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[33]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[33])
);
// bit 34
csr_sw csr_sw_34
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[34]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[15]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[34]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[34])
);
// bit 35
csr_sw csr_sw_35
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[35]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[16]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[35]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[35])
);
// bit 36
csr_sw csr_sw_36
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[36]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[17]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[36]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[36])
);
// bit 37
csr_sw csr_sw_37
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[37]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[18]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[37]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[37])
);
// bit 38
csr_sw csr_sw_38
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[38]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[19]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[38]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[38])
);
// bit 39
csr_sw csr_sw_39
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[39]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[20]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[39]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[39])
);
// bit 40
csr_sw csr_sw_40
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[40]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[21]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[40]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[40])
);
// bit 41
csr_sw csr_sw_41
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[41]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[22]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[41]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[41])
);
// bit 42
csr_sw csr_sw_42
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[42]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[23]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[42]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[42])
);
// bit 43
csr_sw csr_sw_43
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[43]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[24]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[43]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[43])
);
// bit 44
csr_sw csr_sw_44
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[44]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[25]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[44]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[44])
);
// bit 45
csr_sw csr_sw_45
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[45]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[26]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[45]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[45])
);
// bit 46
csr_sw csr_sw_46
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[46]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[27]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[46]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[46])
);
// bit 47
csr_sw csr_sw_47
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[47]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[28]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[47]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[47])
);
// bit 48
csr_sw csr_sw_48
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[48]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[29]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[48]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[48])
);
// bit 49
csr_sw csr_sw_49
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[49]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[30]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[49]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[49])
);
// bit 50
csr_sw csr_sw_50
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[50]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[31]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[50]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[50])
);
// bit 51
csr_sw csr_sw_51
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[51]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[32]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[51]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[51])
);
// bit 52
csr_sw csr_sw_52
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[52]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[33]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[52]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[52])
);
// bit 53
csr_sw csr_sw_53
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[53]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[34]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[53]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[53])
);
// bit 54
csr_sw csr_sw_54
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[54]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[35]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[54]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[54])
);
// bit 55
csr_sw csr_sw_55
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[55]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[36]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[55]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[55])
);
// bit 56
csr_sw csr_sw_56
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[56]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[37]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[56]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[56])
);
// bit 57
csr_sw csr_sw_57
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[57]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[38]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[57]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[57])
);
// bit 58
csr_sw csr_sw_58
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[58]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[39]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[58]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[58])
);
// bit 59
csr_sw csr_sw_59
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[59]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[40]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[59]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[59])
);
// bit 60
csr_sw csr_sw_60
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[60]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[41]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[60]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[60])
);
// bit 61
csr_sw csr_sw_61
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[61]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[42]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[61]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[61])
);
// bit 62
csr_sw csr_sw_62
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[62]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[43]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[62]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[62])
);
// bit 63
csr_sw csr_sw_63
(
// synopsys translate_off
.omni_ld (omni_ld),
.omni_data (omni_data[63]),
.omni_rw_alias (1'b1),
.omni_rw1c_alias (1'b0),
.omni_rw1s_alias (1'b0),
// synopsys translate_on
.rst (rst_l_active_high),
.rst_val (reset_address[44]),
.csr_ld (w_ld),
.csr_data (csrbus_wr_data[63]),
.rw_alias (1'b1),
.rw1c_alias (1'b0),
.rw1s_alias (1'b0),
.hw_ld (1'b0),
.hw_data (1'b0),
.cp (clk),
.q (eq_base_address_csrbus_read_data[63])
);
endmodule // dmu_imu_eqs_csr_eq_base_address_entry
Full OpenSPARC design & verification tarball including full HDL.