Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_ics_csr_imu_eqs_error_log_reg_entry.v

// ========== Copyright Header Begin ==========================================
// 
// OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_eqs_error_log_reg_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
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//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
// 
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// choice is available it will apply instead, Sun elects to use only 
// the General Public License version 2 (GPLv2) at this time for any 
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// ========== Copyright Header End ============================================
module dmu_imu_ics_csr_imu_eqs_error_log_reg_entry 
	(
	// synopsys translate_off
	  omni_ld,
	  omni_data,
	// synopsys translate_on
	clk,
	por_l,
	w_ld,
	csrbus_wr_data,
	imu_eqs_error_log_reg_csrbus_read_data,
	imu_eqs_error_log_reg_hw_ld,
	imu_eqs_error_log_reg_hw_write
	);

//====================================================================
//     Polarity declarations
//====================================================================
// synopsys translate_off
  input  omni_ld;  // Omni load
// vlint flag_input_port_not_connected off
  input  [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH - 1:0] omni_data;
    // Omni write data
// synopsys translate_on
// vlint flag_input_port_not_connected on
input  clk;  // Clock signal
input  por_l;  // Reset signal
input  w_ld;  // SW load
// vlint flag_input_port_not_connected off
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH-1:0] imu_eqs_error_log_reg_csrbus_read_data;
    // SW read data
input  imu_eqs_error_log_reg_hw_ld;  // Hardware load enable for
                                     // imu_eqs_error_log_reg. When set, <hw
                                     // write signal>  will be loaded into
                                     // imu_eqs_error_log_reg.
// vlint flag_input_port_not_connected off
input  [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH -1:0] imu_eqs_error_log_reg_hw_write;
    // data bus for hw loading of imu_eqs_error_log_reg.
// vlint flag_input_port_not_connected on

//====================================================================
//     Type declarations
//====================================================================
// synopsys translate_off
  wire omni_ld;  // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
  wire [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH - 1:0] omni_data;
    // Omni write data
// synopsys translate_on
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk;  // Clock signal
wire por_l;  // Reset signal
wire w_ld;  // SW load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH-1:0] imu_eqs_error_log_reg_csrbus_read_data;
    // SW read data
wire imu_eqs_error_log_reg_hw_ld;  // Hardware load enable for
                                   // imu_eqs_error_log_reg. When set, <hw write
                                   // signal>  will be loaded into
                                   // imu_eqs_error_log_reg.
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_DLC_IMU_ICS_CSR_IMU_EQS_ERROR_LOG_REG_WIDTH -1:0] imu_eqs_error_log_reg_hw_write;
    // data bus for hw loading of imu_eqs_error_log_reg.
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on

//====================================================================
//     Logic     
//====================================================================

//----- Reset values
// verilint 531 off
wire [5:0] reset_eq_num = 6'b0;
// verilint 531 on

//----- Active high reset wires 
wire por_l_active_high = ~por_l;

//====================================================
//     Instantiation of flops
//====================================================

// bit 0
csr_sw csr_sw_0
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[0]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_eq_num[0]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[0]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (imu_eqs_error_log_reg_hw_ld),
	.hw_data        (imu_eqs_error_log_reg_hw_write[0]),
	.cp             (clk),
	.q              (imu_eqs_error_log_reg_csrbus_read_data[0])
	);

// bit 1
csr_sw csr_sw_1
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[1]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_eq_num[1]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[1]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (imu_eqs_error_log_reg_hw_ld),
	.hw_data        (imu_eqs_error_log_reg_hw_write[1]),
	.cp             (clk),
	.q              (imu_eqs_error_log_reg_csrbus_read_data[1])
	);

// bit 2
csr_sw csr_sw_2
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[2]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_eq_num[2]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[2]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (imu_eqs_error_log_reg_hw_ld),
	.hw_data        (imu_eqs_error_log_reg_hw_write[2]),
	.cp             (clk),
	.q              (imu_eqs_error_log_reg_csrbus_read_data[2])
	);

// bit 3
csr_sw csr_sw_3
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[3]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_eq_num[3]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[3]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (imu_eqs_error_log_reg_hw_ld),
	.hw_data        (imu_eqs_error_log_reg_hw_write[3]),
	.cp             (clk),
	.q              (imu_eqs_error_log_reg_csrbus_read_data[3])
	);

// bit 4
csr_sw csr_sw_4
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[4]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_eq_num[4]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[4]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (imu_eqs_error_log_reg_hw_ld),
	.hw_data        (imu_eqs_error_log_reg_hw_write[4]),
	.cp             (clk),
	.q              (imu_eqs_error_log_reg_csrbus_read_data[4])
	);

// bit 5
csr_sw csr_sw_5
	(
	// synopsys translate_off
	  .omni_ld        (omni_ld),
	  .omni_data      (omni_data[5]),
	  .omni_rw_alias   (1'b1),
	  .omni_rw1c_alias (1'b0),
	  .omni_rw1s_alias (1'b0),
	// synopsys translate_on
	.rst            (por_l_active_high),
	.rst_val        (reset_eq_num[5]),
	.csr_ld         (w_ld),
	.csr_data       (csrbus_wr_data[5]),
	.rw_alias       (1'b1),
	.rw1c_alias     (1'b0),
	.rw1s_alias     (1'b0),
	.hw_ld          (imu_eqs_error_log_reg_hw_ld),
	.hw_data        (imu_eqs_error_log_reg_hw_write[5]),
	.cp             (clk),
	.q              (imu_eqs_error_log_reg_csrbus_read_data[5])
	);

assign  imu_eqs_error_log_reg_csrbus_read_data[6] = 1'b0;  // bit 6
assign  imu_eqs_error_log_reg_csrbus_read_data[7] = 1'b0;  // bit 7
assign  imu_eqs_error_log_reg_csrbus_read_data[8] = 1'b0;  // bit 8
assign  imu_eqs_error_log_reg_csrbus_read_data[9] = 1'b0;  // bit 9
assign  imu_eqs_error_log_reg_csrbus_read_data[10] = 1'b0;  // bit 10
assign  imu_eqs_error_log_reg_csrbus_read_data[11] = 1'b0;  // bit 11
assign  imu_eqs_error_log_reg_csrbus_read_data[12] = 1'b0;  // bit 12
assign  imu_eqs_error_log_reg_csrbus_read_data[13] = 1'b0;  // bit 13
assign  imu_eqs_error_log_reg_csrbus_read_data[14] = 1'b0;  // bit 14
assign  imu_eqs_error_log_reg_csrbus_read_data[15] = 1'b0;  // bit 15
assign  imu_eqs_error_log_reg_csrbus_read_data[16] = 1'b0;  // bit 16
assign  imu_eqs_error_log_reg_csrbus_read_data[17] = 1'b0;  // bit 17
assign  imu_eqs_error_log_reg_csrbus_read_data[18] = 1'b0;  // bit 18
assign  imu_eqs_error_log_reg_csrbus_read_data[19] = 1'b0;  // bit 19
assign  imu_eqs_error_log_reg_csrbus_read_data[20] = 1'b0;  // bit 20
assign  imu_eqs_error_log_reg_csrbus_read_data[21] = 1'b0;  // bit 21
assign  imu_eqs_error_log_reg_csrbus_read_data[22] = 1'b0;  // bit 22
assign  imu_eqs_error_log_reg_csrbus_read_data[23] = 1'b0;  // bit 23
assign  imu_eqs_error_log_reg_csrbus_read_data[24] = 1'b0;  // bit 24
assign  imu_eqs_error_log_reg_csrbus_read_data[25] = 1'b0;  // bit 25
assign  imu_eqs_error_log_reg_csrbus_read_data[26] = 1'b0;  // bit 26
assign  imu_eqs_error_log_reg_csrbus_read_data[27] = 1'b0;  // bit 27
assign  imu_eqs_error_log_reg_csrbus_read_data[28] = 1'b0;  // bit 28
assign  imu_eqs_error_log_reg_csrbus_read_data[29] = 1'b0;  // bit 29
assign  imu_eqs_error_log_reg_csrbus_read_data[30] = 1'b0;  // bit 30
assign  imu_eqs_error_log_reg_csrbus_read_data[31] = 1'b0;  // bit 31
assign  imu_eqs_error_log_reg_csrbus_read_data[32] = 1'b0;  // bit 32
assign  imu_eqs_error_log_reg_csrbus_read_data[33] = 1'b0;  // bit 33
assign  imu_eqs_error_log_reg_csrbus_read_data[34] = 1'b0;  // bit 34
assign  imu_eqs_error_log_reg_csrbus_read_data[35] = 1'b0;  // bit 35
assign  imu_eqs_error_log_reg_csrbus_read_data[36] = 1'b0;  // bit 36
assign  imu_eqs_error_log_reg_csrbus_read_data[37] = 1'b0;  // bit 37
assign  imu_eqs_error_log_reg_csrbus_read_data[38] = 1'b0;  // bit 38
assign  imu_eqs_error_log_reg_csrbus_read_data[39] = 1'b0;  // bit 39
assign  imu_eqs_error_log_reg_csrbus_read_data[40] = 1'b0;  // bit 40
assign  imu_eqs_error_log_reg_csrbus_read_data[41] = 1'b0;  // bit 41
assign  imu_eqs_error_log_reg_csrbus_read_data[42] = 1'b0;  // bit 42
assign  imu_eqs_error_log_reg_csrbus_read_data[43] = 1'b0;  // bit 43
assign  imu_eqs_error_log_reg_csrbus_read_data[44] = 1'b0;  // bit 44
assign  imu_eqs_error_log_reg_csrbus_read_data[45] = 1'b0;  // bit 45
assign  imu_eqs_error_log_reg_csrbus_read_data[46] = 1'b0;  // bit 46
assign  imu_eqs_error_log_reg_csrbus_read_data[47] = 1'b0;  // bit 47
assign  imu_eqs_error_log_reg_csrbus_read_data[48] = 1'b0;  // bit 48
assign  imu_eqs_error_log_reg_csrbus_read_data[49] = 1'b0;  // bit 49
assign  imu_eqs_error_log_reg_csrbus_read_data[50] = 1'b0;  // bit 50
assign  imu_eqs_error_log_reg_csrbus_read_data[51] = 1'b0;  // bit 51
assign  imu_eqs_error_log_reg_csrbus_read_data[52] = 1'b0;  // bit 52
assign  imu_eqs_error_log_reg_csrbus_read_data[53] = 1'b0;  // bit 53
assign  imu_eqs_error_log_reg_csrbus_read_data[54] = 1'b0;  // bit 54
assign  imu_eqs_error_log_reg_csrbus_read_data[55] = 1'b0;  // bit 55
assign  imu_eqs_error_log_reg_csrbus_read_data[56] = 1'b0;  // bit 56
assign  imu_eqs_error_log_reg_csrbus_read_data[57] = 1'b0;  // bit 57
assign  imu_eqs_error_log_reg_csrbus_read_data[58] = 1'b0;  // bit 58
assign  imu_eqs_error_log_reg_csrbus_read_data[59] = 1'b0;  // bit 59
assign  imu_eqs_error_log_reg_csrbus_read_data[60] = 1'b0;  // bit 60
assign  imu_eqs_error_log_reg_csrbus_read_data[61] = 1'b0;  // bit 61
assign  imu_eqs_error_log_reg_csrbus_read_data[62] = 1'b0;  // bit 62
assign  imu_eqs_error_log_reg_csrbus_read_data[63] = 1'b0;  // bit 63

endmodule // dmu_imu_ics_csr_imu_eqs_error_log_reg_entry