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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_iss_csr.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: dmu_imu_iss_csr.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
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31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module dmu_imu_iss_csr
36 (
37 clk,
38 csrbus_addr,
39 csrbus_wr_data,
40 csrbus_wr,
41 csrbus_valid,
42 csrbus_mapped,
43 csrbus_done,
44 csrbus_read_data,
45 rst_l,
46 csrbus_src_bus,
47 csrbus_acc_vio,
48 instance_id,
49 ext_wr,
50 interrupt_mapping_20_mdo_mode_hw_read,
51 interrupt_mapping_20_v_hw_read,
52 interrupt_mapping_20_t_id_hw_read,
53 interrupt_mapping_20_int_cntrl_num_hw_read,
54 interrupt_mapping_21_mdo_mode_hw_read,
55 interrupt_mapping_21_v_hw_read,
56 interrupt_mapping_21_t_id_hw_read,
57 interrupt_mapping_21_int_cntrl_num_hw_read,
58 interrupt_mapping_22_mdo_mode_hw_read,
59 interrupt_mapping_22_v_hw_read,
60 interrupt_mapping_22_t_id_hw_read,
61 interrupt_mapping_22_int_cntrl_num_hw_read,
62 interrupt_mapping_23_mdo_mode_hw_read,
63 interrupt_mapping_23_v_hw_read,
64 interrupt_mapping_23_t_id_hw_read,
65 interrupt_mapping_23_int_cntrl_num_hw_read,
66 interrupt_mapping_24_mdo_mode_hw_read,
67 interrupt_mapping_24_v_hw_read,
68 interrupt_mapping_24_t_id_hw_read,
69 interrupt_mapping_24_int_cntrl_num_hw_read,
70 interrupt_mapping_25_mdo_mode_hw_read,
71 interrupt_mapping_25_v_hw_read,
72 interrupt_mapping_25_t_id_hw_read,
73 interrupt_mapping_25_int_cntrl_num_hw_read,
74 interrupt_mapping_26_mdo_mode_hw_read,
75 interrupt_mapping_26_v_hw_read,
76 interrupt_mapping_26_t_id_hw_read,
77 interrupt_mapping_26_int_cntrl_num_hw_read,
78 interrupt_mapping_27_mdo_mode_hw_read,
79 interrupt_mapping_27_v_hw_read,
80 interrupt_mapping_27_t_id_hw_read,
81 interrupt_mapping_27_int_cntrl_num_hw_read,
82 interrupt_mapping_28_mdo_mode_hw_read,
83 interrupt_mapping_28_v_hw_read,
84 interrupt_mapping_28_t_id_hw_read,
85 interrupt_mapping_28_int_cntrl_num_hw_read,
86 interrupt_mapping_29_mdo_mode_hw_read,
87 interrupt_mapping_29_v_hw_read,
88 interrupt_mapping_29_t_id_hw_read,
89 interrupt_mapping_29_int_cntrl_num_hw_read,
90 interrupt_mapping_30_mdo_mode_hw_read,
91 interrupt_mapping_30_v_hw_read,
92 interrupt_mapping_30_t_id_hw_read,
93 interrupt_mapping_30_int_cntrl_num_hw_read,
94 interrupt_mapping_31_mdo_mode_hw_read,
95 interrupt_mapping_31_v_hw_read,
96 interrupt_mapping_31_t_id_hw_read,
97 interrupt_mapping_31_int_cntrl_num_hw_read,
98 interrupt_mapping_32_mdo_mode_hw_read,
99 interrupt_mapping_32_v_hw_read,
100 interrupt_mapping_32_t_id_hw_read,
101 interrupt_mapping_32_int_cntrl_num_hw_read,
102 interrupt_mapping_33_mdo_mode_hw_read,
103 interrupt_mapping_33_v_hw_read,
104 interrupt_mapping_33_t_id_hw_read,
105 interrupt_mapping_33_int_cntrl_num_hw_read,
106 interrupt_mapping_34_mdo_mode_hw_read,
107 interrupt_mapping_34_v_hw_read,
108 interrupt_mapping_34_t_id_hw_read,
109 interrupt_mapping_34_int_cntrl_num_hw_read,
110 interrupt_mapping_35_mdo_mode_hw_read,
111 interrupt_mapping_35_v_hw_read,
112 interrupt_mapping_35_t_id_hw_read,
113 interrupt_mapping_35_int_cntrl_num_hw_read,
114 interrupt_mapping_36_mdo_mode_hw_read,
115 interrupt_mapping_36_v_hw_read,
116 interrupt_mapping_36_t_id_hw_read,
117 interrupt_mapping_36_int_cntrl_num_hw_read,
118 interrupt_mapping_37_mdo_mode_hw_read,
119 interrupt_mapping_37_v_hw_read,
120 interrupt_mapping_37_t_id_hw_read,
121 interrupt_mapping_37_int_cntrl_num_hw_read,
122 interrupt_mapping_38_mdo_mode_hw_read,
123 interrupt_mapping_38_v_hw_read,
124 interrupt_mapping_38_t_id_hw_read,
125 interrupt_mapping_38_int_cntrl_num_hw_read,
126 interrupt_mapping_39_mdo_mode_hw_read,
127 interrupt_mapping_39_v_hw_read,
128 interrupt_mapping_39_t_id_hw_read,
129 interrupt_mapping_39_int_cntrl_num_hw_read,
130 interrupt_mapping_40_mdo_mode_hw_read,
131 interrupt_mapping_40_v_hw_read,
132 interrupt_mapping_40_t_id_hw_read,
133 interrupt_mapping_40_int_cntrl_num_hw_read,
134 interrupt_mapping_41_mdo_mode_hw_read,
135 interrupt_mapping_41_v_hw_read,
136 interrupt_mapping_41_t_id_hw_read,
137 interrupt_mapping_41_int_cntrl_num_hw_read,
138 interrupt_mapping_42_mdo_mode_hw_read,
139 interrupt_mapping_42_v_hw_read,
140 interrupt_mapping_42_t_id_hw_read,
141 interrupt_mapping_42_int_cntrl_num_hw_read,
142 interrupt_mapping_43_mdo_mode_hw_read,
143 interrupt_mapping_43_v_hw_read,
144 interrupt_mapping_43_t_id_hw_read,
145 interrupt_mapping_43_int_cntrl_num_hw_read,
146 interrupt_mapping_44_mdo_mode_hw_read,
147 interrupt_mapping_44_v_hw_read,
148 interrupt_mapping_44_t_id_hw_read,
149 interrupt_mapping_44_int_cntrl_num_hw_read,
150 interrupt_mapping_45_mdo_mode_hw_read,
151 interrupt_mapping_45_v_hw_read,
152 interrupt_mapping_45_t_id_hw_read,
153 interrupt_mapping_45_int_cntrl_num_hw_read,
154 interrupt_mapping_46_mdo_mode_hw_read,
155 interrupt_mapping_46_v_hw_read,
156 interrupt_mapping_46_t_id_hw_read,
157 interrupt_mapping_46_int_cntrl_num_hw_read,
158 interrupt_mapping_47_mdo_mode_hw_read,
159 interrupt_mapping_47_v_hw_read,
160 interrupt_mapping_47_t_id_hw_read,
161 interrupt_mapping_47_int_cntrl_num_hw_read,
162 interrupt_mapping_48_mdo_mode_hw_read,
163 interrupt_mapping_48_v_hw_read,
164 interrupt_mapping_48_t_id_hw_read,
165 interrupt_mapping_48_int_cntrl_num_hw_read,
166 interrupt_mapping_49_mdo_mode_hw_read,
167 interrupt_mapping_49_v_hw_read,
168 interrupt_mapping_49_t_id_hw_read,
169 interrupt_mapping_49_int_cntrl_num_hw_read,
170 interrupt_mapping_50_mdo_mode_hw_read,
171 interrupt_mapping_50_v_hw_read,
172 interrupt_mapping_50_t_id_hw_read,
173 interrupt_mapping_50_int_cntrl_num_hw_read,
174 interrupt_mapping_51_mdo_mode_hw_read,
175 interrupt_mapping_51_v_hw_read,
176 interrupt_mapping_51_t_id_hw_read,
177 interrupt_mapping_51_int_cntrl_num_hw_read,
178 interrupt_mapping_52_mdo_mode_hw_read,
179 interrupt_mapping_52_v_hw_read,
180 interrupt_mapping_52_t_id_hw_read,
181 interrupt_mapping_52_int_cntrl_num_hw_read,
182 interrupt_mapping_53_mdo_mode_hw_read,
183 interrupt_mapping_53_v_hw_read,
184 interrupt_mapping_53_t_id_hw_read,
185 interrupt_mapping_53_int_cntrl_num_hw_read,
186 interrupt_mapping_54_mdo_mode_hw_read,
187 interrupt_mapping_54_v_hw_read,
188 interrupt_mapping_54_t_id_hw_read,
189 interrupt_mapping_54_int_cntrl_num_hw_read,
190 interrupt_mapping_55_mdo_mode_hw_read,
191 interrupt_mapping_55_v_hw_read,
192 interrupt_mapping_55_t_id_hw_read,
193 interrupt_mapping_55_int_cntrl_num_hw_read,
194 interrupt_mapping_56_mdo_mode_hw_read,
195 interrupt_mapping_56_v_hw_read,
196 interrupt_mapping_56_t_id_hw_read,
197 interrupt_mapping_56_int_cntrl_num_hw_read,
198 interrupt_mapping_57_mdo_mode_hw_read,
199 interrupt_mapping_57_v_hw_read,
200 interrupt_mapping_57_t_id_hw_read,
201 interrupt_mapping_57_int_cntrl_num_hw_read,
202 interrupt_mapping_58_mdo_mode_hw_read,
203 interrupt_mapping_58_v_hw_read,
204 interrupt_mapping_58_t_id_hw_read,
205 interrupt_mapping_58_int_cntrl_num_hw_read,
206 interrupt_mapping_59_mdo_mode_hw_read,
207 interrupt_mapping_59_v_hw_read,
208 interrupt_mapping_59_t_id_hw_read,
209 interrupt_mapping_59_int_cntrl_num_hw_read,
210 interrupt_mapping_62_mdo_mode_hw_read,
211 interrupt_mapping_62_v_hw_read,
212 interrupt_mapping_62_t_id_hw_read,
213 interrupt_mapping_62_int_cntrl_num_hw_read,
214 interrupt_mapping_63_mdo_mode_hw_read,
215 interrupt_mapping_63_v_hw_read,
216 interrupt_mapping_63_t_id_hw_read,
217 interrupt_mapping_63_int_cntrl_num_hw_read,
218 clr_int_reg_20_int_state_ext_wr_data,
219 clr_int_reg_20_ext_select,
220 clr_int_reg_20_int_state_ext_read_data,
221 clr_int_reg_21_int_state_ext_wr_data,
222 clr_int_reg_21_ext_select,
223 clr_int_reg_21_int_state_ext_read_data,
224 clr_int_reg_22_int_state_ext_wr_data,
225 clr_int_reg_22_ext_select,
226 clr_int_reg_22_int_state_ext_read_data,
227 clr_int_reg_23_int_state_ext_wr_data,
228 clr_int_reg_23_ext_select,
229 clr_int_reg_23_int_state_ext_read_data,
230 clr_int_reg_24_int_state_ext_wr_data,
231 clr_int_reg_24_ext_select,
232 clr_int_reg_24_int_state_ext_read_data,
233 clr_int_reg_25_int_state_ext_wr_data,
234 clr_int_reg_25_ext_select,
235 clr_int_reg_25_int_state_ext_read_data,
236 clr_int_reg_26_int_state_ext_wr_data,
237 clr_int_reg_26_ext_select,
238 clr_int_reg_26_int_state_ext_read_data,
239 clr_int_reg_27_int_state_ext_wr_data,
240 clr_int_reg_27_ext_select,
241 clr_int_reg_27_int_state_ext_read_data,
242 clr_int_reg_28_int_state_ext_wr_data,
243 clr_int_reg_28_ext_select,
244 clr_int_reg_28_int_state_ext_read_data,
245 clr_int_reg_29_int_state_ext_wr_data,
246 clr_int_reg_29_ext_select,
247 clr_int_reg_29_int_state_ext_read_data,
248 clr_int_reg_30_int_state_ext_wr_data,
249 clr_int_reg_30_ext_select,
250 clr_int_reg_30_int_state_ext_read_data,
251 clr_int_reg_31_int_state_ext_wr_data,
252 clr_int_reg_31_ext_select,
253 clr_int_reg_31_int_state_ext_read_data,
254 clr_int_reg_32_int_state_ext_wr_data,
255 clr_int_reg_32_ext_select,
256 clr_int_reg_32_int_state_ext_read_data,
257 clr_int_reg_33_int_state_ext_wr_data,
258 clr_int_reg_33_ext_select,
259 clr_int_reg_33_int_state_ext_read_data,
260 clr_int_reg_34_int_state_ext_wr_data,
261 clr_int_reg_34_ext_select,
262 clr_int_reg_34_int_state_ext_read_data,
263 clr_int_reg_35_int_state_ext_wr_data,
264 clr_int_reg_35_ext_select,
265 clr_int_reg_35_int_state_ext_read_data,
266 clr_int_reg_36_int_state_ext_wr_data,
267 clr_int_reg_36_ext_select,
268 clr_int_reg_36_int_state_ext_read_data,
269 clr_int_reg_37_int_state_ext_wr_data,
270 clr_int_reg_37_ext_select,
271 clr_int_reg_37_int_state_ext_read_data,
272 clr_int_reg_38_int_state_ext_wr_data,
273 clr_int_reg_38_ext_select,
274 clr_int_reg_38_int_state_ext_read_data,
275 clr_int_reg_39_int_state_ext_wr_data,
276 clr_int_reg_39_ext_select,
277 clr_int_reg_39_int_state_ext_read_data,
278 clr_int_reg_40_int_state_ext_wr_data,
279 clr_int_reg_40_ext_select,
280 clr_int_reg_40_int_state_ext_read_data,
281 clr_int_reg_41_int_state_ext_wr_data,
282 clr_int_reg_41_ext_select,
283 clr_int_reg_41_int_state_ext_read_data,
284 clr_int_reg_42_int_state_ext_wr_data,
285 clr_int_reg_42_ext_select,
286 clr_int_reg_42_int_state_ext_read_data,
287 clr_int_reg_43_int_state_ext_wr_data,
288 clr_int_reg_43_ext_select,
289 clr_int_reg_43_int_state_ext_read_data,
290 clr_int_reg_44_int_state_ext_wr_data,
291 clr_int_reg_44_ext_select,
292 clr_int_reg_44_int_state_ext_read_data,
293 clr_int_reg_45_int_state_ext_wr_data,
294 clr_int_reg_45_ext_select,
295 clr_int_reg_45_int_state_ext_read_data,
296 clr_int_reg_46_int_state_ext_wr_data,
297 clr_int_reg_46_ext_select,
298 clr_int_reg_46_int_state_ext_read_data,
299 clr_int_reg_47_int_state_ext_wr_data,
300 clr_int_reg_47_ext_select,
301 clr_int_reg_47_int_state_ext_read_data,
302 clr_int_reg_48_int_state_ext_wr_data,
303 clr_int_reg_48_ext_select,
304 clr_int_reg_48_int_state_ext_read_data,
305 clr_int_reg_49_int_state_ext_wr_data,
306 clr_int_reg_49_ext_select,
307 clr_int_reg_49_int_state_ext_read_data,
308 clr_int_reg_50_int_state_ext_wr_data,
309 clr_int_reg_50_ext_select,
310 clr_int_reg_50_int_state_ext_read_data,
311 clr_int_reg_51_int_state_ext_wr_data,
312 clr_int_reg_51_ext_select,
313 clr_int_reg_51_int_state_ext_read_data,
314 clr_int_reg_52_int_state_ext_wr_data,
315 clr_int_reg_52_ext_select,
316 clr_int_reg_52_int_state_ext_read_data,
317 clr_int_reg_53_int_state_ext_wr_data,
318 clr_int_reg_53_ext_select,
319 clr_int_reg_53_int_state_ext_read_data,
320 clr_int_reg_54_int_state_ext_wr_data,
321 clr_int_reg_54_ext_select,
322 clr_int_reg_54_int_state_ext_read_data,
323 clr_int_reg_55_int_state_ext_wr_data,
324 clr_int_reg_55_ext_select,
325 clr_int_reg_55_int_state_ext_read_data,
326 clr_int_reg_56_int_state_ext_wr_data,
327 clr_int_reg_56_ext_select,
328 clr_int_reg_56_int_state_ext_read_data,
329 clr_int_reg_57_int_state_ext_wr_data,
330 clr_int_reg_57_ext_select,
331 clr_int_reg_57_int_state_ext_read_data,
332 clr_int_reg_58_int_state_ext_wr_data,
333 clr_int_reg_58_ext_select,
334 clr_int_reg_58_int_state_ext_read_data,
335 clr_int_reg_59_int_state_ext_wr_data,
336 clr_int_reg_59_ext_select,
337 clr_int_reg_59_int_state_ext_read_data,
338 clr_int_reg_62_int_state_ext_wr_data,
339 clr_int_reg_62_ext_select,
340 clr_int_reg_62_int_state_ext_read_data,
341 clr_int_reg_63_int_state_ext_wr_data,
342 clr_int_reg_63_ext_select,
343 clr_int_reg_63_int_state_ext_read_data,
344 interrupt_retry_timer_limit_hw_read,
345 interrupt_state_status_1_state_ext_read_data,
346 interrupt_state_status_2_state_ext_read_data
347 );
348
349//====================================================
350// Polarity declarations
351//====================================================
352input clk; // Clock signal
353input [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
354input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
355input csrbus_wr; // Read/Write signal
356input csrbus_valid; // Valid address
357output csrbus_mapped; // Address is mapped
358output csrbus_done; // Operation is done
359output [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
360input rst_l; // Reset signal
361input [1:0] csrbus_src_bus; // Source bus
362output csrbus_acc_vio; // Violation signal
363input instance_id; // Instance ID
364output ext_wr; // When one, csr operation is a write. When zero, operation is a
365 // read.
366output interrupt_mapping_20_mdo_mode_hw_read; // This signal provides the
367 // current value of
368 // interrupt_mapping_20_mdo_mode.
369output interrupt_mapping_20_v_hw_read; // This signal provides the current
370 // value of interrupt_mapping_20_v.
371output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_INT_SLC] interrupt_mapping_20_t_id_hw_read;
372 // This signal provides the current value of interrupt_mapping_20_t_id.
373output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_20_int_cntrl_num_hw_read;
374 // This signal provides the current value of
375 // interrupt_mapping_20_int_cntrl_num.
376output interrupt_mapping_21_mdo_mode_hw_read; // This signal provides the
377 // current value of
378 // interrupt_mapping_21_mdo_mode.
379output interrupt_mapping_21_v_hw_read; // This signal provides the current
380 // value of interrupt_mapping_21_v.
381output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_INT_SLC] interrupt_mapping_21_t_id_hw_read;
382 // This signal provides the current value of interrupt_mapping_21_t_id.
383output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_21_int_cntrl_num_hw_read;
384 // This signal provides the current value of
385 // interrupt_mapping_21_int_cntrl_num.
386output interrupt_mapping_22_mdo_mode_hw_read; // This signal provides the
387 // current value of
388 // interrupt_mapping_22_mdo_mode.
389output interrupt_mapping_22_v_hw_read; // This signal provides the current
390 // value of interrupt_mapping_22_v.
391output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_INT_SLC] interrupt_mapping_22_t_id_hw_read;
392 // This signal provides the current value of interrupt_mapping_22_t_id.
393output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_22_int_cntrl_num_hw_read;
394 // This signal provides the current value of
395 // interrupt_mapping_22_int_cntrl_num.
396output interrupt_mapping_23_mdo_mode_hw_read; // This signal provides the
397 // current value of
398 // interrupt_mapping_23_mdo_mode.
399output interrupt_mapping_23_v_hw_read; // This signal provides the current
400 // value of interrupt_mapping_23_v.
401output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_INT_SLC] interrupt_mapping_23_t_id_hw_read;
402 // This signal provides the current value of interrupt_mapping_23_t_id.
403output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_23_int_cntrl_num_hw_read;
404 // This signal provides the current value of
405 // interrupt_mapping_23_int_cntrl_num.
406output interrupt_mapping_24_mdo_mode_hw_read; // This signal provides the
407 // current value of
408 // interrupt_mapping_24_mdo_mode.
409output interrupt_mapping_24_v_hw_read; // This signal provides the current
410 // value of interrupt_mapping_24_v.
411output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_INT_SLC] interrupt_mapping_24_t_id_hw_read;
412 // This signal provides the current value of interrupt_mapping_24_t_id.
413output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_24_int_cntrl_num_hw_read;
414 // This signal provides the current value of
415 // interrupt_mapping_24_int_cntrl_num.
416output interrupt_mapping_25_mdo_mode_hw_read; // This signal provides the
417 // current value of
418 // interrupt_mapping_25_mdo_mode.
419output interrupt_mapping_25_v_hw_read; // This signal provides the current
420 // value of interrupt_mapping_25_v.
421output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_INT_SLC] interrupt_mapping_25_t_id_hw_read;
422 // This signal provides the current value of interrupt_mapping_25_t_id.
423output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_25_int_cntrl_num_hw_read;
424 // This signal provides the current value of
425 // interrupt_mapping_25_int_cntrl_num.
426output interrupt_mapping_26_mdo_mode_hw_read; // This signal provides the
427 // current value of
428 // interrupt_mapping_26_mdo_mode.
429output interrupt_mapping_26_v_hw_read; // This signal provides the current
430 // value of interrupt_mapping_26_v.
431output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_INT_SLC] interrupt_mapping_26_t_id_hw_read;
432 // This signal provides the current value of interrupt_mapping_26_t_id.
433output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_26_int_cntrl_num_hw_read;
434 // This signal provides the current value of
435 // interrupt_mapping_26_int_cntrl_num.
436output interrupt_mapping_27_mdo_mode_hw_read; // This signal provides the
437 // current value of
438 // interrupt_mapping_27_mdo_mode.
439output interrupt_mapping_27_v_hw_read; // This signal provides the current
440 // value of interrupt_mapping_27_v.
441output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_INT_SLC] interrupt_mapping_27_t_id_hw_read;
442 // This signal provides the current value of interrupt_mapping_27_t_id.
443output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_27_int_cntrl_num_hw_read;
444 // This signal provides the current value of
445 // interrupt_mapping_27_int_cntrl_num.
446output interrupt_mapping_28_mdo_mode_hw_read; // This signal provides the
447 // current value of
448 // interrupt_mapping_28_mdo_mode.
449output interrupt_mapping_28_v_hw_read; // This signal provides the current
450 // value of interrupt_mapping_28_v.
451output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_INT_SLC] interrupt_mapping_28_t_id_hw_read;
452 // This signal provides the current value of interrupt_mapping_28_t_id.
453output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_28_int_cntrl_num_hw_read;
454 // This signal provides the current value of
455 // interrupt_mapping_28_int_cntrl_num.
456output interrupt_mapping_29_mdo_mode_hw_read; // This signal provides the
457 // current value of
458 // interrupt_mapping_29_mdo_mode.
459output interrupt_mapping_29_v_hw_read; // This signal provides the current
460 // value of interrupt_mapping_29_v.
461output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_INT_SLC] interrupt_mapping_29_t_id_hw_read;
462 // This signal provides the current value of interrupt_mapping_29_t_id.
463output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_29_int_cntrl_num_hw_read;
464 // This signal provides the current value of
465 // interrupt_mapping_29_int_cntrl_num.
466output interrupt_mapping_30_mdo_mode_hw_read; // This signal provides the
467 // current value of
468 // interrupt_mapping_30_mdo_mode.
469output interrupt_mapping_30_v_hw_read; // This signal provides the current
470 // value of interrupt_mapping_30_v.
471output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_INT_SLC] interrupt_mapping_30_t_id_hw_read;
472 // This signal provides the current value of interrupt_mapping_30_t_id.
473output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_30_int_cntrl_num_hw_read;
474 // This signal provides the current value of
475 // interrupt_mapping_30_int_cntrl_num.
476output interrupt_mapping_31_mdo_mode_hw_read; // This signal provides the
477 // current value of
478 // interrupt_mapping_31_mdo_mode.
479output interrupt_mapping_31_v_hw_read; // This signal provides the current
480 // value of interrupt_mapping_31_v.
481output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_INT_SLC] interrupt_mapping_31_t_id_hw_read;
482 // This signal provides the current value of interrupt_mapping_31_t_id.
483output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_31_int_cntrl_num_hw_read;
484 // This signal provides the current value of
485 // interrupt_mapping_31_int_cntrl_num.
486output interrupt_mapping_32_mdo_mode_hw_read; // This signal provides the
487 // current value of
488 // interrupt_mapping_32_mdo_mode.
489output interrupt_mapping_32_v_hw_read; // This signal provides the current
490 // value of interrupt_mapping_32_v.
491output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_INT_SLC] interrupt_mapping_32_t_id_hw_read;
492 // This signal provides the current value of interrupt_mapping_32_t_id.
493output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_32_int_cntrl_num_hw_read;
494 // This signal provides the current value of
495 // interrupt_mapping_32_int_cntrl_num.
496output interrupt_mapping_33_mdo_mode_hw_read; // This signal provides the
497 // current value of
498 // interrupt_mapping_33_mdo_mode.
499output interrupt_mapping_33_v_hw_read; // This signal provides the current
500 // value of interrupt_mapping_33_v.
501output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_INT_SLC] interrupt_mapping_33_t_id_hw_read;
502 // This signal provides the current value of interrupt_mapping_33_t_id.
503output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_33_int_cntrl_num_hw_read;
504 // This signal provides the current value of
505 // interrupt_mapping_33_int_cntrl_num.
506output interrupt_mapping_34_mdo_mode_hw_read; // This signal provides the
507 // current value of
508 // interrupt_mapping_34_mdo_mode.
509output interrupt_mapping_34_v_hw_read; // This signal provides the current
510 // value of interrupt_mapping_34_v.
511output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_INT_SLC] interrupt_mapping_34_t_id_hw_read;
512 // This signal provides the current value of interrupt_mapping_34_t_id.
513output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_34_int_cntrl_num_hw_read;
514 // This signal provides the current value of
515 // interrupt_mapping_34_int_cntrl_num.
516output interrupt_mapping_35_mdo_mode_hw_read; // This signal provides the
517 // current value of
518 // interrupt_mapping_35_mdo_mode.
519output interrupt_mapping_35_v_hw_read; // This signal provides the current
520 // value of interrupt_mapping_35_v.
521output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_INT_SLC] interrupt_mapping_35_t_id_hw_read;
522 // This signal provides the current value of interrupt_mapping_35_t_id.
523output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_35_int_cntrl_num_hw_read;
524 // This signal provides the current value of
525 // interrupt_mapping_35_int_cntrl_num.
526output interrupt_mapping_36_mdo_mode_hw_read; // This signal provides the
527 // current value of
528 // interrupt_mapping_36_mdo_mode.
529output interrupt_mapping_36_v_hw_read; // This signal provides the current
530 // value of interrupt_mapping_36_v.
531output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_INT_SLC] interrupt_mapping_36_t_id_hw_read;
532 // This signal provides the current value of interrupt_mapping_36_t_id.
533output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_36_int_cntrl_num_hw_read;
534 // This signal provides the current value of
535 // interrupt_mapping_36_int_cntrl_num.
536output interrupt_mapping_37_mdo_mode_hw_read; // This signal provides the
537 // current value of
538 // interrupt_mapping_37_mdo_mode.
539output interrupt_mapping_37_v_hw_read; // This signal provides the current
540 // value of interrupt_mapping_37_v.
541output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_INT_SLC] interrupt_mapping_37_t_id_hw_read;
542 // This signal provides the current value of interrupt_mapping_37_t_id.
543output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_37_int_cntrl_num_hw_read;
544 // This signal provides the current value of
545 // interrupt_mapping_37_int_cntrl_num.
546output interrupt_mapping_38_mdo_mode_hw_read; // This signal provides the
547 // current value of
548 // interrupt_mapping_38_mdo_mode.
549output interrupt_mapping_38_v_hw_read; // This signal provides the current
550 // value of interrupt_mapping_38_v.
551output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_INT_SLC] interrupt_mapping_38_t_id_hw_read;
552 // This signal provides the current value of interrupt_mapping_38_t_id.
553output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_38_int_cntrl_num_hw_read;
554 // This signal provides the current value of
555 // interrupt_mapping_38_int_cntrl_num.
556output interrupt_mapping_39_mdo_mode_hw_read; // This signal provides the
557 // current value of
558 // interrupt_mapping_39_mdo_mode.
559output interrupt_mapping_39_v_hw_read; // This signal provides the current
560 // value of interrupt_mapping_39_v.
561output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_INT_SLC] interrupt_mapping_39_t_id_hw_read;
562 // This signal provides the current value of interrupt_mapping_39_t_id.
563output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_39_int_cntrl_num_hw_read;
564 // This signal provides the current value of
565 // interrupt_mapping_39_int_cntrl_num.
566output interrupt_mapping_40_mdo_mode_hw_read; // This signal provides the
567 // current value of
568 // interrupt_mapping_40_mdo_mode.
569output interrupt_mapping_40_v_hw_read; // This signal provides the current
570 // value of interrupt_mapping_40_v.
571output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_INT_SLC] interrupt_mapping_40_t_id_hw_read;
572 // This signal provides the current value of interrupt_mapping_40_t_id.
573output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_40_int_cntrl_num_hw_read;
574 // This signal provides the current value of
575 // interrupt_mapping_40_int_cntrl_num.
576output interrupt_mapping_41_mdo_mode_hw_read; // This signal provides the
577 // current value of
578 // interrupt_mapping_41_mdo_mode.
579output interrupt_mapping_41_v_hw_read; // This signal provides the current
580 // value of interrupt_mapping_41_v.
581output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_INT_SLC] interrupt_mapping_41_t_id_hw_read;
582 // This signal provides the current value of interrupt_mapping_41_t_id.
583output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_41_int_cntrl_num_hw_read;
584 // This signal provides the current value of
585 // interrupt_mapping_41_int_cntrl_num.
586output interrupt_mapping_42_mdo_mode_hw_read; // This signal provides the
587 // current value of
588 // interrupt_mapping_42_mdo_mode.
589output interrupt_mapping_42_v_hw_read; // This signal provides the current
590 // value of interrupt_mapping_42_v.
591output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_INT_SLC] interrupt_mapping_42_t_id_hw_read;
592 // This signal provides the current value of interrupt_mapping_42_t_id.
593output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_42_int_cntrl_num_hw_read;
594 // This signal provides the current value of
595 // interrupt_mapping_42_int_cntrl_num.
596output interrupt_mapping_43_mdo_mode_hw_read; // This signal provides the
597 // current value of
598 // interrupt_mapping_43_mdo_mode.
599output interrupt_mapping_43_v_hw_read; // This signal provides the current
600 // value of interrupt_mapping_43_v.
601output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_INT_SLC] interrupt_mapping_43_t_id_hw_read;
602 // This signal provides the current value of interrupt_mapping_43_t_id.
603output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_43_int_cntrl_num_hw_read;
604 // This signal provides the current value of
605 // interrupt_mapping_43_int_cntrl_num.
606output interrupt_mapping_44_mdo_mode_hw_read; // This signal provides the
607 // current value of
608 // interrupt_mapping_44_mdo_mode.
609output interrupt_mapping_44_v_hw_read; // This signal provides the current
610 // value of interrupt_mapping_44_v.
611output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_INT_SLC] interrupt_mapping_44_t_id_hw_read;
612 // This signal provides the current value of interrupt_mapping_44_t_id.
613output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_44_int_cntrl_num_hw_read;
614 // This signal provides the current value of
615 // interrupt_mapping_44_int_cntrl_num.
616output interrupt_mapping_45_mdo_mode_hw_read; // This signal provides the
617 // current value of
618 // interrupt_mapping_45_mdo_mode.
619output interrupt_mapping_45_v_hw_read; // This signal provides the current
620 // value of interrupt_mapping_45_v.
621output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_INT_SLC] interrupt_mapping_45_t_id_hw_read;
622 // This signal provides the current value of interrupt_mapping_45_t_id.
623output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_45_int_cntrl_num_hw_read;
624 // This signal provides the current value of
625 // interrupt_mapping_45_int_cntrl_num.
626output interrupt_mapping_46_mdo_mode_hw_read; // This signal provides the
627 // current value of
628 // interrupt_mapping_46_mdo_mode.
629output interrupt_mapping_46_v_hw_read; // This signal provides the current
630 // value of interrupt_mapping_46_v.
631output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_INT_SLC] interrupt_mapping_46_t_id_hw_read;
632 // This signal provides the current value of interrupt_mapping_46_t_id.
633output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_46_int_cntrl_num_hw_read;
634 // This signal provides the current value of
635 // interrupt_mapping_46_int_cntrl_num.
636output interrupt_mapping_47_mdo_mode_hw_read; // This signal provides the
637 // current value of
638 // interrupt_mapping_47_mdo_mode.
639output interrupt_mapping_47_v_hw_read; // This signal provides the current
640 // value of interrupt_mapping_47_v.
641output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_INT_SLC] interrupt_mapping_47_t_id_hw_read;
642 // This signal provides the current value of interrupt_mapping_47_t_id.
643output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_47_int_cntrl_num_hw_read;
644 // This signal provides the current value of
645 // interrupt_mapping_47_int_cntrl_num.
646output interrupt_mapping_48_mdo_mode_hw_read; // This signal provides the
647 // current value of
648 // interrupt_mapping_48_mdo_mode.
649output interrupt_mapping_48_v_hw_read; // This signal provides the current
650 // value of interrupt_mapping_48_v.
651output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_INT_SLC] interrupt_mapping_48_t_id_hw_read;
652 // This signal provides the current value of interrupt_mapping_48_t_id.
653output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_48_int_cntrl_num_hw_read;
654 // This signal provides the current value of
655 // interrupt_mapping_48_int_cntrl_num.
656output interrupt_mapping_49_mdo_mode_hw_read; // This signal provides the
657 // current value of
658 // interrupt_mapping_49_mdo_mode.
659output interrupt_mapping_49_v_hw_read; // This signal provides the current
660 // value of interrupt_mapping_49_v.
661output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_INT_SLC] interrupt_mapping_49_t_id_hw_read;
662 // This signal provides the current value of interrupt_mapping_49_t_id.
663output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_49_int_cntrl_num_hw_read;
664 // This signal provides the current value of
665 // interrupt_mapping_49_int_cntrl_num.
666output interrupt_mapping_50_mdo_mode_hw_read; // This signal provides the
667 // current value of
668 // interrupt_mapping_50_mdo_mode.
669output interrupt_mapping_50_v_hw_read; // This signal provides the current
670 // value of interrupt_mapping_50_v.
671output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_INT_SLC] interrupt_mapping_50_t_id_hw_read;
672 // This signal provides the current value of interrupt_mapping_50_t_id.
673output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_50_int_cntrl_num_hw_read;
674 // This signal provides the current value of
675 // interrupt_mapping_50_int_cntrl_num.
676output interrupt_mapping_51_mdo_mode_hw_read; // This signal provides the
677 // current value of
678 // interrupt_mapping_51_mdo_mode.
679output interrupt_mapping_51_v_hw_read; // This signal provides the current
680 // value of interrupt_mapping_51_v.
681output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_INT_SLC] interrupt_mapping_51_t_id_hw_read;
682 // This signal provides the current value of interrupt_mapping_51_t_id.
683output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_51_int_cntrl_num_hw_read;
684 // This signal provides the current value of
685 // interrupt_mapping_51_int_cntrl_num.
686output interrupt_mapping_52_mdo_mode_hw_read; // This signal provides the
687 // current value of
688 // interrupt_mapping_52_mdo_mode.
689output interrupt_mapping_52_v_hw_read; // This signal provides the current
690 // value of interrupt_mapping_52_v.
691output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_INT_SLC] interrupt_mapping_52_t_id_hw_read;
692 // This signal provides the current value of interrupt_mapping_52_t_id.
693output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_52_int_cntrl_num_hw_read;
694 // This signal provides the current value of
695 // interrupt_mapping_52_int_cntrl_num.
696output interrupt_mapping_53_mdo_mode_hw_read; // This signal provides the
697 // current value of
698 // interrupt_mapping_53_mdo_mode.
699output interrupt_mapping_53_v_hw_read; // This signal provides the current
700 // value of interrupt_mapping_53_v.
701output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_INT_SLC] interrupt_mapping_53_t_id_hw_read;
702 // This signal provides the current value of interrupt_mapping_53_t_id.
703output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_53_int_cntrl_num_hw_read;
704 // This signal provides the current value of
705 // interrupt_mapping_53_int_cntrl_num.
706output interrupt_mapping_54_mdo_mode_hw_read; // This signal provides the
707 // current value of
708 // interrupt_mapping_54_mdo_mode.
709output interrupt_mapping_54_v_hw_read; // This signal provides the current
710 // value of interrupt_mapping_54_v.
711output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_INT_SLC] interrupt_mapping_54_t_id_hw_read;
712 // This signal provides the current value of interrupt_mapping_54_t_id.
713output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_54_int_cntrl_num_hw_read;
714 // This signal provides the current value of
715 // interrupt_mapping_54_int_cntrl_num.
716output interrupt_mapping_55_mdo_mode_hw_read; // This signal provides the
717 // current value of
718 // interrupt_mapping_55_mdo_mode.
719output interrupt_mapping_55_v_hw_read; // This signal provides the current
720 // value of interrupt_mapping_55_v.
721output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_INT_SLC] interrupt_mapping_55_t_id_hw_read;
722 // This signal provides the current value of interrupt_mapping_55_t_id.
723output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_55_int_cntrl_num_hw_read;
724 // This signal provides the current value of
725 // interrupt_mapping_55_int_cntrl_num.
726output interrupt_mapping_56_mdo_mode_hw_read; // This signal provides the
727 // current value of
728 // interrupt_mapping_56_mdo_mode.
729output interrupt_mapping_56_v_hw_read; // This signal provides the current
730 // value of interrupt_mapping_56_v.
731output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_INT_SLC] interrupt_mapping_56_t_id_hw_read;
732 // This signal provides the current value of interrupt_mapping_56_t_id.
733output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_56_int_cntrl_num_hw_read;
734 // This signal provides the current value of
735 // interrupt_mapping_56_int_cntrl_num.
736output interrupt_mapping_57_mdo_mode_hw_read; // This signal provides the
737 // current value of
738 // interrupt_mapping_57_mdo_mode.
739output interrupt_mapping_57_v_hw_read; // This signal provides the current
740 // value of interrupt_mapping_57_v.
741output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_INT_SLC] interrupt_mapping_57_t_id_hw_read;
742 // This signal provides the current value of interrupt_mapping_57_t_id.
743output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_57_int_cntrl_num_hw_read;
744 // This signal provides the current value of
745 // interrupt_mapping_57_int_cntrl_num.
746output interrupt_mapping_58_mdo_mode_hw_read; // This signal provides the
747 // current value of
748 // interrupt_mapping_58_mdo_mode.
749output interrupt_mapping_58_v_hw_read; // This signal provides the current
750 // value of interrupt_mapping_58_v.
751output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_INT_SLC] interrupt_mapping_58_t_id_hw_read;
752 // This signal provides the current value of interrupt_mapping_58_t_id.
753output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_58_int_cntrl_num_hw_read;
754 // This signal provides the current value of
755 // interrupt_mapping_58_int_cntrl_num.
756output interrupt_mapping_59_mdo_mode_hw_read; // This signal provides the
757 // current value of
758 // interrupt_mapping_59_mdo_mode.
759output interrupt_mapping_59_v_hw_read; // This signal provides the current
760 // value of interrupt_mapping_59_v.
761output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_INT_SLC] interrupt_mapping_59_t_id_hw_read;
762 // This signal provides the current value of interrupt_mapping_59_t_id.
763output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_59_int_cntrl_num_hw_read;
764 // This signal provides the current value of
765 // interrupt_mapping_59_int_cntrl_num.
766output interrupt_mapping_62_mdo_mode_hw_read; // This signal provides the
767 // current value of
768 // interrupt_mapping_62_mdo_mode.
769output interrupt_mapping_62_v_hw_read; // This signal provides the current
770 // value of interrupt_mapping_62_v.
771output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_INT_SLC] interrupt_mapping_62_t_id_hw_read;
772 // This signal provides the current value of interrupt_mapping_62_t_id.
773output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_62_int_cntrl_num_hw_read;
774 // This signal provides the current value of
775 // interrupt_mapping_62_int_cntrl_num.
776output interrupt_mapping_63_mdo_mode_hw_read; // This signal provides the
777 // current value of
778 // interrupt_mapping_63_mdo_mode.
779output interrupt_mapping_63_v_hw_read; // This signal provides the current
780 // value of interrupt_mapping_63_v.
781output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_INT_SLC] interrupt_mapping_63_t_id_hw_read;
782 // This signal provides the current value of interrupt_mapping_63_t_id.
783output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_63_int_cntrl_num_hw_read;
784 // This signal provides the current value of
785 // interrupt_mapping_63_int_cntrl_num.
786output [1:0] clr_int_reg_20_int_state_ext_wr_data; // Provides SW write data
787 // for external register
788 // "clr_int_reg_20", field
789 // "int_state"
790output clr_int_reg_20_ext_select; // When set, register clr_int_reg_20 is
791 // selected. This signal is a pulse.
792input [1:0] clr_int_reg_20_int_state_ext_read_data; // Ext read data (decode)
793output [1:0] clr_int_reg_21_int_state_ext_wr_data; // Provides SW write data
794 // for external register
795 // "clr_int_reg_21", field
796 // "int_state"
797output clr_int_reg_21_ext_select; // When set, register clr_int_reg_21 is
798 // selected. This signal is a pulse.
799input [1:0] clr_int_reg_21_int_state_ext_read_data; // Ext read data (decode)
800output [1:0] clr_int_reg_22_int_state_ext_wr_data; // Provides SW write data
801 // for external register
802 // "clr_int_reg_22", field
803 // "int_state"
804output clr_int_reg_22_ext_select; // When set, register clr_int_reg_22 is
805 // selected. This signal is a pulse.
806input [1:0] clr_int_reg_22_int_state_ext_read_data; // Ext read data (decode)
807output [1:0] clr_int_reg_23_int_state_ext_wr_data; // Provides SW write data
808 // for external register
809 // "clr_int_reg_23", field
810 // "int_state"
811output clr_int_reg_23_ext_select; // When set, register clr_int_reg_23 is
812 // selected. This signal is a pulse.
813input [1:0] clr_int_reg_23_int_state_ext_read_data; // Ext read data (decode)
814output [1:0] clr_int_reg_24_int_state_ext_wr_data; // Provides SW write data
815 // for external register
816 // "clr_int_reg_24", field
817 // "int_state"
818output clr_int_reg_24_ext_select; // When set, register clr_int_reg_24 is
819 // selected. This signal is a pulse.
820input [1:0] clr_int_reg_24_int_state_ext_read_data; // Ext read data (decode)
821output [1:0] clr_int_reg_25_int_state_ext_wr_data; // Provides SW write data
822 // for external register
823 // "clr_int_reg_25", field
824 // "int_state"
825output clr_int_reg_25_ext_select; // When set, register clr_int_reg_25 is
826 // selected. This signal is a pulse.
827input [1:0] clr_int_reg_25_int_state_ext_read_data; // Ext read data (decode)
828output [1:0] clr_int_reg_26_int_state_ext_wr_data; // Provides SW write data
829 // for external register
830 // "clr_int_reg_26", field
831 // "int_state"
832output clr_int_reg_26_ext_select; // When set, register clr_int_reg_26 is
833 // selected. This signal is a pulse.
834input [1:0] clr_int_reg_26_int_state_ext_read_data; // Ext read data (decode)
835output [1:0] clr_int_reg_27_int_state_ext_wr_data; // Provides SW write data
836 // for external register
837 // "clr_int_reg_27", field
838 // "int_state"
839output clr_int_reg_27_ext_select; // When set, register clr_int_reg_27 is
840 // selected. This signal is a pulse.
841input [1:0] clr_int_reg_27_int_state_ext_read_data; // Ext read data (decode)
842output [1:0] clr_int_reg_28_int_state_ext_wr_data; // Provides SW write data
843 // for external register
844 // "clr_int_reg_28", field
845 // "int_state"
846output clr_int_reg_28_ext_select; // When set, register clr_int_reg_28 is
847 // selected. This signal is a pulse.
848input [1:0] clr_int_reg_28_int_state_ext_read_data; // Ext read data (decode)
849output [1:0] clr_int_reg_29_int_state_ext_wr_data; // Provides SW write data
850 // for external register
851 // "clr_int_reg_29", field
852 // "int_state"
853output clr_int_reg_29_ext_select; // When set, register clr_int_reg_29 is
854 // selected. This signal is a pulse.
855input [1:0] clr_int_reg_29_int_state_ext_read_data; // Ext read data (decode)
856output [1:0] clr_int_reg_30_int_state_ext_wr_data; // Provides SW write data
857 // for external register
858 // "clr_int_reg_30", field
859 // "int_state"
860output clr_int_reg_30_ext_select; // When set, register clr_int_reg_30 is
861 // selected. This signal is a pulse.
862input [1:0] clr_int_reg_30_int_state_ext_read_data; // Ext read data (decode)
863output [1:0] clr_int_reg_31_int_state_ext_wr_data; // Provides SW write data
864 // for external register
865 // "clr_int_reg_31", field
866 // "int_state"
867output clr_int_reg_31_ext_select; // When set, register clr_int_reg_31 is
868 // selected. This signal is a pulse.
869input [1:0] clr_int_reg_31_int_state_ext_read_data; // Ext read data (decode)
870output [1:0] clr_int_reg_32_int_state_ext_wr_data; // Provides SW write data
871 // for external register
872 // "clr_int_reg_32", field
873 // "int_state"
874output clr_int_reg_32_ext_select; // When set, register clr_int_reg_32 is
875 // selected. This signal is a pulse.
876input [1:0] clr_int_reg_32_int_state_ext_read_data; // Ext read data (decode)
877output [1:0] clr_int_reg_33_int_state_ext_wr_data; // Provides SW write data
878 // for external register
879 // "clr_int_reg_33", field
880 // "int_state"
881output clr_int_reg_33_ext_select; // When set, register clr_int_reg_33 is
882 // selected. This signal is a pulse.
883input [1:0] clr_int_reg_33_int_state_ext_read_data; // Ext read data (decode)
884output [1:0] clr_int_reg_34_int_state_ext_wr_data; // Provides SW write data
885 // for external register
886 // "clr_int_reg_34", field
887 // "int_state"
888output clr_int_reg_34_ext_select; // When set, register clr_int_reg_34 is
889 // selected. This signal is a pulse.
890input [1:0] clr_int_reg_34_int_state_ext_read_data; // Ext read data (decode)
891output [1:0] clr_int_reg_35_int_state_ext_wr_data; // Provides SW write data
892 // for external register
893 // "clr_int_reg_35", field
894 // "int_state"
895output clr_int_reg_35_ext_select; // When set, register clr_int_reg_35 is
896 // selected. This signal is a pulse.
897input [1:0] clr_int_reg_35_int_state_ext_read_data; // Ext read data (decode)
898output [1:0] clr_int_reg_36_int_state_ext_wr_data; // Provides SW write data
899 // for external register
900 // "clr_int_reg_36", field
901 // "int_state"
902output clr_int_reg_36_ext_select; // When set, register clr_int_reg_36 is
903 // selected. This signal is a pulse.
904input [1:0] clr_int_reg_36_int_state_ext_read_data; // Ext read data (decode)
905output [1:0] clr_int_reg_37_int_state_ext_wr_data; // Provides SW write data
906 // for external register
907 // "clr_int_reg_37", field
908 // "int_state"
909output clr_int_reg_37_ext_select; // When set, register clr_int_reg_37 is
910 // selected. This signal is a pulse.
911input [1:0] clr_int_reg_37_int_state_ext_read_data; // Ext read data (decode)
912output [1:0] clr_int_reg_38_int_state_ext_wr_data; // Provides SW write data
913 // for external register
914 // "clr_int_reg_38", field
915 // "int_state"
916output clr_int_reg_38_ext_select; // When set, register clr_int_reg_38 is
917 // selected. This signal is a pulse.
918input [1:0] clr_int_reg_38_int_state_ext_read_data; // Ext read data (decode)
919output [1:0] clr_int_reg_39_int_state_ext_wr_data; // Provides SW write data
920 // for external register
921 // "clr_int_reg_39", field
922 // "int_state"
923output clr_int_reg_39_ext_select; // When set, register clr_int_reg_39 is
924 // selected. This signal is a pulse.
925input [1:0] clr_int_reg_39_int_state_ext_read_data; // Ext read data (decode)
926output [1:0] clr_int_reg_40_int_state_ext_wr_data; // Provides SW write data
927 // for external register
928 // "clr_int_reg_40", field
929 // "int_state"
930output clr_int_reg_40_ext_select; // When set, register clr_int_reg_40 is
931 // selected. This signal is a pulse.
932input [1:0] clr_int_reg_40_int_state_ext_read_data; // Ext read data (decode)
933output [1:0] clr_int_reg_41_int_state_ext_wr_data; // Provides SW write data
934 // for external register
935 // "clr_int_reg_41", field
936 // "int_state"
937output clr_int_reg_41_ext_select; // When set, register clr_int_reg_41 is
938 // selected. This signal is a pulse.
939input [1:0] clr_int_reg_41_int_state_ext_read_data; // Ext read data (decode)
940output [1:0] clr_int_reg_42_int_state_ext_wr_data; // Provides SW write data
941 // for external register
942 // "clr_int_reg_42", field
943 // "int_state"
944output clr_int_reg_42_ext_select; // When set, register clr_int_reg_42 is
945 // selected. This signal is a pulse.
946input [1:0] clr_int_reg_42_int_state_ext_read_data; // Ext read data (decode)
947output [1:0] clr_int_reg_43_int_state_ext_wr_data; // Provides SW write data
948 // for external register
949 // "clr_int_reg_43", field
950 // "int_state"
951output clr_int_reg_43_ext_select; // When set, register clr_int_reg_43 is
952 // selected. This signal is a pulse.
953input [1:0] clr_int_reg_43_int_state_ext_read_data; // Ext read data (decode)
954output [1:0] clr_int_reg_44_int_state_ext_wr_data; // Provides SW write data
955 // for external register
956 // "clr_int_reg_44", field
957 // "int_state"
958output clr_int_reg_44_ext_select; // When set, register clr_int_reg_44 is
959 // selected. This signal is a pulse.
960input [1:0] clr_int_reg_44_int_state_ext_read_data; // Ext read data (decode)
961output [1:0] clr_int_reg_45_int_state_ext_wr_data; // Provides SW write data
962 // for external register
963 // "clr_int_reg_45", field
964 // "int_state"
965output clr_int_reg_45_ext_select; // When set, register clr_int_reg_45 is
966 // selected. This signal is a pulse.
967input [1:0] clr_int_reg_45_int_state_ext_read_data; // Ext read data (decode)
968output [1:0] clr_int_reg_46_int_state_ext_wr_data; // Provides SW write data
969 // for external register
970 // "clr_int_reg_46", field
971 // "int_state"
972output clr_int_reg_46_ext_select; // When set, register clr_int_reg_46 is
973 // selected. This signal is a pulse.
974input [1:0] clr_int_reg_46_int_state_ext_read_data; // Ext read data (decode)
975output [1:0] clr_int_reg_47_int_state_ext_wr_data; // Provides SW write data
976 // for external register
977 // "clr_int_reg_47", field
978 // "int_state"
979output clr_int_reg_47_ext_select; // When set, register clr_int_reg_47 is
980 // selected. This signal is a pulse.
981input [1:0] clr_int_reg_47_int_state_ext_read_data; // Ext read data (decode)
982output [1:0] clr_int_reg_48_int_state_ext_wr_data; // Provides SW write data
983 // for external register
984 // "clr_int_reg_48", field
985 // "int_state"
986output clr_int_reg_48_ext_select; // When set, register clr_int_reg_48 is
987 // selected. This signal is a pulse.
988input [1:0] clr_int_reg_48_int_state_ext_read_data; // Ext read data (decode)
989output [1:0] clr_int_reg_49_int_state_ext_wr_data; // Provides SW write data
990 // for external register
991 // "clr_int_reg_49", field
992 // "int_state"
993output clr_int_reg_49_ext_select; // When set, register clr_int_reg_49 is
994 // selected. This signal is a pulse.
995input [1:0] clr_int_reg_49_int_state_ext_read_data; // Ext read data (decode)
996output [1:0] clr_int_reg_50_int_state_ext_wr_data; // Provides SW write data
997 // for external register
998 // "clr_int_reg_50", field
999 // "int_state"
1000output clr_int_reg_50_ext_select; // When set, register clr_int_reg_50 is
1001 // selected. This signal is a pulse.
1002input [1:0] clr_int_reg_50_int_state_ext_read_data; // Ext read data (decode)
1003output [1:0] clr_int_reg_51_int_state_ext_wr_data; // Provides SW write data
1004 // for external register
1005 // "clr_int_reg_51", field
1006 // "int_state"
1007output clr_int_reg_51_ext_select; // When set, register clr_int_reg_51 is
1008 // selected. This signal is a pulse.
1009input [1:0] clr_int_reg_51_int_state_ext_read_data; // Ext read data (decode)
1010output [1:0] clr_int_reg_52_int_state_ext_wr_data; // Provides SW write data
1011 // for external register
1012 // "clr_int_reg_52", field
1013 // "int_state"
1014output clr_int_reg_52_ext_select; // When set, register clr_int_reg_52 is
1015 // selected. This signal is a pulse.
1016input [1:0] clr_int_reg_52_int_state_ext_read_data; // Ext read data (decode)
1017output [1:0] clr_int_reg_53_int_state_ext_wr_data; // Provides SW write data
1018 // for external register
1019 // "clr_int_reg_53", field
1020 // "int_state"
1021output clr_int_reg_53_ext_select; // When set, register clr_int_reg_53 is
1022 // selected. This signal is a pulse.
1023input [1:0] clr_int_reg_53_int_state_ext_read_data; // Ext read data (decode)
1024output [1:0] clr_int_reg_54_int_state_ext_wr_data; // Provides SW write data
1025 // for external register
1026 // "clr_int_reg_54", field
1027 // "int_state"
1028output clr_int_reg_54_ext_select; // When set, register clr_int_reg_54 is
1029 // selected. This signal is a pulse.
1030input [1:0] clr_int_reg_54_int_state_ext_read_data; // Ext read data (decode)
1031output [1:0] clr_int_reg_55_int_state_ext_wr_data; // Provides SW write data
1032 // for external register
1033 // "clr_int_reg_55", field
1034 // "int_state"
1035output clr_int_reg_55_ext_select; // When set, register clr_int_reg_55 is
1036 // selected. This signal is a pulse.
1037input [1:0] clr_int_reg_55_int_state_ext_read_data; // Ext read data (decode)
1038output [1:0] clr_int_reg_56_int_state_ext_wr_data; // Provides SW write data
1039 // for external register
1040 // "clr_int_reg_56", field
1041 // "int_state"
1042output clr_int_reg_56_ext_select; // When set, register clr_int_reg_56 is
1043 // selected. This signal is a pulse.
1044input [1:0] clr_int_reg_56_int_state_ext_read_data; // Ext read data (decode)
1045output [1:0] clr_int_reg_57_int_state_ext_wr_data; // Provides SW write data
1046 // for external register
1047 // "clr_int_reg_57", field
1048 // "int_state"
1049output clr_int_reg_57_ext_select; // When set, register clr_int_reg_57 is
1050 // selected. This signal is a pulse.
1051input [1:0] clr_int_reg_57_int_state_ext_read_data; // Ext read data (decode)
1052output [1:0] clr_int_reg_58_int_state_ext_wr_data; // Provides SW write data
1053 // for external register
1054 // "clr_int_reg_58", field
1055 // "int_state"
1056output clr_int_reg_58_ext_select; // When set, register clr_int_reg_58 is
1057 // selected. This signal is a pulse.
1058input [1:0] clr_int_reg_58_int_state_ext_read_data; // Ext read data (decode)
1059output [1:0] clr_int_reg_59_int_state_ext_wr_data; // Provides SW write data
1060 // for external register
1061 // "clr_int_reg_59", field
1062 // "int_state"
1063output clr_int_reg_59_ext_select; // When set, register clr_int_reg_59 is
1064 // selected. This signal is a pulse.
1065input [1:0] clr_int_reg_59_int_state_ext_read_data; // Ext read data (decode)
1066output [1:0] clr_int_reg_62_int_state_ext_wr_data; // Provides SW write data
1067 // for external register
1068 // "clr_int_reg_62", field
1069 // "int_state"
1070output clr_int_reg_62_ext_select; // When set, register clr_int_reg_62 is
1071 // selected. This signal is a pulse.
1072input [1:0] clr_int_reg_62_int_state_ext_read_data; // Ext read data (decode)
1073output [1:0] clr_int_reg_63_int_state_ext_wr_data; // Provides SW write data
1074 // for external register
1075 // "clr_int_reg_63", field
1076 // "int_state"
1077output clr_int_reg_63_ext_select; // When set, register clr_int_reg_63 is
1078 // selected. This signal is a pulse.
1079input [1:0] clr_int_reg_63_int_state_ext_read_data; // Ext read data (decode)
1080output [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_INT_SLC] interrupt_retry_timer_limit_hw_read;
1081 // This signal provides the current value of interrupt_retry_timer_limit.
1082input [23:0] interrupt_state_status_1_state_ext_read_data; // Ext read data
1083 // (decode)
1084input [63:0] interrupt_state_status_2_state_ext_read_data; // Ext read data
1085 // (decode)
1086
1087//====================================================
1088// Type declarations
1089//====================================================
1090wire clk; // Clock signal
1091wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] csrbus_addr; // Address bus
1092wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
1093wire csrbus_wr; // Read/Write signal
1094wire csrbus_valid; // Valid address
1095wire csrbus_mapped; // Address is mapped
1096wire csrbus_done; // Operation is done
1097wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_read_data; // SW read data bus
1098wire rst_l; // Reset signal
1099wire [1:0] csrbus_src_bus; // Source bus
1100wire csrbus_acc_vio; // Violation signal
1101wire instance_id; // Instance ID
1102wire ext_wr; // When one, csr operation is a write. When zero, operation is a
1103 // read.
1104wire interrupt_mapping_20_mdo_mode_hw_read; // This signal provides the current
1105 // value of
1106 // interrupt_mapping_20_mdo_mode.
1107wire interrupt_mapping_20_v_hw_read; // This signal provides the current value
1108 // of interrupt_mapping_20_v.
1109wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_INT_SLC] interrupt_mapping_20_t_id_hw_read;
1110 // This signal provides the current value of interrupt_mapping_20_t_id.
1111wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_20_int_cntrl_num_hw_read;
1112 // This signal provides the current value of
1113 // interrupt_mapping_20_int_cntrl_num.
1114wire interrupt_mapping_21_mdo_mode_hw_read; // This signal provides the current
1115 // value of
1116 // interrupt_mapping_21_mdo_mode.
1117wire interrupt_mapping_21_v_hw_read; // This signal provides the current value
1118 // of interrupt_mapping_21_v.
1119wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_INT_SLC] interrupt_mapping_21_t_id_hw_read;
1120 // This signal provides the current value of interrupt_mapping_21_t_id.
1121wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_21_int_cntrl_num_hw_read;
1122 // This signal provides the current value of
1123 // interrupt_mapping_21_int_cntrl_num.
1124wire interrupt_mapping_22_mdo_mode_hw_read; // This signal provides the current
1125 // value of
1126 // interrupt_mapping_22_mdo_mode.
1127wire interrupt_mapping_22_v_hw_read; // This signal provides the current value
1128 // of interrupt_mapping_22_v.
1129wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_INT_SLC] interrupt_mapping_22_t_id_hw_read;
1130 // This signal provides the current value of interrupt_mapping_22_t_id.
1131wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_22_int_cntrl_num_hw_read;
1132 // This signal provides the current value of
1133 // interrupt_mapping_22_int_cntrl_num.
1134wire interrupt_mapping_23_mdo_mode_hw_read; // This signal provides the current
1135 // value of
1136 // interrupt_mapping_23_mdo_mode.
1137wire interrupt_mapping_23_v_hw_read; // This signal provides the current value
1138 // of interrupt_mapping_23_v.
1139wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_INT_SLC] interrupt_mapping_23_t_id_hw_read;
1140 // This signal provides the current value of interrupt_mapping_23_t_id.
1141wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_23_int_cntrl_num_hw_read;
1142 // This signal provides the current value of
1143 // interrupt_mapping_23_int_cntrl_num.
1144wire interrupt_mapping_24_mdo_mode_hw_read; // This signal provides the current
1145 // value of
1146 // interrupt_mapping_24_mdo_mode.
1147wire interrupt_mapping_24_v_hw_read; // This signal provides the current value
1148 // of interrupt_mapping_24_v.
1149wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_INT_SLC] interrupt_mapping_24_t_id_hw_read;
1150 // This signal provides the current value of interrupt_mapping_24_t_id.
1151wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_24_int_cntrl_num_hw_read;
1152 // This signal provides the current value of
1153 // interrupt_mapping_24_int_cntrl_num.
1154wire interrupt_mapping_25_mdo_mode_hw_read; // This signal provides the current
1155 // value of
1156 // interrupt_mapping_25_mdo_mode.
1157wire interrupt_mapping_25_v_hw_read; // This signal provides the current value
1158 // of interrupt_mapping_25_v.
1159wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_INT_SLC] interrupt_mapping_25_t_id_hw_read;
1160 // This signal provides the current value of interrupt_mapping_25_t_id.
1161wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_25_int_cntrl_num_hw_read;
1162 // This signal provides the current value of
1163 // interrupt_mapping_25_int_cntrl_num.
1164wire interrupt_mapping_26_mdo_mode_hw_read; // This signal provides the current
1165 // value of
1166 // interrupt_mapping_26_mdo_mode.
1167wire interrupt_mapping_26_v_hw_read; // This signal provides the current value
1168 // of interrupt_mapping_26_v.
1169wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_INT_SLC] interrupt_mapping_26_t_id_hw_read;
1170 // This signal provides the current value of interrupt_mapping_26_t_id.
1171wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_26_int_cntrl_num_hw_read;
1172 // This signal provides the current value of
1173 // interrupt_mapping_26_int_cntrl_num.
1174wire interrupt_mapping_27_mdo_mode_hw_read; // This signal provides the current
1175 // value of
1176 // interrupt_mapping_27_mdo_mode.
1177wire interrupt_mapping_27_v_hw_read; // This signal provides the current value
1178 // of interrupt_mapping_27_v.
1179wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_INT_SLC] interrupt_mapping_27_t_id_hw_read;
1180 // This signal provides the current value of interrupt_mapping_27_t_id.
1181wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_27_int_cntrl_num_hw_read;
1182 // This signal provides the current value of
1183 // interrupt_mapping_27_int_cntrl_num.
1184wire interrupt_mapping_28_mdo_mode_hw_read; // This signal provides the current
1185 // value of
1186 // interrupt_mapping_28_mdo_mode.
1187wire interrupt_mapping_28_v_hw_read; // This signal provides the current value
1188 // of interrupt_mapping_28_v.
1189wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_INT_SLC] interrupt_mapping_28_t_id_hw_read;
1190 // This signal provides the current value of interrupt_mapping_28_t_id.
1191wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_28_int_cntrl_num_hw_read;
1192 // This signal provides the current value of
1193 // interrupt_mapping_28_int_cntrl_num.
1194wire interrupt_mapping_29_mdo_mode_hw_read; // This signal provides the current
1195 // value of
1196 // interrupt_mapping_29_mdo_mode.
1197wire interrupt_mapping_29_v_hw_read; // This signal provides the current value
1198 // of interrupt_mapping_29_v.
1199wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_INT_SLC] interrupt_mapping_29_t_id_hw_read;
1200 // This signal provides the current value of interrupt_mapping_29_t_id.
1201wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_29_int_cntrl_num_hw_read;
1202 // This signal provides the current value of
1203 // interrupt_mapping_29_int_cntrl_num.
1204wire interrupt_mapping_30_mdo_mode_hw_read; // This signal provides the current
1205 // value of
1206 // interrupt_mapping_30_mdo_mode.
1207wire interrupt_mapping_30_v_hw_read; // This signal provides the current value
1208 // of interrupt_mapping_30_v.
1209wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_INT_SLC] interrupt_mapping_30_t_id_hw_read;
1210 // This signal provides the current value of interrupt_mapping_30_t_id.
1211wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_30_int_cntrl_num_hw_read;
1212 // This signal provides the current value of
1213 // interrupt_mapping_30_int_cntrl_num.
1214wire interrupt_mapping_31_mdo_mode_hw_read; // This signal provides the current
1215 // value of
1216 // interrupt_mapping_31_mdo_mode.
1217wire interrupt_mapping_31_v_hw_read; // This signal provides the current value
1218 // of interrupt_mapping_31_v.
1219wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_INT_SLC] interrupt_mapping_31_t_id_hw_read;
1220 // This signal provides the current value of interrupt_mapping_31_t_id.
1221wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_31_int_cntrl_num_hw_read;
1222 // This signal provides the current value of
1223 // interrupt_mapping_31_int_cntrl_num.
1224wire interrupt_mapping_32_mdo_mode_hw_read; // This signal provides the current
1225 // value of
1226 // interrupt_mapping_32_mdo_mode.
1227wire interrupt_mapping_32_v_hw_read; // This signal provides the current value
1228 // of interrupt_mapping_32_v.
1229wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_INT_SLC] interrupt_mapping_32_t_id_hw_read;
1230 // This signal provides the current value of interrupt_mapping_32_t_id.
1231wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_32_int_cntrl_num_hw_read;
1232 // This signal provides the current value of
1233 // interrupt_mapping_32_int_cntrl_num.
1234wire interrupt_mapping_33_mdo_mode_hw_read; // This signal provides the current
1235 // value of
1236 // interrupt_mapping_33_mdo_mode.
1237wire interrupt_mapping_33_v_hw_read; // This signal provides the current value
1238 // of interrupt_mapping_33_v.
1239wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_INT_SLC] interrupt_mapping_33_t_id_hw_read;
1240 // This signal provides the current value of interrupt_mapping_33_t_id.
1241wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_33_int_cntrl_num_hw_read;
1242 // This signal provides the current value of
1243 // interrupt_mapping_33_int_cntrl_num.
1244wire interrupt_mapping_34_mdo_mode_hw_read; // This signal provides the current
1245 // value of
1246 // interrupt_mapping_34_mdo_mode.
1247wire interrupt_mapping_34_v_hw_read; // This signal provides the current value
1248 // of interrupt_mapping_34_v.
1249wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_INT_SLC] interrupt_mapping_34_t_id_hw_read;
1250 // This signal provides the current value of interrupt_mapping_34_t_id.
1251wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_34_int_cntrl_num_hw_read;
1252 // This signal provides the current value of
1253 // interrupt_mapping_34_int_cntrl_num.
1254wire interrupt_mapping_35_mdo_mode_hw_read; // This signal provides the current
1255 // value of
1256 // interrupt_mapping_35_mdo_mode.
1257wire interrupt_mapping_35_v_hw_read; // This signal provides the current value
1258 // of interrupt_mapping_35_v.
1259wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_INT_SLC] interrupt_mapping_35_t_id_hw_read;
1260 // This signal provides the current value of interrupt_mapping_35_t_id.
1261wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_35_int_cntrl_num_hw_read;
1262 // This signal provides the current value of
1263 // interrupt_mapping_35_int_cntrl_num.
1264wire interrupt_mapping_36_mdo_mode_hw_read; // This signal provides the current
1265 // value of
1266 // interrupt_mapping_36_mdo_mode.
1267wire interrupt_mapping_36_v_hw_read; // This signal provides the current value
1268 // of interrupt_mapping_36_v.
1269wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_INT_SLC] interrupt_mapping_36_t_id_hw_read;
1270 // This signal provides the current value of interrupt_mapping_36_t_id.
1271wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_36_int_cntrl_num_hw_read;
1272 // This signal provides the current value of
1273 // interrupt_mapping_36_int_cntrl_num.
1274wire interrupt_mapping_37_mdo_mode_hw_read; // This signal provides the current
1275 // value of
1276 // interrupt_mapping_37_mdo_mode.
1277wire interrupt_mapping_37_v_hw_read; // This signal provides the current value
1278 // of interrupt_mapping_37_v.
1279wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_INT_SLC] interrupt_mapping_37_t_id_hw_read;
1280 // This signal provides the current value of interrupt_mapping_37_t_id.
1281wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_37_int_cntrl_num_hw_read;
1282 // This signal provides the current value of
1283 // interrupt_mapping_37_int_cntrl_num.
1284wire interrupt_mapping_38_mdo_mode_hw_read; // This signal provides the current
1285 // value of
1286 // interrupt_mapping_38_mdo_mode.
1287wire interrupt_mapping_38_v_hw_read; // This signal provides the current value
1288 // of interrupt_mapping_38_v.
1289wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_INT_SLC] interrupt_mapping_38_t_id_hw_read;
1290 // This signal provides the current value of interrupt_mapping_38_t_id.
1291wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_38_int_cntrl_num_hw_read;
1292 // This signal provides the current value of
1293 // interrupt_mapping_38_int_cntrl_num.
1294wire interrupt_mapping_39_mdo_mode_hw_read; // This signal provides the current
1295 // value of
1296 // interrupt_mapping_39_mdo_mode.
1297wire interrupt_mapping_39_v_hw_read; // This signal provides the current value
1298 // of interrupt_mapping_39_v.
1299wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_INT_SLC] interrupt_mapping_39_t_id_hw_read;
1300 // This signal provides the current value of interrupt_mapping_39_t_id.
1301wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_39_int_cntrl_num_hw_read;
1302 // This signal provides the current value of
1303 // interrupt_mapping_39_int_cntrl_num.
1304wire interrupt_mapping_40_mdo_mode_hw_read; // This signal provides the current
1305 // value of
1306 // interrupt_mapping_40_mdo_mode.
1307wire interrupt_mapping_40_v_hw_read; // This signal provides the current value
1308 // of interrupt_mapping_40_v.
1309wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_INT_SLC] interrupt_mapping_40_t_id_hw_read;
1310 // This signal provides the current value of interrupt_mapping_40_t_id.
1311wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_40_int_cntrl_num_hw_read;
1312 // This signal provides the current value of
1313 // interrupt_mapping_40_int_cntrl_num.
1314wire interrupt_mapping_41_mdo_mode_hw_read; // This signal provides the current
1315 // value of
1316 // interrupt_mapping_41_mdo_mode.
1317wire interrupt_mapping_41_v_hw_read; // This signal provides the current value
1318 // of interrupt_mapping_41_v.
1319wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_INT_SLC] interrupt_mapping_41_t_id_hw_read;
1320 // This signal provides the current value of interrupt_mapping_41_t_id.
1321wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_41_int_cntrl_num_hw_read;
1322 // This signal provides the current value of
1323 // interrupt_mapping_41_int_cntrl_num.
1324wire interrupt_mapping_42_mdo_mode_hw_read; // This signal provides the current
1325 // value of
1326 // interrupt_mapping_42_mdo_mode.
1327wire interrupt_mapping_42_v_hw_read; // This signal provides the current value
1328 // of interrupt_mapping_42_v.
1329wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_INT_SLC] interrupt_mapping_42_t_id_hw_read;
1330 // This signal provides the current value of interrupt_mapping_42_t_id.
1331wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_42_int_cntrl_num_hw_read;
1332 // This signal provides the current value of
1333 // interrupt_mapping_42_int_cntrl_num.
1334wire interrupt_mapping_43_mdo_mode_hw_read; // This signal provides the current
1335 // value of
1336 // interrupt_mapping_43_mdo_mode.
1337wire interrupt_mapping_43_v_hw_read; // This signal provides the current value
1338 // of interrupt_mapping_43_v.
1339wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_INT_SLC] interrupt_mapping_43_t_id_hw_read;
1340 // This signal provides the current value of interrupt_mapping_43_t_id.
1341wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_43_int_cntrl_num_hw_read;
1342 // This signal provides the current value of
1343 // interrupt_mapping_43_int_cntrl_num.
1344wire interrupt_mapping_44_mdo_mode_hw_read; // This signal provides the current
1345 // value of
1346 // interrupt_mapping_44_mdo_mode.
1347wire interrupt_mapping_44_v_hw_read; // This signal provides the current value
1348 // of interrupt_mapping_44_v.
1349wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_INT_SLC] interrupt_mapping_44_t_id_hw_read;
1350 // This signal provides the current value of interrupt_mapping_44_t_id.
1351wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_44_int_cntrl_num_hw_read;
1352 // This signal provides the current value of
1353 // interrupt_mapping_44_int_cntrl_num.
1354wire interrupt_mapping_45_mdo_mode_hw_read; // This signal provides the current
1355 // value of
1356 // interrupt_mapping_45_mdo_mode.
1357wire interrupt_mapping_45_v_hw_read; // This signal provides the current value
1358 // of interrupt_mapping_45_v.
1359wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_INT_SLC] interrupt_mapping_45_t_id_hw_read;
1360 // This signal provides the current value of interrupt_mapping_45_t_id.
1361wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_45_int_cntrl_num_hw_read;
1362 // This signal provides the current value of
1363 // interrupt_mapping_45_int_cntrl_num.
1364wire interrupt_mapping_46_mdo_mode_hw_read; // This signal provides the current
1365 // value of
1366 // interrupt_mapping_46_mdo_mode.
1367wire interrupt_mapping_46_v_hw_read; // This signal provides the current value
1368 // of interrupt_mapping_46_v.
1369wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_INT_SLC] interrupt_mapping_46_t_id_hw_read;
1370 // This signal provides the current value of interrupt_mapping_46_t_id.
1371wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_46_int_cntrl_num_hw_read;
1372 // This signal provides the current value of
1373 // interrupt_mapping_46_int_cntrl_num.
1374wire interrupt_mapping_47_mdo_mode_hw_read; // This signal provides the current
1375 // value of
1376 // interrupt_mapping_47_mdo_mode.
1377wire interrupt_mapping_47_v_hw_read; // This signal provides the current value
1378 // of interrupt_mapping_47_v.
1379wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_INT_SLC] interrupt_mapping_47_t_id_hw_read;
1380 // This signal provides the current value of interrupt_mapping_47_t_id.
1381wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_47_int_cntrl_num_hw_read;
1382 // This signal provides the current value of
1383 // interrupt_mapping_47_int_cntrl_num.
1384wire interrupt_mapping_48_mdo_mode_hw_read; // This signal provides the current
1385 // value of
1386 // interrupt_mapping_48_mdo_mode.
1387wire interrupt_mapping_48_v_hw_read; // This signal provides the current value
1388 // of interrupt_mapping_48_v.
1389wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_INT_SLC] interrupt_mapping_48_t_id_hw_read;
1390 // This signal provides the current value of interrupt_mapping_48_t_id.
1391wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_48_int_cntrl_num_hw_read;
1392 // This signal provides the current value of
1393 // interrupt_mapping_48_int_cntrl_num.
1394wire interrupt_mapping_49_mdo_mode_hw_read; // This signal provides the current
1395 // value of
1396 // interrupt_mapping_49_mdo_mode.
1397wire interrupt_mapping_49_v_hw_read; // This signal provides the current value
1398 // of interrupt_mapping_49_v.
1399wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_INT_SLC] interrupt_mapping_49_t_id_hw_read;
1400 // This signal provides the current value of interrupt_mapping_49_t_id.
1401wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_49_int_cntrl_num_hw_read;
1402 // This signal provides the current value of
1403 // interrupt_mapping_49_int_cntrl_num.
1404wire interrupt_mapping_50_mdo_mode_hw_read; // This signal provides the current
1405 // value of
1406 // interrupt_mapping_50_mdo_mode.
1407wire interrupt_mapping_50_v_hw_read; // This signal provides the current value
1408 // of interrupt_mapping_50_v.
1409wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_INT_SLC] interrupt_mapping_50_t_id_hw_read;
1410 // This signal provides the current value of interrupt_mapping_50_t_id.
1411wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_50_int_cntrl_num_hw_read;
1412 // This signal provides the current value of
1413 // interrupt_mapping_50_int_cntrl_num.
1414wire interrupt_mapping_51_mdo_mode_hw_read; // This signal provides the current
1415 // value of
1416 // interrupt_mapping_51_mdo_mode.
1417wire interrupt_mapping_51_v_hw_read; // This signal provides the current value
1418 // of interrupt_mapping_51_v.
1419wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_INT_SLC] interrupt_mapping_51_t_id_hw_read;
1420 // This signal provides the current value of interrupt_mapping_51_t_id.
1421wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_51_int_cntrl_num_hw_read;
1422 // This signal provides the current value of
1423 // interrupt_mapping_51_int_cntrl_num.
1424wire interrupt_mapping_52_mdo_mode_hw_read; // This signal provides the current
1425 // value of
1426 // interrupt_mapping_52_mdo_mode.
1427wire interrupt_mapping_52_v_hw_read; // This signal provides the current value
1428 // of interrupt_mapping_52_v.
1429wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_INT_SLC] interrupt_mapping_52_t_id_hw_read;
1430 // This signal provides the current value of interrupt_mapping_52_t_id.
1431wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_52_int_cntrl_num_hw_read;
1432 // This signal provides the current value of
1433 // interrupt_mapping_52_int_cntrl_num.
1434wire interrupt_mapping_53_mdo_mode_hw_read; // This signal provides the current
1435 // value of
1436 // interrupt_mapping_53_mdo_mode.
1437wire interrupt_mapping_53_v_hw_read; // This signal provides the current value
1438 // of interrupt_mapping_53_v.
1439wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_INT_SLC] interrupt_mapping_53_t_id_hw_read;
1440 // This signal provides the current value of interrupt_mapping_53_t_id.
1441wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_53_int_cntrl_num_hw_read;
1442 // This signal provides the current value of
1443 // interrupt_mapping_53_int_cntrl_num.
1444wire interrupt_mapping_54_mdo_mode_hw_read; // This signal provides the current
1445 // value of
1446 // interrupt_mapping_54_mdo_mode.
1447wire interrupt_mapping_54_v_hw_read; // This signal provides the current value
1448 // of interrupt_mapping_54_v.
1449wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_INT_SLC] interrupt_mapping_54_t_id_hw_read;
1450 // This signal provides the current value of interrupt_mapping_54_t_id.
1451wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_54_int_cntrl_num_hw_read;
1452 // This signal provides the current value of
1453 // interrupt_mapping_54_int_cntrl_num.
1454wire interrupt_mapping_55_mdo_mode_hw_read; // This signal provides the current
1455 // value of
1456 // interrupt_mapping_55_mdo_mode.
1457wire interrupt_mapping_55_v_hw_read; // This signal provides the current value
1458 // of interrupt_mapping_55_v.
1459wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_INT_SLC] interrupt_mapping_55_t_id_hw_read;
1460 // This signal provides the current value of interrupt_mapping_55_t_id.
1461wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_55_int_cntrl_num_hw_read;
1462 // This signal provides the current value of
1463 // interrupt_mapping_55_int_cntrl_num.
1464wire interrupt_mapping_56_mdo_mode_hw_read; // This signal provides the current
1465 // value of
1466 // interrupt_mapping_56_mdo_mode.
1467wire interrupt_mapping_56_v_hw_read; // This signal provides the current value
1468 // of interrupt_mapping_56_v.
1469wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_INT_SLC] interrupt_mapping_56_t_id_hw_read;
1470 // This signal provides the current value of interrupt_mapping_56_t_id.
1471wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_56_int_cntrl_num_hw_read;
1472 // This signal provides the current value of
1473 // interrupt_mapping_56_int_cntrl_num.
1474wire interrupt_mapping_57_mdo_mode_hw_read; // This signal provides the current
1475 // value of
1476 // interrupt_mapping_57_mdo_mode.
1477wire interrupt_mapping_57_v_hw_read; // This signal provides the current value
1478 // of interrupt_mapping_57_v.
1479wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_INT_SLC] interrupt_mapping_57_t_id_hw_read;
1480 // This signal provides the current value of interrupt_mapping_57_t_id.
1481wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_57_int_cntrl_num_hw_read;
1482 // This signal provides the current value of
1483 // interrupt_mapping_57_int_cntrl_num.
1484wire interrupt_mapping_58_mdo_mode_hw_read; // This signal provides the current
1485 // value of
1486 // interrupt_mapping_58_mdo_mode.
1487wire interrupt_mapping_58_v_hw_read; // This signal provides the current value
1488 // of interrupt_mapping_58_v.
1489wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_INT_SLC] interrupt_mapping_58_t_id_hw_read;
1490 // This signal provides the current value of interrupt_mapping_58_t_id.
1491wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_58_int_cntrl_num_hw_read;
1492 // This signal provides the current value of
1493 // interrupt_mapping_58_int_cntrl_num.
1494wire interrupt_mapping_59_mdo_mode_hw_read; // This signal provides the current
1495 // value of
1496 // interrupt_mapping_59_mdo_mode.
1497wire interrupt_mapping_59_v_hw_read; // This signal provides the current value
1498 // of interrupt_mapping_59_v.
1499wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_INT_SLC] interrupt_mapping_59_t_id_hw_read;
1500 // This signal provides the current value of interrupt_mapping_59_t_id.
1501wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_59_int_cntrl_num_hw_read;
1502 // This signal provides the current value of
1503 // interrupt_mapping_59_int_cntrl_num.
1504wire interrupt_mapping_62_mdo_mode_hw_read; // This signal provides the current
1505 // value of
1506 // interrupt_mapping_62_mdo_mode.
1507wire interrupt_mapping_62_v_hw_read; // This signal provides the current value
1508 // of interrupt_mapping_62_v.
1509wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_INT_SLC] interrupt_mapping_62_t_id_hw_read;
1510 // This signal provides the current value of interrupt_mapping_62_t_id.
1511wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_62_int_cntrl_num_hw_read;
1512 // This signal provides the current value of
1513 // interrupt_mapping_62_int_cntrl_num.
1514wire interrupt_mapping_63_mdo_mode_hw_read; // This signal provides the current
1515 // value of
1516 // interrupt_mapping_63_mdo_mode.
1517wire interrupt_mapping_63_v_hw_read; // This signal provides the current value
1518 // of interrupt_mapping_63_v.
1519wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_INT_SLC] interrupt_mapping_63_t_id_hw_read;
1520 // This signal provides the current value of interrupt_mapping_63_t_id.
1521wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_INT_SLC] interrupt_mapping_63_int_cntrl_num_hw_read;
1522 // This signal provides the current value of
1523 // interrupt_mapping_63_int_cntrl_num.
1524wire [1:0] clr_int_reg_20_int_state_ext_wr_data; // Provides SW write data for
1525 // external register
1526 // "clr_int_reg_20", field
1527 // "int_state"
1528wire clr_int_reg_20_ext_select; // When set, register clr_int_reg_20 is
1529 // selected. This signal is a pulse.
1530wire [1:0] clr_int_reg_20_int_state_ext_read_data; // Ext read data (decode)
1531wire [1:0] clr_int_reg_21_int_state_ext_wr_data; // Provides SW write data for
1532 // external register
1533 // "clr_int_reg_21", field
1534 // "int_state"
1535wire clr_int_reg_21_ext_select; // When set, register clr_int_reg_21 is
1536 // selected. This signal is a pulse.
1537wire [1:0] clr_int_reg_21_int_state_ext_read_data; // Ext read data (decode)
1538wire [1:0] clr_int_reg_22_int_state_ext_wr_data; // Provides SW write data for
1539 // external register
1540 // "clr_int_reg_22", field
1541 // "int_state"
1542wire clr_int_reg_22_ext_select; // When set, register clr_int_reg_22 is
1543 // selected. This signal is a pulse.
1544wire [1:0] clr_int_reg_22_int_state_ext_read_data; // Ext read data (decode)
1545wire [1:0] clr_int_reg_23_int_state_ext_wr_data; // Provides SW write data for
1546 // external register
1547 // "clr_int_reg_23", field
1548 // "int_state"
1549wire clr_int_reg_23_ext_select; // When set, register clr_int_reg_23 is
1550 // selected. This signal is a pulse.
1551wire [1:0] clr_int_reg_23_int_state_ext_read_data; // Ext read data (decode)
1552wire [1:0] clr_int_reg_24_int_state_ext_wr_data; // Provides SW write data for
1553 // external register
1554 // "clr_int_reg_24", field
1555 // "int_state"
1556wire clr_int_reg_24_ext_select; // When set, register clr_int_reg_24 is
1557 // selected. This signal is a pulse.
1558wire [1:0] clr_int_reg_24_int_state_ext_read_data; // Ext read data (decode)
1559wire [1:0] clr_int_reg_25_int_state_ext_wr_data; // Provides SW write data for
1560 // external register
1561 // "clr_int_reg_25", field
1562 // "int_state"
1563wire clr_int_reg_25_ext_select; // When set, register clr_int_reg_25 is
1564 // selected. This signal is a pulse.
1565wire [1:0] clr_int_reg_25_int_state_ext_read_data; // Ext read data (decode)
1566wire [1:0] clr_int_reg_26_int_state_ext_wr_data; // Provides SW write data for
1567 // external register
1568 // "clr_int_reg_26", field
1569 // "int_state"
1570wire clr_int_reg_26_ext_select; // When set, register clr_int_reg_26 is
1571 // selected. This signal is a pulse.
1572wire [1:0] clr_int_reg_26_int_state_ext_read_data; // Ext read data (decode)
1573wire [1:0] clr_int_reg_27_int_state_ext_wr_data; // Provides SW write data for
1574 // external register
1575 // "clr_int_reg_27", field
1576 // "int_state"
1577wire clr_int_reg_27_ext_select; // When set, register clr_int_reg_27 is
1578 // selected. This signal is a pulse.
1579wire [1:0] clr_int_reg_27_int_state_ext_read_data; // Ext read data (decode)
1580wire [1:0] clr_int_reg_28_int_state_ext_wr_data; // Provides SW write data for
1581 // external register
1582 // "clr_int_reg_28", field
1583 // "int_state"
1584wire clr_int_reg_28_ext_select; // When set, register clr_int_reg_28 is
1585 // selected. This signal is a pulse.
1586wire [1:0] clr_int_reg_28_int_state_ext_read_data; // Ext read data (decode)
1587wire [1:0] clr_int_reg_29_int_state_ext_wr_data; // Provides SW write data for
1588 // external register
1589 // "clr_int_reg_29", field
1590 // "int_state"
1591wire clr_int_reg_29_ext_select; // When set, register clr_int_reg_29 is
1592 // selected. This signal is a pulse.
1593wire [1:0] clr_int_reg_29_int_state_ext_read_data; // Ext read data (decode)
1594wire [1:0] clr_int_reg_30_int_state_ext_wr_data; // Provides SW write data for
1595 // external register
1596 // "clr_int_reg_30", field
1597 // "int_state"
1598wire clr_int_reg_30_ext_select; // When set, register clr_int_reg_30 is
1599 // selected. This signal is a pulse.
1600wire [1:0] clr_int_reg_30_int_state_ext_read_data; // Ext read data (decode)
1601wire [1:0] clr_int_reg_31_int_state_ext_wr_data; // Provides SW write data for
1602 // external register
1603 // "clr_int_reg_31", field
1604 // "int_state"
1605wire clr_int_reg_31_ext_select; // When set, register clr_int_reg_31 is
1606 // selected. This signal is a pulse.
1607wire [1:0] clr_int_reg_31_int_state_ext_read_data; // Ext read data (decode)
1608wire [1:0] clr_int_reg_32_int_state_ext_wr_data; // Provides SW write data for
1609 // external register
1610 // "clr_int_reg_32", field
1611 // "int_state"
1612wire clr_int_reg_32_ext_select; // When set, register clr_int_reg_32 is
1613 // selected. This signal is a pulse.
1614wire [1:0] clr_int_reg_32_int_state_ext_read_data; // Ext read data (decode)
1615wire [1:0] clr_int_reg_33_int_state_ext_wr_data; // Provides SW write data for
1616 // external register
1617 // "clr_int_reg_33", field
1618 // "int_state"
1619wire clr_int_reg_33_ext_select; // When set, register clr_int_reg_33 is
1620 // selected. This signal is a pulse.
1621wire [1:0] clr_int_reg_33_int_state_ext_read_data; // Ext read data (decode)
1622wire [1:0] clr_int_reg_34_int_state_ext_wr_data; // Provides SW write data for
1623 // external register
1624 // "clr_int_reg_34", field
1625 // "int_state"
1626wire clr_int_reg_34_ext_select; // When set, register clr_int_reg_34 is
1627 // selected. This signal is a pulse.
1628wire [1:0] clr_int_reg_34_int_state_ext_read_data; // Ext read data (decode)
1629wire [1:0] clr_int_reg_35_int_state_ext_wr_data; // Provides SW write data for
1630 // external register
1631 // "clr_int_reg_35", field
1632 // "int_state"
1633wire clr_int_reg_35_ext_select; // When set, register clr_int_reg_35 is
1634 // selected. This signal is a pulse.
1635wire [1:0] clr_int_reg_35_int_state_ext_read_data; // Ext read data (decode)
1636wire [1:0] clr_int_reg_36_int_state_ext_wr_data; // Provides SW write data for
1637 // external register
1638 // "clr_int_reg_36", field
1639 // "int_state"
1640wire clr_int_reg_36_ext_select; // When set, register clr_int_reg_36 is
1641 // selected. This signal is a pulse.
1642wire [1:0] clr_int_reg_36_int_state_ext_read_data; // Ext read data (decode)
1643wire [1:0] clr_int_reg_37_int_state_ext_wr_data; // Provides SW write data for
1644 // external register
1645 // "clr_int_reg_37", field
1646 // "int_state"
1647wire clr_int_reg_37_ext_select; // When set, register clr_int_reg_37 is
1648 // selected. This signal is a pulse.
1649wire [1:0] clr_int_reg_37_int_state_ext_read_data; // Ext read data (decode)
1650wire [1:0] clr_int_reg_38_int_state_ext_wr_data; // Provides SW write data for
1651 // external register
1652 // "clr_int_reg_38", field
1653 // "int_state"
1654wire clr_int_reg_38_ext_select; // When set, register clr_int_reg_38 is
1655 // selected. This signal is a pulse.
1656wire [1:0] clr_int_reg_38_int_state_ext_read_data; // Ext read data (decode)
1657wire [1:0] clr_int_reg_39_int_state_ext_wr_data; // Provides SW write data for
1658 // external register
1659 // "clr_int_reg_39", field
1660 // "int_state"
1661wire clr_int_reg_39_ext_select; // When set, register clr_int_reg_39 is
1662 // selected. This signal is a pulse.
1663wire [1:0] clr_int_reg_39_int_state_ext_read_data; // Ext read data (decode)
1664wire [1:0] clr_int_reg_40_int_state_ext_wr_data; // Provides SW write data for
1665 // external register
1666 // "clr_int_reg_40", field
1667 // "int_state"
1668wire clr_int_reg_40_ext_select; // When set, register clr_int_reg_40 is
1669 // selected. This signal is a pulse.
1670wire [1:0] clr_int_reg_40_int_state_ext_read_data; // Ext read data (decode)
1671wire [1:0] clr_int_reg_41_int_state_ext_wr_data; // Provides SW write data for
1672 // external register
1673 // "clr_int_reg_41", field
1674 // "int_state"
1675wire clr_int_reg_41_ext_select; // When set, register clr_int_reg_41 is
1676 // selected. This signal is a pulse.
1677wire [1:0] clr_int_reg_41_int_state_ext_read_data; // Ext read data (decode)
1678wire [1:0] clr_int_reg_42_int_state_ext_wr_data; // Provides SW write data for
1679 // external register
1680 // "clr_int_reg_42", field
1681 // "int_state"
1682wire clr_int_reg_42_ext_select; // When set, register clr_int_reg_42 is
1683 // selected. This signal is a pulse.
1684wire [1:0] clr_int_reg_42_int_state_ext_read_data; // Ext read data (decode)
1685wire [1:0] clr_int_reg_43_int_state_ext_wr_data; // Provides SW write data for
1686 // external register
1687 // "clr_int_reg_43", field
1688 // "int_state"
1689wire clr_int_reg_43_ext_select; // When set, register clr_int_reg_43 is
1690 // selected. This signal is a pulse.
1691wire [1:0] clr_int_reg_43_int_state_ext_read_data; // Ext read data (decode)
1692wire [1:0] clr_int_reg_44_int_state_ext_wr_data; // Provides SW write data for
1693 // external register
1694 // "clr_int_reg_44", field
1695 // "int_state"
1696wire clr_int_reg_44_ext_select; // When set, register clr_int_reg_44 is
1697 // selected. This signal is a pulse.
1698wire [1:0] clr_int_reg_44_int_state_ext_read_data; // Ext read data (decode)
1699wire [1:0] clr_int_reg_45_int_state_ext_wr_data; // Provides SW write data for
1700 // external register
1701 // "clr_int_reg_45", field
1702 // "int_state"
1703wire clr_int_reg_45_ext_select; // When set, register clr_int_reg_45 is
1704 // selected. This signal is a pulse.
1705wire [1:0] clr_int_reg_45_int_state_ext_read_data; // Ext read data (decode)
1706wire [1:0] clr_int_reg_46_int_state_ext_wr_data; // Provides SW write data for
1707 // external register
1708 // "clr_int_reg_46", field
1709 // "int_state"
1710wire clr_int_reg_46_ext_select; // When set, register clr_int_reg_46 is
1711 // selected. This signal is a pulse.
1712wire [1:0] clr_int_reg_46_int_state_ext_read_data; // Ext read data (decode)
1713wire [1:0] clr_int_reg_47_int_state_ext_wr_data; // Provides SW write data for
1714 // external register
1715 // "clr_int_reg_47", field
1716 // "int_state"
1717wire clr_int_reg_47_ext_select; // When set, register clr_int_reg_47 is
1718 // selected. This signal is a pulse.
1719wire [1:0] clr_int_reg_47_int_state_ext_read_data; // Ext read data (decode)
1720wire [1:0] clr_int_reg_48_int_state_ext_wr_data; // Provides SW write data for
1721 // external register
1722 // "clr_int_reg_48", field
1723 // "int_state"
1724wire clr_int_reg_48_ext_select; // When set, register clr_int_reg_48 is
1725 // selected. This signal is a pulse.
1726wire [1:0] clr_int_reg_48_int_state_ext_read_data; // Ext read data (decode)
1727wire [1:0] clr_int_reg_49_int_state_ext_wr_data; // Provides SW write data for
1728 // external register
1729 // "clr_int_reg_49", field
1730 // "int_state"
1731wire clr_int_reg_49_ext_select; // When set, register clr_int_reg_49 is
1732 // selected. This signal is a pulse.
1733wire [1:0] clr_int_reg_49_int_state_ext_read_data; // Ext read data (decode)
1734wire [1:0] clr_int_reg_50_int_state_ext_wr_data; // Provides SW write data for
1735 // external register
1736 // "clr_int_reg_50", field
1737 // "int_state"
1738wire clr_int_reg_50_ext_select; // When set, register clr_int_reg_50 is
1739 // selected. This signal is a pulse.
1740wire [1:0] clr_int_reg_50_int_state_ext_read_data; // Ext read data (decode)
1741wire [1:0] clr_int_reg_51_int_state_ext_wr_data; // Provides SW write data for
1742 // external register
1743 // "clr_int_reg_51", field
1744 // "int_state"
1745wire clr_int_reg_51_ext_select; // When set, register clr_int_reg_51 is
1746 // selected. This signal is a pulse.
1747wire [1:0] clr_int_reg_51_int_state_ext_read_data; // Ext read data (decode)
1748wire [1:0] clr_int_reg_52_int_state_ext_wr_data; // Provides SW write data for
1749 // external register
1750 // "clr_int_reg_52", field
1751 // "int_state"
1752wire clr_int_reg_52_ext_select; // When set, register clr_int_reg_52 is
1753 // selected. This signal is a pulse.
1754wire [1:0] clr_int_reg_52_int_state_ext_read_data; // Ext read data (decode)
1755wire [1:0] clr_int_reg_53_int_state_ext_wr_data; // Provides SW write data for
1756 // external register
1757 // "clr_int_reg_53", field
1758 // "int_state"
1759wire clr_int_reg_53_ext_select; // When set, register clr_int_reg_53 is
1760 // selected. This signal is a pulse.
1761wire [1:0] clr_int_reg_53_int_state_ext_read_data; // Ext read data (decode)
1762wire [1:0] clr_int_reg_54_int_state_ext_wr_data; // Provides SW write data for
1763 // external register
1764 // "clr_int_reg_54", field
1765 // "int_state"
1766wire clr_int_reg_54_ext_select; // When set, register clr_int_reg_54 is
1767 // selected. This signal is a pulse.
1768wire [1:0] clr_int_reg_54_int_state_ext_read_data; // Ext read data (decode)
1769wire [1:0] clr_int_reg_55_int_state_ext_wr_data; // Provides SW write data for
1770 // external register
1771 // "clr_int_reg_55", field
1772 // "int_state"
1773wire clr_int_reg_55_ext_select; // When set, register clr_int_reg_55 is
1774 // selected. This signal is a pulse.
1775wire [1:0] clr_int_reg_55_int_state_ext_read_data; // Ext read data (decode)
1776wire [1:0] clr_int_reg_56_int_state_ext_wr_data; // Provides SW write data for
1777 // external register
1778 // "clr_int_reg_56", field
1779 // "int_state"
1780wire clr_int_reg_56_ext_select; // When set, register clr_int_reg_56 is
1781 // selected. This signal is a pulse.
1782wire [1:0] clr_int_reg_56_int_state_ext_read_data; // Ext read data (decode)
1783wire [1:0] clr_int_reg_57_int_state_ext_wr_data; // Provides SW write data for
1784 // external register
1785 // "clr_int_reg_57", field
1786 // "int_state"
1787wire clr_int_reg_57_ext_select; // When set, register clr_int_reg_57 is
1788 // selected. This signal is a pulse.
1789wire [1:0] clr_int_reg_57_int_state_ext_read_data; // Ext read data (decode)
1790wire [1:0] clr_int_reg_58_int_state_ext_wr_data; // Provides SW write data for
1791 // external register
1792 // "clr_int_reg_58", field
1793 // "int_state"
1794wire clr_int_reg_58_ext_select; // When set, register clr_int_reg_58 is
1795 // selected. This signal is a pulse.
1796wire [1:0] clr_int_reg_58_int_state_ext_read_data; // Ext read data (decode)
1797wire [1:0] clr_int_reg_59_int_state_ext_wr_data; // Provides SW write data for
1798 // external register
1799 // "clr_int_reg_59", field
1800 // "int_state"
1801wire clr_int_reg_59_ext_select; // When set, register clr_int_reg_59 is
1802 // selected. This signal is a pulse.
1803wire [1:0] clr_int_reg_59_int_state_ext_read_data; // Ext read data (decode)
1804wire [1:0] clr_int_reg_62_int_state_ext_wr_data; // Provides SW write data for
1805 // external register
1806 // "clr_int_reg_62", field
1807 // "int_state"
1808wire clr_int_reg_62_ext_select; // When set, register clr_int_reg_62 is
1809 // selected. This signal is a pulse.
1810wire [1:0] clr_int_reg_62_int_state_ext_read_data; // Ext read data (decode)
1811wire [1:0] clr_int_reg_63_int_state_ext_wr_data; // Provides SW write data for
1812 // external register
1813 // "clr_int_reg_63", field
1814 // "int_state"
1815wire clr_int_reg_63_ext_select; // When set, register clr_int_reg_63 is
1816 // selected. This signal is a pulse.
1817wire [1:0] clr_int_reg_63_int_state_ext_read_data; // Ext read data (decode)
1818wire [`FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_INT_SLC] interrupt_retry_timer_limit_hw_read;
1819 // This signal provides the current value of interrupt_retry_timer_limit.
1820wire [23:0] interrupt_state_status_1_state_ext_read_data; // Ext read data
1821 // (decode)
1822wire [63:0] interrupt_state_status_2_state_ext_read_data; // Ext read data
1823 // (decode)
1824
1825//====================================================
1826// Logic
1827//====================================================
1828wire daemon_transaction_in_progress;
1829wire daemon_csrbus_mapped;
1830wire daemon_csrbus_valid;
1831// vlint flag_dangling_net_within_module off
1832// vlint flag_net_has_no_load off
1833wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data_tmp;
1834wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] daemon_csrbus_wr_data;
1835// vlint flag_dangling_net_within_module on
1836// vlint flag_net_has_no_load on
1837wire daemon_csrbus_done;
1838wire [`FIRE_CSRBUS_ADDR_WIDTH-1:0] daemon_csrbus_addr;
1839wire daemon_csrbus_wr_tmp;
1840wire daemon_csrbus_wr;
1841
1842//summit modcovoff -bepgnv
1843pcie_dcm_daemon #(`FIRE_CSRBUS_ADDR_WIDTH,`FIRE_CSRBUS_DATA_WIDTH) pcie_dcm_daemon (
1844 .daemon_csrbus_valid (daemon_csrbus_valid),
1845 .daemon_csrbus_mapped (daemon_csrbus_mapped),
1846 .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
1847 .daemon_csrbus_done (daemon_csrbus_done),
1848 .daemon_csrbus_addr (daemon_csrbus_addr),
1849 .daemon_csrbus_wr (daemon_csrbus_wr_tmp),
1850 .daemon_transaction_in_progress (daemon_transaction_in_progress),
1851// synopsys translate_off
1852 .clk(clk),
1853 .csrbus_read_data (csrbus_read_data),
1854 .rst_l (rst_l),
1855// synopsys translate_on
1856 .csrbus_valid (csrbus_valid),
1857 .csrbus_mapped (csrbus_mapped),
1858 .csrbus_wr_data (csrbus_wr_data),
1859 .csrbus_done (csrbus_done),
1860 .csrbus_addr (csrbus_addr),
1861 .csrbus_wr (csrbus_wr)
1862 );
1863//summit modcovon -bepgnv
1864
1865//====================================================================
1866// Address decode
1867//====================================================================
1868wire interrupt_mapping_20_select_pulse;
1869wire interrupt_mapping_21_select_pulse;
1870wire interrupt_mapping_22_select_pulse;
1871wire interrupt_mapping_23_select_pulse;
1872wire interrupt_mapping_24_select_pulse;
1873wire interrupt_mapping_25_select_pulse;
1874wire interrupt_mapping_26_select_pulse;
1875wire interrupt_mapping_27_select_pulse;
1876wire interrupt_mapping_28_select_pulse;
1877wire interrupt_mapping_29_select_pulse;
1878wire interrupt_mapping_30_select_pulse;
1879wire interrupt_mapping_31_select_pulse;
1880wire interrupt_mapping_32_select_pulse;
1881wire interrupt_mapping_33_select_pulse;
1882wire interrupt_mapping_34_select_pulse;
1883wire interrupt_mapping_35_select_pulse;
1884wire interrupt_mapping_36_select_pulse;
1885wire interrupt_mapping_37_select_pulse;
1886wire interrupt_mapping_38_select_pulse;
1887wire interrupt_mapping_39_select_pulse;
1888wire interrupt_mapping_40_select_pulse;
1889wire interrupt_mapping_41_select_pulse;
1890wire interrupt_mapping_42_select_pulse;
1891wire interrupt_mapping_43_select_pulse;
1892wire interrupt_mapping_44_select_pulse;
1893wire interrupt_mapping_45_select_pulse;
1894wire interrupt_mapping_46_select_pulse;
1895wire interrupt_mapping_47_select_pulse;
1896wire interrupt_mapping_48_select_pulse;
1897wire interrupt_mapping_49_select_pulse;
1898wire interrupt_mapping_50_select_pulse;
1899wire interrupt_mapping_51_select_pulse;
1900wire interrupt_mapping_52_select_pulse;
1901wire interrupt_mapping_53_select_pulse;
1902wire interrupt_mapping_54_select_pulse;
1903wire interrupt_mapping_55_select_pulse;
1904wire interrupt_mapping_56_select_pulse;
1905wire interrupt_mapping_57_select_pulse;
1906wire interrupt_mapping_58_select_pulse;
1907wire interrupt_mapping_59_select_pulse;
1908wire interrupt_mapping_62_select_pulse;
1909wire interrupt_mapping_63_select_pulse;
1910wire clr_int_reg_20_select;
1911wire clr_int_reg_21_select;
1912wire clr_int_reg_22_select;
1913wire clr_int_reg_23_select;
1914wire clr_int_reg_24_select;
1915wire clr_int_reg_25_select;
1916wire clr_int_reg_26_select;
1917wire clr_int_reg_27_select;
1918wire clr_int_reg_28_select;
1919wire clr_int_reg_29_select;
1920wire clr_int_reg_30_select;
1921wire clr_int_reg_31_select;
1922wire clr_int_reg_32_select;
1923wire clr_int_reg_33_select;
1924wire clr_int_reg_34_select;
1925wire clr_int_reg_35_select;
1926wire clr_int_reg_36_select;
1927wire clr_int_reg_37_select;
1928wire clr_int_reg_38_select;
1929wire clr_int_reg_39_select;
1930wire clr_int_reg_40_select;
1931wire clr_int_reg_41_select;
1932wire clr_int_reg_42_select;
1933wire clr_int_reg_43_select;
1934wire clr_int_reg_44_select;
1935wire clr_int_reg_45_select;
1936wire clr_int_reg_46_select;
1937wire clr_int_reg_47_select;
1938wire clr_int_reg_48_select;
1939wire clr_int_reg_49_select;
1940wire clr_int_reg_50_select;
1941wire clr_int_reg_51_select;
1942wire clr_int_reg_52_select;
1943wire clr_int_reg_53_select;
1944wire clr_int_reg_54_select;
1945wire clr_int_reg_55_select;
1946wire clr_int_reg_56_select;
1947wire clr_int_reg_57_select;
1948wire clr_int_reg_58_select;
1949wire clr_int_reg_59_select;
1950wire clr_int_reg_62_select;
1951wire clr_int_reg_63_select;
1952wire interrupt_retry_timer_select_pulse;
1953wire interrupt_state_status_1_select;
1954wire interrupt_state_status_2_select;
1955
1956dmu_imu_iss_addr_decode dmu_imu_iss_addr_decode
1957 (
1958 .clk (clk),
1959 .rst_l (rst_l),
1960 .daemon_csrbus_valid (daemon_csrbus_valid),
1961 .daemon_csrbus_addr (daemon_csrbus_addr),
1962 .csrbus_src_bus (csrbus_src_bus),
1963 .daemon_csrbus_wr (daemon_csrbus_wr_tmp),
1964 .daemon_csrbus_wr_out (daemon_csrbus_wr),
1965 .daemon_csrbus_wr_data (daemon_csrbus_wr_data_tmp),
1966 .daemon_csrbus_wr_data_out (daemon_csrbus_wr_data),
1967 .daemon_csrbus_mapped (daemon_csrbus_mapped),
1968 .csrbus_acc_vio (csrbus_acc_vio),
1969 .daemon_transaction_in_progress (daemon_transaction_in_progress),
1970 .instance_id (instance_id),
1971 .daemon_csrbus_done (daemon_csrbus_done),
1972 .interrupt_mapping_20_select_pulse (interrupt_mapping_20_select_pulse),
1973 .interrupt_mapping_21_select_pulse (interrupt_mapping_21_select_pulse),
1974 .interrupt_mapping_22_select_pulse (interrupt_mapping_22_select_pulse),
1975 .interrupt_mapping_23_select_pulse (interrupt_mapping_23_select_pulse),
1976 .interrupt_mapping_24_select_pulse (interrupt_mapping_24_select_pulse),
1977 .interrupt_mapping_25_select_pulse (interrupt_mapping_25_select_pulse),
1978 .interrupt_mapping_26_select_pulse (interrupt_mapping_26_select_pulse),
1979 .interrupt_mapping_27_select_pulse (interrupt_mapping_27_select_pulse),
1980 .interrupt_mapping_28_select_pulse (interrupt_mapping_28_select_pulse),
1981 .interrupt_mapping_29_select_pulse (interrupt_mapping_29_select_pulse),
1982 .interrupt_mapping_30_select_pulse (interrupt_mapping_30_select_pulse),
1983 .interrupt_mapping_31_select_pulse (interrupt_mapping_31_select_pulse),
1984 .interrupt_mapping_32_select_pulse (interrupt_mapping_32_select_pulse),
1985 .interrupt_mapping_33_select_pulse (interrupt_mapping_33_select_pulse),
1986 .interrupt_mapping_34_select_pulse (interrupt_mapping_34_select_pulse),
1987 .interrupt_mapping_35_select_pulse (interrupt_mapping_35_select_pulse),
1988 .interrupt_mapping_36_select_pulse (interrupt_mapping_36_select_pulse),
1989 .interrupt_mapping_37_select_pulse (interrupt_mapping_37_select_pulse),
1990 .interrupt_mapping_38_select_pulse (interrupt_mapping_38_select_pulse),
1991 .interrupt_mapping_39_select_pulse (interrupt_mapping_39_select_pulse),
1992 .interrupt_mapping_40_select_pulse (interrupt_mapping_40_select_pulse),
1993 .interrupt_mapping_41_select_pulse (interrupt_mapping_41_select_pulse),
1994 .interrupt_mapping_42_select_pulse (interrupt_mapping_42_select_pulse),
1995 .interrupt_mapping_43_select_pulse (interrupt_mapping_43_select_pulse),
1996 .interrupt_mapping_44_select_pulse (interrupt_mapping_44_select_pulse),
1997 .interrupt_mapping_45_select_pulse (interrupt_mapping_45_select_pulse),
1998 .interrupt_mapping_46_select_pulse (interrupt_mapping_46_select_pulse),
1999 .interrupt_mapping_47_select_pulse (interrupt_mapping_47_select_pulse),
2000 .interrupt_mapping_48_select_pulse (interrupt_mapping_48_select_pulse),
2001 .interrupt_mapping_49_select_pulse (interrupt_mapping_49_select_pulse),
2002 .interrupt_mapping_50_select_pulse (interrupt_mapping_50_select_pulse),
2003 .interrupt_mapping_51_select_pulse (interrupt_mapping_51_select_pulse),
2004 .interrupt_mapping_52_select_pulse (interrupt_mapping_52_select_pulse),
2005 .interrupt_mapping_53_select_pulse (interrupt_mapping_53_select_pulse),
2006 .interrupt_mapping_54_select_pulse (interrupt_mapping_54_select_pulse),
2007 .interrupt_mapping_55_select_pulse (interrupt_mapping_55_select_pulse),
2008 .interrupt_mapping_56_select_pulse (interrupt_mapping_56_select_pulse),
2009 .interrupt_mapping_57_select_pulse (interrupt_mapping_57_select_pulse),
2010 .interrupt_mapping_58_select_pulse (interrupt_mapping_58_select_pulse),
2011 .interrupt_mapping_59_select_pulse (interrupt_mapping_59_select_pulse),
2012 .interrupt_mapping_62_select_pulse (interrupt_mapping_62_select_pulse),
2013 .interrupt_mapping_63_select_pulse (interrupt_mapping_63_select_pulse),
2014 .clr_int_reg_20_select (clr_int_reg_20_select),
2015 .clr_int_reg_21_select (clr_int_reg_21_select),
2016 .clr_int_reg_22_select (clr_int_reg_22_select),
2017 .clr_int_reg_23_select (clr_int_reg_23_select),
2018 .clr_int_reg_24_select (clr_int_reg_24_select),
2019 .clr_int_reg_25_select (clr_int_reg_25_select),
2020 .clr_int_reg_26_select (clr_int_reg_26_select),
2021 .clr_int_reg_27_select (clr_int_reg_27_select),
2022 .clr_int_reg_28_select (clr_int_reg_28_select),
2023 .clr_int_reg_29_select (clr_int_reg_29_select),
2024 .clr_int_reg_30_select (clr_int_reg_30_select),
2025 .clr_int_reg_31_select (clr_int_reg_31_select),
2026 .clr_int_reg_32_select (clr_int_reg_32_select),
2027 .clr_int_reg_33_select (clr_int_reg_33_select),
2028 .clr_int_reg_34_select (clr_int_reg_34_select),
2029 .clr_int_reg_35_select (clr_int_reg_35_select),
2030 .clr_int_reg_36_select (clr_int_reg_36_select),
2031 .clr_int_reg_37_select (clr_int_reg_37_select),
2032 .clr_int_reg_38_select (clr_int_reg_38_select),
2033 .clr_int_reg_39_select (clr_int_reg_39_select),
2034 .clr_int_reg_40_select (clr_int_reg_40_select),
2035 .clr_int_reg_41_select (clr_int_reg_41_select),
2036 .clr_int_reg_42_select (clr_int_reg_42_select),
2037 .clr_int_reg_43_select (clr_int_reg_43_select),
2038 .clr_int_reg_44_select (clr_int_reg_44_select),
2039 .clr_int_reg_45_select (clr_int_reg_45_select),
2040 .clr_int_reg_46_select (clr_int_reg_46_select),
2041 .clr_int_reg_47_select (clr_int_reg_47_select),
2042 .clr_int_reg_48_select (clr_int_reg_48_select),
2043 .clr_int_reg_49_select (clr_int_reg_49_select),
2044 .clr_int_reg_50_select (clr_int_reg_50_select),
2045 .clr_int_reg_51_select (clr_int_reg_51_select),
2046 .clr_int_reg_52_select (clr_int_reg_52_select),
2047 .clr_int_reg_53_select (clr_int_reg_53_select),
2048 .clr_int_reg_54_select (clr_int_reg_54_select),
2049 .clr_int_reg_55_select (clr_int_reg_55_select),
2050 .clr_int_reg_56_select (clr_int_reg_56_select),
2051 .clr_int_reg_57_select (clr_int_reg_57_select),
2052 .clr_int_reg_58_select (clr_int_reg_58_select),
2053 .clr_int_reg_59_select (clr_int_reg_59_select),
2054 .clr_int_reg_62_select (clr_int_reg_62_select),
2055 .clr_int_reg_63_select (clr_int_reg_63_select),
2056 .interrupt_retry_timer_select_pulse (interrupt_retry_timer_select_pulse),
2057 .interrupt_state_status_1_select (interrupt_state_status_1_select),
2058 .interrupt_state_status_2_select (interrupt_state_status_2_select)
2059 );
2060
2061//====================================================================
2062// OUTPUT: csrbus_read_data (pipelining)
2063//====================================================================
2064//----- connecting wires
2065wire stage_mux_only_rst_l;
2066wire stage_mux_only_daemon_csrbus_wr;
2067wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_daemon_csrbus_wr_data;
2068
2069//----- Stage: 1 / Grp: default_grp (87 inputs / 1 outputs)
2070wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] default_grp_read_data_0_out;
2071wire default_grp_interrupt_mapping_20_select_pulse;
2072wire default_grp_interrupt_mapping_21_select_pulse;
2073wire default_grp_interrupt_mapping_22_select_pulse;
2074wire default_grp_interrupt_mapping_23_select_pulse;
2075wire default_grp_interrupt_mapping_24_select_pulse;
2076wire default_grp_interrupt_mapping_25_select_pulse;
2077wire default_grp_interrupt_mapping_26_select_pulse;
2078wire default_grp_interrupt_mapping_27_select_pulse;
2079wire default_grp_interrupt_mapping_28_select_pulse;
2080wire default_grp_interrupt_mapping_29_select_pulse;
2081wire default_grp_interrupt_mapping_30_select_pulse;
2082wire default_grp_interrupt_mapping_31_select_pulse;
2083wire default_grp_interrupt_mapping_32_select_pulse;
2084wire default_grp_interrupt_mapping_33_select_pulse;
2085wire default_grp_interrupt_mapping_34_select_pulse;
2086wire default_grp_interrupt_mapping_35_select_pulse;
2087wire default_grp_interrupt_mapping_36_select_pulse;
2088wire default_grp_interrupt_mapping_37_select_pulse;
2089wire default_grp_interrupt_mapping_38_select_pulse;
2090wire default_grp_interrupt_mapping_39_select_pulse;
2091wire default_grp_interrupt_mapping_40_select_pulse;
2092wire default_grp_interrupt_mapping_41_select_pulse;
2093wire default_grp_interrupt_mapping_42_select_pulse;
2094wire default_grp_interrupt_mapping_43_select_pulse;
2095wire default_grp_interrupt_mapping_44_select_pulse;
2096wire default_grp_interrupt_mapping_45_select_pulse;
2097wire default_grp_interrupt_mapping_46_select_pulse;
2098wire default_grp_interrupt_mapping_47_select_pulse;
2099wire default_grp_interrupt_mapping_48_select_pulse;
2100wire default_grp_interrupt_mapping_49_select_pulse;
2101wire default_grp_interrupt_mapping_50_select_pulse;
2102wire default_grp_interrupt_mapping_51_select_pulse;
2103wire default_grp_interrupt_mapping_52_select_pulse;
2104wire default_grp_interrupt_mapping_53_select_pulse;
2105wire default_grp_interrupt_mapping_54_select_pulse;
2106wire default_grp_interrupt_mapping_55_select_pulse;
2107wire default_grp_interrupt_mapping_56_select_pulse;
2108wire default_grp_interrupt_mapping_57_select_pulse;
2109wire default_grp_interrupt_mapping_58_select_pulse;
2110wire default_grp_interrupt_mapping_59_select_pulse;
2111wire default_grp_interrupt_mapping_62_select_pulse;
2112wire default_grp_interrupt_mapping_63_select_pulse;
2113wire default_grp_clr_int_reg_20_select;
2114wire default_grp_clr_int_reg_21_select;
2115wire default_grp_clr_int_reg_22_select;
2116wire default_grp_clr_int_reg_23_select;
2117wire default_grp_clr_int_reg_24_select;
2118wire default_grp_clr_int_reg_25_select;
2119wire default_grp_clr_int_reg_26_select;
2120wire default_grp_clr_int_reg_27_select;
2121wire default_grp_clr_int_reg_28_select;
2122wire default_grp_clr_int_reg_29_select;
2123wire default_grp_clr_int_reg_30_select;
2124wire default_grp_clr_int_reg_31_select;
2125wire default_grp_clr_int_reg_32_select;
2126wire default_grp_clr_int_reg_33_select;
2127wire default_grp_clr_int_reg_34_select;
2128wire default_grp_clr_int_reg_35_select;
2129wire default_grp_clr_int_reg_36_select;
2130wire default_grp_clr_int_reg_37_select;
2131wire default_grp_clr_int_reg_38_select;
2132wire default_grp_clr_int_reg_39_select;
2133wire default_grp_clr_int_reg_40_select;
2134wire default_grp_clr_int_reg_41_select;
2135wire default_grp_clr_int_reg_42_select;
2136wire default_grp_clr_int_reg_43_select;
2137wire default_grp_clr_int_reg_44_select;
2138wire default_grp_clr_int_reg_45_select;
2139wire default_grp_clr_int_reg_46_select;
2140wire default_grp_clr_int_reg_47_select;
2141wire default_grp_clr_int_reg_48_select;
2142wire default_grp_clr_int_reg_49_select;
2143wire default_grp_clr_int_reg_50_select;
2144wire default_grp_clr_int_reg_51_select;
2145wire default_grp_clr_int_reg_52_select;
2146wire default_grp_clr_int_reg_53_select;
2147wire default_grp_clr_int_reg_54_select;
2148wire default_grp_clr_int_reg_55_select;
2149wire default_grp_clr_int_reg_56_select;
2150wire default_grp_clr_int_reg_57_select;
2151wire default_grp_clr_int_reg_58_select;
2152wire default_grp_clr_int_reg_59_select;
2153wire default_grp_clr_int_reg_62_select;
2154wire default_grp_clr_int_reg_63_select;
2155wire default_grp_interrupt_retry_timer_select_pulse;
2156wire default_grp_interrupt_state_status_1_select;
2157wire default_grp_interrupt_state_status_2_select;
2158
2159dmu_imu_iss_default_grp dmu_imu_iss_default_grp
2160 (
2161 .clk (clk),
2162 .interrupt_mapping_20_mdo_mode_hw_read (interrupt_mapping_20_mdo_mode_hw_read),
2163 .interrupt_mapping_20_v_hw_read (interrupt_mapping_20_v_hw_read),
2164 .interrupt_mapping_20_t_id_hw_read (interrupt_mapping_20_t_id_hw_read),
2165 .interrupt_mapping_20_int_cntrl_num_hw_read (interrupt_mapping_20_int_cntrl_num_hw_read),
2166 .interrupt_mapping_20_select_pulse (default_grp_interrupt_mapping_20_select_pulse),
2167 .interrupt_mapping_21_mdo_mode_hw_read (interrupt_mapping_21_mdo_mode_hw_read),
2168 .interrupt_mapping_21_v_hw_read (interrupt_mapping_21_v_hw_read),
2169 .interrupt_mapping_21_t_id_hw_read (interrupt_mapping_21_t_id_hw_read),
2170 .interrupt_mapping_21_int_cntrl_num_hw_read (interrupt_mapping_21_int_cntrl_num_hw_read),
2171 .interrupt_mapping_21_select_pulse (default_grp_interrupt_mapping_21_select_pulse),
2172 .interrupt_mapping_22_mdo_mode_hw_read (interrupt_mapping_22_mdo_mode_hw_read),
2173 .interrupt_mapping_22_v_hw_read (interrupt_mapping_22_v_hw_read),
2174 .interrupt_mapping_22_t_id_hw_read (interrupt_mapping_22_t_id_hw_read),
2175 .interrupt_mapping_22_int_cntrl_num_hw_read (interrupt_mapping_22_int_cntrl_num_hw_read),
2176 .interrupt_mapping_22_select_pulse (default_grp_interrupt_mapping_22_select_pulse),
2177 .interrupt_mapping_23_mdo_mode_hw_read (interrupt_mapping_23_mdo_mode_hw_read),
2178 .interrupt_mapping_23_v_hw_read (interrupt_mapping_23_v_hw_read),
2179 .interrupt_mapping_23_t_id_hw_read (interrupt_mapping_23_t_id_hw_read),
2180 .interrupt_mapping_23_int_cntrl_num_hw_read (interrupt_mapping_23_int_cntrl_num_hw_read),
2181 .interrupt_mapping_23_select_pulse (default_grp_interrupt_mapping_23_select_pulse),
2182 .interrupt_mapping_24_mdo_mode_hw_read (interrupt_mapping_24_mdo_mode_hw_read),
2183 .interrupt_mapping_24_v_hw_read (interrupt_mapping_24_v_hw_read),
2184 .interrupt_mapping_24_t_id_hw_read (interrupt_mapping_24_t_id_hw_read),
2185 .interrupt_mapping_24_int_cntrl_num_hw_read (interrupt_mapping_24_int_cntrl_num_hw_read),
2186 .interrupt_mapping_24_select_pulse (default_grp_interrupt_mapping_24_select_pulse),
2187 .interrupt_mapping_25_mdo_mode_hw_read (interrupt_mapping_25_mdo_mode_hw_read),
2188 .interrupt_mapping_25_v_hw_read (interrupt_mapping_25_v_hw_read),
2189 .interrupt_mapping_25_t_id_hw_read (interrupt_mapping_25_t_id_hw_read),
2190 .interrupt_mapping_25_int_cntrl_num_hw_read (interrupt_mapping_25_int_cntrl_num_hw_read),
2191 .interrupt_mapping_25_select_pulse (default_grp_interrupt_mapping_25_select_pulse),
2192 .interrupt_mapping_26_mdo_mode_hw_read (interrupt_mapping_26_mdo_mode_hw_read),
2193 .interrupt_mapping_26_v_hw_read (interrupt_mapping_26_v_hw_read),
2194 .interrupt_mapping_26_t_id_hw_read (interrupt_mapping_26_t_id_hw_read),
2195 .interrupt_mapping_26_int_cntrl_num_hw_read (interrupt_mapping_26_int_cntrl_num_hw_read),
2196 .interrupt_mapping_26_select_pulse (default_grp_interrupt_mapping_26_select_pulse),
2197 .interrupt_mapping_27_mdo_mode_hw_read (interrupt_mapping_27_mdo_mode_hw_read),
2198 .interrupt_mapping_27_v_hw_read (interrupt_mapping_27_v_hw_read),
2199 .interrupt_mapping_27_t_id_hw_read (interrupt_mapping_27_t_id_hw_read),
2200 .interrupt_mapping_27_int_cntrl_num_hw_read (interrupt_mapping_27_int_cntrl_num_hw_read),
2201 .interrupt_mapping_27_select_pulse (default_grp_interrupt_mapping_27_select_pulse),
2202 .interrupt_mapping_28_mdo_mode_hw_read (interrupt_mapping_28_mdo_mode_hw_read),
2203 .interrupt_mapping_28_v_hw_read (interrupt_mapping_28_v_hw_read),
2204 .interrupt_mapping_28_t_id_hw_read (interrupt_mapping_28_t_id_hw_read),
2205 .interrupt_mapping_28_int_cntrl_num_hw_read (interrupt_mapping_28_int_cntrl_num_hw_read),
2206 .interrupt_mapping_28_select_pulse (default_grp_interrupt_mapping_28_select_pulse),
2207 .interrupt_mapping_29_mdo_mode_hw_read (interrupt_mapping_29_mdo_mode_hw_read),
2208 .interrupt_mapping_29_v_hw_read (interrupt_mapping_29_v_hw_read),
2209 .interrupt_mapping_29_t_id_hw_read (interrupt_mapping_29_t_id_hw_read),
2210 .interrupt_mapping_29_int_cntrl_num_hw_read (interrupt_mapping_29_int_cntrl_num_hw_read),
2211 .interrupt_mapping_29_select_pulse (default_grp_interrupt_mapping_29_select_pulse),
2212 .interrupt_mapping_30_mdo_mode_hw_read (interrupt_mapping_30_mdo_mode_hw_read),
2213 .interrupt_mapping_30_v_hw_read (interrupt_mapping_30_v_hw_read),
2214 .interrupt_mapping_30_t_id_hw_read (interrupt_mapping_30_t_id_hw_read),
2215 .interrupt_mapping_30_int_cntrl_num_hw_read (interrupt_mapping_30_int_cntrl_num_hw_read),
2216 .interrupt_mapping_30_select_pulse (default_grp_interrupt_mapping_30_select_pulse),
2217 .interrupt_mapping_31_mdo_mode_hw_read (interrupt_mapping_31_mdo_mode_hw_read),
2218 .interrupt_mapping_31_v_hw_read (interrupt_mapping_31_v_hw_read),
2219 .interrupt_mapping_31_t_id_hw_read (interrupt_mapping_31_t_id_hw_read),
2220 .interrupt_mapping_31_int_cntrl_num_hw_read (interrupt_mapping_31_int_cntrl_num_hw_read),
2221 .interrupt_mapping_31_select_pulse (default_grp_interrupt_mapping_31_select_pulse),
2222 .interrupt_mapping_32_mdo_mode_hw_read (interrupt_mapping_32_mdo_mode_hw_read),
2223 .interrupt_mapping_32_v_hw_read (interrupt_mapping_32_v_hw_read),
2224 .interrupt_mapping_32_t_id_hw_read (interrupt_mapping_32_t_id_hw_read),
2225 .interrupt_mapping_32_int_cntrl_num_hw_read (interrupt_mapping_32_int_cntrl_num_hw_read),
2226 .interrupt_mapping_32_select_pulse (default_grp_interrupt_mapping_32_select_pulse),
2227 .interrupt_mapping_33_mdo_mode_hw_read (interrupt_mapping_33_mdo_mode_hw_read),
2228 .interrupt_mapping_33_v_hw_read (interrupt_mapping_33_v_hw_read),
2229 .interrupt_mapping_33_t_id_hw_read (interrupt_mapping_33_t_id_hw_read),
2230 .interrupt_mapping_33_int_cntrl_num_hw_read (interrupt_mapping_33_int_cntrl_num_hw_read),
2231 .interrupt_mapping_33_select_pulse (default_grp_interrupt_mapping_33_select_pulse),
2232 .interrupt_mapping_34_mdo_mode_hw_read (interrupt_mapping_34_mdo_mode_hw_read),
2233 .interrupt_mapping_34_v_hw_read (interrupt_mapping_34_v_hw_read),
2234 .interrupt_mapping_34_t_id_hw_read (interrupt_mapping_34_t_id_hw_read),
2235 .interrupt_mapping_34_int_cntrl_num_hw_read (interrupt_mapping_34_int_cntrl_num_hw_read),
2236 .interrupt_mapping_34_select_pulse (default_grp_interrupt_mapping_34_select_pulse),
2237 .interrupt_mapping_35_mdo_mode_hw_read (interrupt_mapping_35_mdo_mode_hw_read),
2238 .interrupt_mapping_35_v_hw_read (interrupt_mapping_35_v_hw_read),
2239 .interrupt_mapping_35_t_id_hw_read (interrupt_mapping_35_t_id_hw_read),
2240 .interrupt_mapping_35_int_cntrl_num_hw_read (interrupt_mapping_35_int_cntrl_num_hw_read),
2241 .interrupt_mapping_35_select_pulse (default_grp_interrupt_mapping_35_select_pulse),
2242 .interrupt_mapping_36_mdo_mode_hw_read (interrupt_mapping_36_mdo_mode_hw_read),
2243 .interrupt_mapping_36_v_hw_read (interrupt_mapping_36_v_hw_read),
2244 .interrupt_mapping_36_t_id_hw_read (interrupt_mapping_36_t_id_hw_read),
2245 .interrupt_mapping_36_int_cntrl_num_hw_read (interrupt_mapping_36_int_cntrl_num_hw_read),
2246 .interrupt_mapping_36_select_pulse (default_grp_interrupt_mapping_36_select_pulse),
2247 .interrupt_mapping_37_mdo_mode_hw_read (interrupt_mapping_37_mdo_mode_hw_read),
2248 .interrupt_mapping_37_v_hw_read (interrupt_mapping_37_v_hw_read),
2249 .interrupt_mapping_37_t_id_hw_read (interrupt_mapping_37_t_id_hw_read),
2250 .interrupt_mapping_37_int_cntrl_num_hw_read (interrupt_mapping_37_int_cntrl_num_hw_read),
2251 .interrupt_mapping_37_select_pulse (default_grp_interrupt_mapping_37_select_pulse),
2252 .interrupt_mapping_38_mdo_mode_hw_read (interrupt_mapping_38_mdo_mode_hw_read),
2253 .interrupt_mapping_38_v_hw_read (interrupt_mapping_38_v_hw_read),
2254 .interrupt_mapping_38_t_id_hw_read (interrupt_mapping_38_t_id_hw_read),
2255 .interrupt_mapping_38_int_cntrl_num_hw_read (interrupt_mapping_38_int_cntrl_num_hw_read),
2256 .interrupt_mapping_38_select_pulse (default_grp_interrupt_mapping_38_select_pulse),
2257 .interrupt_mapping_39_mdo_mode_hw_read (interrupt_mapping_39_mdo_mode_hw_read),
2258 .interrupt_mapping_39_v_hw_read (interrupt_mapping_39_v_hw_read),
2259 .interrupt_mapping_39_t_id_hw_read (interrupt_mapping_39_t_id_hw_read),
2260 .interrupt_mapping_39_int_cntrl_num_hw_read (interrupt_mapping_39_int_cntrl_num_hw_read),
2261 .interrupt_mapping_39_select_pulse (default_grp_interrupt_mapping_39_select_pulse),
2262 .interrupt_mapping_40_mdo_mode_hw_read (interrupt_mapping_40_mdo_mode_hw_read),
2263 .interrupt_mapping_40_v_hw_read (interrupt_mapping_40_v_hw_read),
2264 .interrupt_mapping_40_t_id_hw_read (interrupt_mapping_40_t_id_hw_read),
2265 .interrupt_mapping_40_int_cntrl_num_hw_read (interrupt_mapping_40_int_cntrl_num_hw_read),
2266 .interrupt_mapping_40_select_pulse (default_grp_interrupt_mapping_40_select_pulse),
2267 .interrupt_mapping_41_mdo_mode_hw_read (interrupt_mapping_41_mdo_mode_hw_read),
2268 .interrupt_mapping_41_v_hw_read (interrupt_mapping_41_v_hw_read),
2269 .interrupt_mapping_41_t_id_hw_read (interrupt_mapping_41_t_id_hw_read),
2270 .interrupt_mapping_41_int_cntrl_num_hw_read (interrupt_mapping_41_int_cntrl_num_hw_read),
2271 .interrupt_mapping_41_select_pulse (default_grp_interrupt_mapping_41_select_pulse),
2272 .interrupt_mapping_42_mdo_mode_hw_read (interrupt_mapping_42_mdo_mode_hw_read),
2273 .interrupt_mapping_42_v_hw_read (interrupt_mapping_42_v_hw_read),
2274 .interrupt_mapping_42_t_id_hw_read (interrupt_mapping_42_t_id_hw_read),
2275 .interrupt_mapping_42_int_cntrl_num_hw_read (interrupt_mapping_42_int_cntrl_num_hw_read),
2276 .interrupt_mapping_42_select_pulse (default_grp_interrupt_mapping_42_select_pulse),
2277 .interrupt_mapping_43_mdo_mode_hw_read (interrupt_mapping_43_mdo_mode_hw_read),
2278 .interrupt_mapping_43_v_hw_read (interrupt_mapping_43_v_hw_read),
2279 .interrupt_mapping_43_t_id_hw_read (interrupt_mapping_43_t_id_hw_read),
2280 .interrupt_mapping_43_int_cntrl_num_hw_read (interrupt_mapping_43_int_cntrl_num_hw_read),
2281 .interrupt_mapping_43_select_pulse (default_grp_interrupt_mapping_43_select_pulse),
2282 .interrupt_mapping_44_mdo_mode_hw_read (interrupt_mapping_44_mdo_mode_hw_read),
2283 .interrupt_mapping_44_v_hw_read (interrupt_mapping_44_v_hw_read),
2284 .interrupt_mapping_44_t_id_hw_read (interrupt_mapping_44_t_id_hw_read),
2285 .interrupt_mapping_44_int_cntrl_num_hw_read (interrupt_mapping_44_int_cntrl_num_hw_read),
2286 .interrupt_mapping_44_select_pulse (default_grp_interrupt_mapping_44_select_pulse),
2287 .interrupt_mapping_45_mdo_mode_hw_read (interrupt_mapping_45_mdo_mode_hw_read),
2288 .interrupt_mapping_45_v_hw_read (interrupt_mapping_45_v_hw_read),
2289 .interrupt_mapping_45_t_id_hw_read (interrupt_mapping_45_t_id_hw_read),
2290 .interrupt_mapping_45_int_cntrl_num_hw_read (interrupt_mapping_45_int_cntrl_num_hw_read),
2291 .interrupt_mapping_45_select_pulse (default_grp_interrupt_mapping_45_select_pulse),
2292 .interrupt_mapping_46_mdo_mode_hw_read (interrupt_mapping_46_mdo_mode_hw_read),
2293 .interrupt_mapping_46_v_hw_read (interrupt_mapping_46_v_hw_read),
2294 .interrupt_mapping_46_t_id_hw_read (interrupt_mapping_46_t_id_hw_read),
2295 .interrupt_mapping_46_int_cntrl_num_hw_read (interrupt_mapping_46_int_cntrl_num_hw_read),
2296 .interrupt_mapping_46_select_pulse (default_grp_interrupt_mapping_46_select_pulse),
2297 .interrupt_mapping_47_mdo_mode_hw_read (interrupt_mapping_47_mdo_mode_hw_read),
2298 .interrupt_mapping_47_v_hw_read (interrupt_mapping_47_v_hw_read),
2299 .interrupt_mapping_47_t_id_hw_read (interrupt_mapping_47_t_id_hw_read),
2300 .interrupt_mapping_47_int_cntrl_num_hw_read (interrupt_mapping_47_int_cntrl_num_hw_read),
2301 .interrupt_mapping_47_select_pulse (default_grp_interrupt_mapping_47_select_pulse),
2302 .interrupt_mapping_48_mdo_mode_hw_read (interrupt_mapping_48_mdo_mode_hw_read),
2303 .interrupt_mapping_48_v_hw_read (interrupt_mapping_48_v_hw_read),
2304 .interrupt_mapping_48_t_id_hw_read (interrupt_mapping_48_t_id_hw_read),
2305 .interrupt_mapping_48_int_cntrl_num_hw_read (interrupt_mapping_48_int_cntrl_num_hw_read),
2306 .interrupt_mapping_48_select_pulse (default_grp_interrupt_mapping_48_select_pulse),
2307 .interrupt_mapping_49_mdo_mode_hw_read (interrupt_mapping_49_mdo_mode_hw_read),
2308 .interrupt_mapping_49_v_hw_read (interrupt_mapping_49_v_hw_read),
2309 .interrupt_mapping_49_t_id_hw_read (interrupt_mapping_49_t_id_hw_read),
2310 .interrupt_mapping_49_int_cntrl_num_hw_read (interrupt_mapping_49_int_cntrl_num_hw_read),
2311 .interrupt_mapping_49_select_pulse (default_grp_interrupt_mapping_49_select_pulse),
2312 .interrupt_mapping_50_mdo_mode_hw_read (interrupt_mapping_50_mdo_mode_hw_read),
2313 .interrupt_mapping_50_v_hw_read (interrupt_mapping_50_v_hw_read),
2314 .interrupt_mapping_50_t_id_hw_read (interrupt_mapping_50_t_id_hw_read),
2315 .interrupt_mapping_50_int_cntrl_num_hw_read (interrupt_mapping_50_int_cntrl_num_hw_read),
2316 .interrupt_mapping_50_select_pulse (default_grp_interrupt_mapping_50_select_pulse),
2317 .interrupt_mapping_51_mdo_mode_hw_read (interrupt_mapping_51_mdo_mode_hw_read),
2318 .interrupt_mapping_51_v_hw_read (interrupt_mapping_51_v_hw_read),
2319 .interrupt_mapping_51_t_id_hw_read (interrupt_mapping_51_t_id_hw_read),
2320 .interrupt_mapping_51_int_cntrl_num_hw_read (interrupt_mapping_51_int_cntrl_num_hw_read),
2321 .interrupt_mapping_51_select_pulse (default_grp_interrupt_mapping_51_select_pulse),
2322 .interrupt_mapping_52_mdo_mode_hw_read (interrupt_mapping_52_mdo_mode_hw_read),
2323 .interrupt_mapping_52_v_hw_read (interrupt_mapping_52_v_hw_read),
2324 .interrupt_mapping_52_t_id_hw_read (interrupt_mapping_52_t_id_hw_read),
2325 .interrupt_mapping_52_int_cntrl_num_hw_read (interrupt_mapping_52_int_cntrl_num_hw_read),
2326 .interrupt_mapping_52_select_pulse (default_grp_interrupt_mapping_52_select_pulse),
2327 .interrupt_mapping_53_mdo_mode_hw_read (interrupt_mapping_53_mdo_mode_hw_read),
2328 .interrupt_mapping_53_v_hw_read (interrupt_mapping_53_v_hw_read),
2329 .interrupt_mapping_53_t_id_hw_read (interrupt_mapping_53_t_id_hw_read),
2330 .interrupt_mapping_53_int_cntrl_num_hw_read (interrupt_mapping_53_int_cntrl_num_hw_read),
2331 .interrupt_mapping_53_select_pulse (default_grp_interrupt_mapping_53_select_pulse),
2332 .interrupt_mapping_54_mdo_mode_hw_read (interrupt_mapping_54_mdo_mode_hw_read),
2333 .interrupt_mapping_54_v_hw_read (interrupt_mapping_54_v_hw_read),
2334 .interrupt_mapping_54_t_id_hw_read (interrupt_mapping_54_t_id_hw_read),
2335 .interrupt_mapping_54_int_cntrl_num_hw_read (interrupt_mapping_54_int_cntrl_num_hw_read),
2336 .interrupt_mapping_54_select_pulse (default_grp_interrupt_mapping_54_select_pulse),
2337 .interrupt_mapping_55_mdo_mode_hw_read (interrupt_mapping_55_mdo_mode_hw_read),
2338 .interrupt_mapping_55_v_hw_read (interrupt_mapping_55_v_hw_read),
2339 .interrupt_mapping_55_t_id_hw_read (interrupt_mapping_55_t_id_hw_read),
2340 .interrupt_mapping_55_int_cntrl_num_hw_read (interrupt_mapping_55_int_cntrl_num_hw_read),
2341 .interrupt_mapping_55_select_pulse (default_grp_interrupt_mapping_55_select_pulse),
2342 .interrupt_mapping_56_mdo_mode_hw_read (interrupt_mapping_56_mdo_mode_hw_read),
2343 .interrupt_mapping_56_v_hw_read (interrupt_mapping_56_v_hw_read),
2344 .interrupt_mapping_56_t_id_hw_read (interrupt_mapping_56_t_id_hw_read),
2345 .interrupt_mapping_56_int_cntrl_num_hw_read (interrupt_mapping_56_int_cntrl_num_hw_read),
2346 .interrupt_mapping_56_select_pulse (default_grp_interrupt_mapping_56_select_pulse),
2347 .interrupt_mapping_57_mdo_mode_hw_read (interrupt_mapping_57_mdo_mode_hw_read),
2348 .interrupt_mapping_57_v_hw_read (interrupt_mapping_57_v_hw_read),
2349 .interrupt_mapping_57_t_id_hw_read (interrupt_mapping_57_t_id_hw_read),
2350 .interrupt_mapping_57_int_cntrl_num_hw_read (interrupt_mapping_57_int_cntrl_num_hw_read),
2351 .interrupt_mapping_57_select_pulse (default_grp_interrupt_mapping_57_select_pulse),
2352 .interrupt_mapping_58_mdo_mode_hw_read (interrupt_mapping_58_mdo_mode_hw_read),
2353 .interrupt_mapping_58_v_hw_read (interrupt_mapping_58_v_hw_read),
2354 .interrupt_mapping_58_t_id_hw_read (interrupt_mapping_58_t_id_hw_read),
2355 .interrupt_mapping_58_int_cntrl_num_hw_read (interrupt_mapping_58_int_cntrl_num_hw_read),
2356 .interrupt_mapping_58_select_pulse (default_grp_interrupt_mapping_58_select_pulse),
2357 .interrupt_mapping_59_mdo_mode_hw_read (interrupt_mapping_59_mdo_mode_hw_read),
2358 .interrupt_mapping_59_v_hw_read (interrupt_mapping_59_v_hw_read),
2359 .interrupt_mapping_59_t_id_hw_read (interrupt_mapping_59_t_id_hw_read),
2360 .interrupt_mapping_59_int_cntrl_num_hw_read (interrupt_mapping_59_int_cntrl_num_hw_read),
2361 .interrupt_mapping_59_select_pulse (default_grp_interrupt_mapping_59_select_pulse),
2362 .interrupt_mapping_62_mdo_mode_hw_read (interrupt_mapping_62_mdo_mode_hw_read),
2363 .interrupt_mapping_62_v_hw_read (interrupt_mapping_62_v_hw_read),
2364 .interrupt_mapping_62_t_id_hw_read (interrupt_mapping_62_t_id_hw_read),
2365 .interrupt_mapping_62_int_cntrl_num_hw_read (interrupt_mapping_62_int_cntrl_num_hw_read),
2366 .interrupt_mapping_62_select_pulse (default_grp_interrupt_mapping_62_select_pulse),
2367 .interrupt_mapping_63_mdo_mode_hw_read (interrupt_mapping_63_mdo_mode_hw_read),
2368 .interrupt_mapping_63_v_hw_read (interrupt_mapping_63_v_hw_read),
2369 .interrupt_mapping_63_t_id_hw_read (interrupt_mapping_63_t_id_hw_read),
2370 .interrupt_mapping_63_int_cntrl_num_hw_read (interrupt_mapping_63_int_cntrl_num_hw_read),
2371 .interrupt_mapping_63_select_pulse (default_grp_interrupt_mapping_63_select_pulse),
2372 .clr_int_reg_20_ext_select (clr_int_reg_20_ext_select),
2373 .clr_int_reg_20_select (default_grp_clr_int_reg_20_select),
2374 .clr_int_reg_20_ext_read_data
2375 (
2376 {
2377 62'b0,
2378 clr_int_reg_20_int_state_ext_read_data
2379 }),
2380 .clr_int_reg_20_int_state_ext_wr_data (clr_int_reg_20_int_state_ext_wr_data),
2381 .clr_int_reg_21_ext_select (clr_int_reg_21_ext_select),
2382 .clr_int_reg_21_select (default_grp_clr_int_reg_21_select),
2383 .clr_int_reg_21_ext_read_data
2384 (
2385 {
2386 62'b0,
2387 clr_int_reg_21_int_state_ext_read_data
2388 }),
2389 .clr_int_reg_21_int_state_ext_wr_data (clr_int_reg_21_int_state_ext_wr_data),
2390 .clr_int_reg_22_ext_select (clr_int_reg_22_ext_select),
2391 .clr_int_reg_22_select (default_grp_clr_int_reg_22_select),
2392 .clr_int_reg_22_ext_read_data
2393 (
2394 {
2395 62'b0,
2396 clr_int_reg_22_int_state_ext_read_data
2397 }),
2398 .clr_int_reg_22_int_state_ext_wr_data (clr_int_reg_22_int_state_ext_wr_data),
2399 .clr_int_reg_23_ext_select (clr_int_reg_23_ext_select),
2400 .clr_int_reg_23_select (default_grp_clr_int_reg_23_select),
2401 .clr_int_reg_23_ext_read_data
2402 (
2403 {
2404 62'b0,
2405 clr_int_reg_23_int_state_ext_read_data
2406 }),
2407 .clr_int_reg_23_int_state_ext_wr_data (clr_int_reg_23_int_state_ext_wr_data),
2408 .clr_int_reg_24_ext_select (clr_int_reg_24_ext_select),
2409 .clr_int_reg_24_select (default_grp_clr_int_reg_24_select),
2410 .clr_int_reg_24_ext_read_data
2411 (
2412 {
2413 62'b0,
2414 clr_int_reg_24_int_state_ext_read_data
2415 }),
2416 .clr_int_reg_24_int_state_ext_wr_data (clr_int_reg_24_int_state_ext_wr_data),
2417 .clr_int_reg_25_ext_select (clr_int_reg_25_ext_select),
2418 .clr_int_reg_25_select (default_grp_clr_int_reg_25_select),
2419 .clr_int_reg_25_ext_read_data
2420 (
2421 {
2422 62'b0,
2423 clr_int_reg_25_int_state_ext_read_data
2424 }),
2425 .clr_int_reg_25_int_state_ext_wr_data (clr_int_reg_25_int_state_ext_wr_data),
2426 .clr_int_reg_26_ext_select (clr_int_reg_26_ext_select),
2427 .clr_int_reg_26_select (default_grp_clr_int_reg_26_select),
2428 .clr_int_reg_26_ext_read_data
2429 (
2430 {
2431 62'b0,
2432 clr_int_reg_26_int_state_ext_read_data
2433 }),
2434 .clr_int_reg_26_int_state_ext_wr_data (clr_int_reg_26_int_state_ext_wr_data),
2435 .clr_int_reg_27_ext_select (clr_int_reg_27_ext_select),
2436 .clr_int_reg_27_select (default_grp_clr_int_reg_27_select),
2437 .clr_int_reg_27_ext_read_data
2438 (
2439 {
2440 62'b0,
2441 clr_int_reg_27_int_state_ext_read_data
2442 }),
2443 .clr_int_reg_27_int_state_ext_wr_data (clr_int_reg_27_int_state_ext_wr_data),
2444 .clr_int_reg_28_ext_select (clr_int_reg_28_ext_select),
2445 .clr_int_reg_28_select (default_grp_clr_int_reg_28_select),
2446 .clr_int_reg_28_ext_read_data
2447 (
2448 {
2449 62'b0,
2450 clr_int_reg_28_int_state_ext_read_data
2451 }),
2452 .clr_int_reg_28_int_state_ext_wr_data (clr_int_reg_28_int_state_ext_wr_data),
2453 .clr_int_reg_29_ext_select (clr_int_reg_29_ext_select),
2454 .clr_int_reg_29_select (default_grp_clr_int_reg_29_select),
2455 .clr_int_reg_29_ext_read_data
2456 (
2457 {
2458 62'b0,
2459 clr_int_reg_29_int_state_ext_read_data
2460 }),
2461 .clr_int_reg_29_int_state_ext_wr_data (clr_int_reg_29_int_state_ext_wr_data),
2462 .clr_int_reg_30_ext_select (clr_int_reg_30_ext_select),
2463 .clr_int_reg_30_select (default_grp_clr_int_reg_30_select),
2464 .clr_int_reg_30_ext_read_data
2465 (
2466 {
2467 62'b0,
2468 clr_int_reg_30_int_state_ext_read_data
2469 }),
2470 .clr_int_reg_30_int_state_ext_wr_data (clr_int_reg_30_int_state_ext_wr_data),
2471 .clr_int_reg_31_ext_select (clr_int_reg_31_ext_select),
2472 .clr_int_reg_31_select (default_grp_clr_int_reg_31_select),
2473 .clr_int_reg_31_ext_read_data
2474 (
2475 {
2476 62'b0,
2477 clr_int_reg_31_int_state_ext_read_data
2478 }),
2479 .clr_int_reg_31_int_state_ext_wr_data (clr_int_reg_31_int_state_ext_wr_data),
2480 .clr_int_reg_32_ext_select (clr_int_reg_32_ext_select),
2481 .clr_int_reg_32_select (default_grp_clr_int_reg_32_select),
2482 .clr_int_reg_32_ext_read_data
2483 (
2484 {
2485 62'b0,
2486 clr_int_reg_32_int_state_ext_read_data
2487 }),
2488 .clr_int_reg_32_int_state_ext_wr_data (clr_int_reg_32_int_state_ext_wr_data),
2489 .clr_int_reg_33_ext_select (clr_int_reg_33_ext_select),
2490 .clr_int_reg_33_select (default_grp_clr_int_reg_33_select),
2491 .clr_int_reg_33_ext_read_data
2492 (
2493 {
2494 62'b0,
2495 clr_int_reg_33_int_state_ext_read_data
2496 }),
2497 .clr_int_reg_33_int_state_ext_wr_data (clr_int_reg_33_int_state_ext_wr_data),
2498 .clr_int_reg_34_ext_select (clr_int_reg_34_ext_select),
2499 .clr_int_reg_34_select (default_grp_clr_int_reg_34_select),
2500 .clr_int_reg_34_ext_read_data
2501 (
2502 {
2503 62'b0,
2504 clr_int_reg_34_int_state_ext_read_data
2505 }),
2506 .clr_int_reg_34_int_state_ext_wr_data (clr_int_reg_34_int_state_ext_wr_data),
2507 .clr_int_reg_35_ext_select (clr_int_reg_35_ext_select),
2508 .clr_int_reg_35_select (default_grp_clr_int_reg_35_select),
2509 .clr_int_reg_35_ext_read_data
2510 (
2511 {
2512 62'b0,
2513 clr_int_reg_35_int_state_ext_read_data
2514 }),
2515 .clr_int_reg_35_int_state_ext_wr_data (clr_int_reg_35_int_state_ext_wr_data),
2516 .clr_int_reg_36_ext_select (clr_int_reg_36_ext_select),
2517 .clr_int_reg_36_select (default_grp_clr_int_reg_36_select),
2518 .clr_int_reg_36_ext_read_data
2519 (
2520 {
2521 62'b0,
2522 clr_int_reg_36_int_state_ext_read_data
2523 }),
2524 .clr_int_reg_36_int_state_ext_wr_data (clr_int_reg_36_int_state_ext_wr_data),
2525 .clr_int_reg_37_ext_select (clr_int_reg_37_ext_select),
2526 .clr_int_reg_37_select (default_grp_clr_int_reg_37_select),
2527 .clr_int_reg_37_ext_read_data
2528 (
2529 {
2530 62'b0,
2531 clr_int_reg_37_int_state_ext_read_data
2532 }),
2533 .clr_int_reg_37_int_state_ext_wr_data (clr_int_reg_37_int_state_ext_wr_data),
2534 .clr_int_reg_38_ext_select (clr_int_reg_38_ext_select),
2535 .clr_int_reg_38_select (default_grp_clr_int_reg_38_select),
2536 .clr_int_reg_38_ext_read_data
2537 (
2538 {
2539 62'b0,
2540 clr_int_reg_38_int_state_ext_read_data
2541 }),
2542 .clr_int_reg_38_int_state_ext_wr_data (clr_int_reg_38_int_state_ext_wr_data),
2543 .clr_int_reg_39_ext_select (clr_int_reg_39_ext_select),
2544 .clr_int_reg_39_select (default_grp_clr_int_reg_39_select),
2545 .clr_int_reg_39_ext_read_data
2546 (
2547 {
2548 62'b0,
2549 clr_int_reg_39_int_state_ext_read_data
2550 }),
2551 .clr_int_reg_39_int_state_ext_wr_data (clr_int_reg_39_int_state_ext_wr_data),
2552 .clr_int_reg_40_ext_select (clr_int_reg_40_ext_select),
2553 .clr_int_reg_40_select (default_grp_clr_int_reg_40_select),
2554 .clr_int_reg_40_ext_read_data
2555 (
2556 {
2557 62'b0,
2558 clr_int_reg_40_int_state_ext_read_data
2559 }),
2560 .clr_int_reg_40_int_state_ext_wr_data (clr_int_reg_40_int_state_ext_wr_data),
2561 .clr_int_reg_41_ext_select (clr_int_reg_41_ext_select),
2562 .clr_int_reg_41_select (default_grp_clr_int_reg_41_select),
2563 .clr_int_reg_41_ext_read_data
2564 (
2565 {
2566 62'b0,
2567 clr_int_reg_41_int_state_ext_read_data
2568 }),
2569 .clr_int_reg_41_int_state_ext_wr_data (clr_int_reg_41_int_state_ext_wr_data),
2570 .clr_int_reg_42_ext_select (clr_int_reg_42_ext_select),
2571 .clr_int_reg_42_select (default_grp_clr_int_reg_42_select),
2572 .clr_int_reg_42_ext_read_data
2573 (
2574 {
2575 62'b0,
2576 clr_int_reg_42_int_state_ext_read_data
2577 }),
2578 .clr_int_reg_42_int_state_ext_wr_data (clr_int_reg_42_int_state_ext_wr_data),
2579 .clr_int_reg_43_ext_select (clr_int_reg_43_ext_select),
2580 .clr_int_reg_43_select (default_grp_clr_int_reg_43_select),
2581 .clr_int_reg_43_ext_read_data
2582 (
2583 {
2584 62'b0,
2585 clr_int_reg_43_int_state_ext_read_data
2586 }),
2587 .clr_int_reg_43_int_state_ext_wr_data (clr_int_reg_43_int_state_ext_wr_data),
2588 .clr_int_reg_44_ext_select (clr_int_reg_44_ext_select),
2589 .clr_int_reg_44_select (default_grp_clr_int_reg_44_select),
2590 .clr_int_reg_44_ext_read_data
2591 (
2592 {
2593 62'b0,
2594 clr_int_reg_44_int_state_ext_read_data
2595 }),
2596 .clr_int_reg_44_int_state_ext_wr_data (clr_int_reg_44_int_state_ext_wr_data),
2597 .clr_int_reg_45_ext_select (clr_int_reg_45_ext_select),
2598 .clr_int_reg_45_select (default_grp_clr_int_reg_45_select),
2599 .clr_int_reg_45_ext_read_data
2600 (
2601 {
2602 62'b0,
2603 clr_int_reg_45_int_state_ext_read_data
2604 }),
2605 .clr_int_reg_45_int_state_ext_wr_data (clr_int_reg_45_int_state_ext_wr_data),
2606 .clr_int_reg_46_ext_select (clr_int_reg_46_ext_select),
2607 .clr_int_reg_46_select (default_grp_clr_int_reg_46_select),
2608 .clr_int_reg_46_ext_read_data
2609 (
2610 {
2611 62'b0,
2612 clr_int_reg_46_int_state_ext_read_data
2613 }),
2614 .clr_int_reg_46_int_state_ext_wr_data (clr_int_reg_46_int_state_ext_wr_data),
2615 .clr_int_reg_47_ext_select (clr_int_reg_47_ext_select),
2616 .clr_int_reg_47_select (default_grp_clr_int_reg_47_select),
2617 .clr_int_reg_47_ext_read_data
2618 (
2619 {
2620 62'b0,
2621 clr_int_reg_47_int_state_ext_read_data
2622 }),
2623 .clr_int_reg_47_int_state_ext_wr_data (clr_int_reg_47_int_state_ext_wr_data),
2624 .clr_int_reg_48_ext_select (clr_int_reg_48_ext_select),
2625 .clr_int_reg_48_select (default_grp_clr_int_reg_48_select),
2626 .clr_int_reg_48_ext_read_data
2627 (
2628 {
2629 62'b0,
2630 clr_int_reg_48_int_state_ext_read_data
2631 }),
2632 .clr_int_reg_48_int_state_ext_wr_data (clr_int_reg_48_int_state_ext_wr_data),
2633 .clr_int_reg_49_ext_select (clr_int_reg_49_ext_select),
2634 .clr_int_reg_49_select (default_grp_clr_int_reg_49_select),
2635 .clr_int_reg_49_ext_read_data
2636 (
2637 {
2638 62'b0,
2639 clr_int_reg_49_int_state_ext_read_data
2640 }),
2641 .clr_int_reg_49_int_state_ext_wr_data (clr_int_reg_49_int_state_ext_wr_data),
2642 .clr_int_reg_50_ext_select (clr_int_reg_50_ext_select),
2643 .clr_int_reg_50_select (default_grp_clr_int_reg_50_select),
2644 .clr_int_reg_50_ext_read_data
2645 (
2646 {
2647 62'b0,
2648 clr_int_reg_50_int_state_ext_read_data
2649 }),
2650 .clr_int_reg_50_int_state_ext_wr_data (clr_int_reg_50_int_state_ext_wr_data),
2651 .clr_int_reg_51_ext_select (clr_int_reg_51_ext_select),
2652 .clr_int_reg_51_select (default_grp_clr_int_reg_51_select),
2653 .clr_int_reg_51_ext_read_data
2654 (
2655 {
2656 62'b0,
2657 clr_int_reg_51_int_state_ext_read_data
2658 }),
2659 .clr_int_reg_51_int_state_ext_wr_data (clr_int_reg_51_int_state_ext_wr_data),
2660 .clr_int_reg_52_ext_select (clr_int_reg_52_ext_select),
2661 .clr_int_reg_52_select (default_grp_clr_int_reg_52_select),
2662 .clr_int_reg_52_ext_read_data
2663 (
2664 {
2665 62'b0,
2666 clr_int_reg_52_int_state_ext_read_data
2667 }),
2668 .clr_int_reg_52_int_state_ext_wr_data (clr_int_reg_52_int_state_ext_wr_data),
2669 .clr_int_reg_53_ext_select (clr_int_reg_53_ext_select),
2670 .clr_int_reg_53_select (default_grp_clr_int_reg_53_select),
2671 .clr_int_reg_53_ext_read_data
2672 (
2673 {
2674 62'b0,
2675 clr_int_reg_53_int_state_ext_read_data
2676 }),
2677 .clr_int_reg_53_int_state_ext_wr_data (clr_int_reg_53_int_state_ext_wr_data),
2678 .clr_int_reg_54_ext_select (clr_int_reg_54_ext_select),
2679 .clr_int_reg_54_select (default_grp_clr_int_reg_54_select),
2680 .clr_int_reg_54_ext_read_data
2681 (
2682 {
2683 62'b0,
2684 clr_int_reg_54_int_state_ext_read_data
2685 }),
2686 .clr_int_reg_54_int_state_ext_wr_data (clr_int_reg_54_int_state_ext_wr_data),
2687 .clr_int_reg_55_ext_select (clr_int_reg_55_ext_select),
2688 .clr_int_reg_55_select (default_grp_clr_int_reg_55_select),
2689 .clr_int_reg_55_ext_read_data
2690 (
2691 {
2692 62'b0,
2693 clr_int_reg_55_int_state_ext_read_data
2694 }),
2695 .clr_int_reg_55_int_state_ext_wr_data (clr_int_reg_55_int_state_ext_wr_data),
2696 .clr_int_reg_56_ext_select (clr_int_reg_56_ext_select),
2697 .clr_int_reg_56_select (default_grp_clr_int_reg_56_select),
2698 .clr_int_reg_56_ext_read_data
2699 (
2700 {
2701 62'b0,
2702 clr_int_reg_56_int_state_ext_read_data
2703 }),
2704 .clr_int_reg_56_int_state_ext_wr_data (clr_int_reg_56_int_state_ext_wr_data),
2705 .clr_int_reg_57_ext_select (clr_int_reg_57_ext_select),
2706 .clr_int_reg_57_select (default_grp_clr_int_reg_57_select),
2707 .clr_int_reg_57_ext_read_data
2708 (
2709 {
2710 62'b0,
2711 clr_int_reg_57_int_state_ext_read_data
2712 }),
2713 .clr_int_reg_57_int_state_ext_wr_data (clr_int_reg_57_int_state_ext_wr_data),
2714 .clr_int_reg_58_ext_select (clr_int_reg_58_ext_select),
2715 .clr_int_reg_58_select (default_grp_clr_int_reg_58_select),
2716 .clr_int_reg_58_ext_read_data
2717 (
2718 {
2719 62'b0,
2720 clr_int_reg_58_int_state_ext_read_data
2721 }),
2722 .clr_int_reg_58_int_state_ext_wr_data (clr_int_reg_58_int_state_ext_wr_data),
2723 .clr_int_reg_59_ext_select (clr_int_reg_59_ext_select),
2724 .clr_int_reg_59_select (default_grp_clr_int_reg_59_select),
2725 .clr_int_reg_59_ext_read_data
2726 (
2727 {
2728 62'b0,
2729 clr_int_reg_59_int_state_ext_read_data
2730 }),
2731 .clr_int_reg_59_int_state_ext_wr_data (clr_int_reg_59_int_state_ext_wr_data),
2732 .clr_int_reg_62_ext_select (clr_int_reg_62_ext_select),
2733 .clr_int_reg_62_select (default_grp_clr_int_reg_62_select),
2734 .clr_int_reg_62_ext_read_data
2735 (
2736 {
2737 62'b0,
2738 clr_int_reg_62_int_state_ext_read_data
2739 }),
2740 .clr_int_reg_62_int_state_ext_wr_data (clr_int_reg_62_int_state_ext_wr_data),
2741 .clr_int_reg_63_ext_select (clr_int_reg_63_ext_select),
2742 .clr_int_reg_63_select (default_grp_clr_int_reg_63_select),
2743 .clr_int_reg_63_ext_read_data
2744 (
2745 {
2746 62'b0,
2747 clr_int_reg_63_int_state_ext_read_data
2748 }),
2749 .clr_int_reg_63_int_state_ext_wr_data (clr_int_reg_63_int_state_ext_wr_data),
2750 .interrupt_retry_timer_limit_hw_read (interrupt_retry_timer_limit_hw_read),
2751 .interrupt_retry_timer_select_pulse (default_grp_interrupt_retry_timer_select_pulse),
2752 .interrupt_state_status_1_select (default_grp_interrupt_state_status_1_select),
2753 .interrupt_state_status_1_ext_read_data
2754 (
2755 {
2756 interrupt_state_status_1_state_ext_read_data,
2757 40'b0
2758 }),
2759 .interrupt_state_status_2_select (default_grp_interrupt_state_status_2_select),
2760 .interrupt_state_status_2_ext_read_data
2761 (
2762 {
2763 interrupt_state_status_2_state_ext_read_data
2764 }),
2765 .rst_l (stage_mux_only_rst_l),
2766 .daemon_csrbus_wr_in (stage_mux_only_daemon_csrbus_wr),
2767 .daemon_csrbus_wr_out (ext_wr),
2768 .daemon_csrbus_wr_data_in (stage_mux_only_daemon_csrbus_wr_data),
2769 .read_data_0_out (default_grp_read_data_0_out)
2770 );
2771
2772//----- Stage: 2 / Grp: stage_mux_only (1 inputs / 1 outputs) (Mux only)
2773wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] stage_mux_only_read_data_0_out;
2774
2775dmu_imu_iss_stage_mux_only dmu_imu_iss_stage_mux_only
2776 (
2777 .clk (clk),
2778 .read_data_0 (default_grp_read_data_0_out),
2779 .interrupt_mapping_20_select_pulse (interrupt_mapping_20_select_pulse),
2780 .interrupt_mapping_20_select_pulse_out (default_grp_interrupt_mapping_20_select_pulse),
2781 .interrupt_mapping_21_select_pulse (interrupt_mapping_21_select_pulse),
2782 .interrupt_mapping_21_select_pulse_out (default_grp_interrupt_mapping_21_select_pulse),
2783 .interrupt_mapping_22_select_pulse (interrupt_mapping_22_select_pulse),
2784 .interrupt_mapping_22_select_pulse_out (default_grp_interrupt_mapping_22_select_pulse),
2785 .interrupt_mapping_23_select_pulse (interrupt_mapping_23_select_pulse),
2786 .interrupt_mapping_23_select_pulse_out (default_grp_interrupt_mapping_23_select_pulse),
2787 .interrupt_mapping_24_select_pulse (interrupt_mapping_24_select_pulse),
2788 .interrupt_mapping_24_select_pulse_out (default_grp_interrupt_mapping_24_select_pulse),
2789 .interrupt_mapping_25_select_pulse (interrupt_mapping_25_select_pulse),
2790 .interrupt_mapping_25_select_pulse_out (default_grp_interrupt_mapping_25_select_pulse),
2791 .interrupt_mapping_26_select_pulse (interrupt_mapping_26_select_pulse),
2792 .interrupt_mapping_26_select_pulse_out (default_grp_interrupt_mapping_26_select_pulse),
2793 .interrupt_mapping_27_select_pulse (interrupt_mapping_27_select_pulse),
2794 .interrupt_mapping_27_select_pulse_out (default_grp_interrupt_mapping_27_select_pulse),
2795 .interrupt_mapping_28_select_pulse (interrupt_mapping_28_select_pulse),
2796 .interrupt_mapping_28_select_pulse_out (default_grp_interrupt_mapping_28_select_pulse),
2797 .interrupt_mapping_29_select_pulse (interrupt_mapping_29_select_pulse),
2798 .interrupt_mapping_29_select_pulse_out (default_grp_interrupt_mapping_29_select_pulse),
2799 .interrupt_mapping_30_select_pulse (interrupt_mapping_30_select_pulse),
2800 .interrupt_mapping_30_select_pulse_out (default_grp_interrupt_mapping_30_select_pulse),
2801 .interrupt_mapping_31_select_pulse (interrupt_mapping_31_select_pulse),
2802 .interrupt_mapping_31_select_pulse_out (default_grp_interrupt_mapping_31_select_pulse),
2803 .interrupt_mapping_32_select_pulse (interrupt_mapping_32_select_pulse),
2804 .interrupt_mapping_32_select_pulse_out (default_grp_interrupt_mapping_32_select_pulse),
2805 .interrupt_mapping_33_select_pulse (interrupt_mapping_33_select_pulse),
2806 .interrupt_mapping_33_select_pulse_out (default_grp_interrupt_mapping_33_select_pulse),
2807 .interrupt_mapping_34_select_pulse (interrupt_mapping_34_select_pulse),
2808 .interrupt_mapping_34_select_pulse_out (default_grp_interrupt_mapping_34_select_pulse),
2809 .interrupt_mapping_35_select_pulse (interrupt_mapping_35_select_pulse),
2810 .interrupt_mapping_35_select_pulse_out (default_grp_interrupt_mapping_35_select_pulse),
2811 .interrupt_mapping_36_select_pulse (interrupt_mapping_36_select_pulse),
2812 .interrupt_mapping_36_select_pulse_out (default_grp_interrupt_mapping_36_select_pulse),
2813 .interrupt_mapping_37_select_pulse (interrupt_mapping_37_select_pulse),
2814 .interrupt_mapping_37_select_pulse_out (default_grp_interrupt_mapping_37_select_pulse),
2815 .interrupt_mapping_38_select_pulse (interrupt_mapping_38_select_pulse),
2816 .interrupt_mapping_38_select_pulse_out (default_grp_interrupt_mapping_38_select_pulse),
2817 .interrupt_mapping_39_select_pulse (interrupt_mapping_39_select_pulse),
2818 .interrupt_mapping_39_select_pulse_out (default_grp_interrupt_mapping_39_select_pulse),
2819 .interrupt_mapping_40_select_pulse (interrupt_mapping_40_select_pulse),
2820 .interrupt_mapping_40_select_pulse_out (default_grp_interrupt_mapping_40_select_pulse),
2821 .interrupt_mapping_41_select_pulse (interrupt_mapping_41_select_pulse),
2822 .interrupt_mapping_41_select_pulse_out (default_grp_interrupt_mapping_41_select_pulse),
2823 .interrupt_mapping_42_select_pulse (interrupt_mapping_42_select_pulse),
2824 .interrupt_mapping_42_select_pulse_out (default_grp_interrupt_mapping_42_select_pulse),
2825 .interrupt_mapping_43_select_pulse (interrupt_mapping_43_select_pulse),
2826 .interrupt_mapping_43_select_pulse_out (default_grp_interrupt_mapping_43_select_pulse),
2827 .interrupt_mapping_44_select_pulse (interrupt_mapping_44_select_pulse),
2828 .interrupt_mapping_44_select_pulse_out (default_grp_interrupt_mapping_44_select_pulse),
2829 .interrupt_mapping_45_select_pulse (interrupt_mapping_45_select_pulse),
2830 .interrupt_mapping_45_select_pulse_out (default_grp_interrupt_mapping_45_select_pulse),
2831 .interrupt_mapping_46_select_pulse (interrupt_mapping_46_select_pulse),
2832 .interrupt_mapping_46_select_pulse_out (default_grp_interrupt_mapping_46_select_pulse),
2833 .interrupt_mapping_47_select_pulse (interrupt_mapping_47_select_pulse),
2834 .interrupt_mapping_47_select_pulse_out (default_grp_interrupt_mapping_47_select_pulse),
2835 .interrupt_mapping_48_select_pulse (interrupt_mapping_48_select_pulse),
2836 .interrupt_mapping_48_select_pulse_out (default_grp_interrupt_mapping_48_select_pulse),
2837 .interrupt_mapping_49_select_pulse (interrupt_mapping_49_select_pulse),
2838 .interrupt_mapping_49_select_pulse_out (default_grp_interrupt_mapping_49_select_pulse),
2839 .interrupt_mapping_50_select_pulse (interrupt_mapping_50_select_pulse),
2840 .interrupt_mapping_50_select_pulse_out (default_grp_interrupt_mapping_50_select_pulse),
2841 .interrupt_mapping_51_select_pulse (interrupt_mapping_51_select_pulse),
2842 .interrupt_mapping_51_select_pulse_out (default_grp_interrupt_mapping_51_select_pulse),
2843 .interrupt_mapping_52_select_pulse (interrupt_mapping_52_select_pulse),
2844 .interrupt_mapping_52_select_pulse_out (default_grp_interrupt_mapping_52_select_pulse),
2845 .interrupt_mapping_53_select_pulse (interrupt_mapping_53_select_pulse),
2846 .interrupt_mapping_53_select_pulse_out (default_grp_interrupt_mapping_53_select_pulse),
2847 .interrupt_mapping_54_select_pulse (interrupt_mapping_54_select_pulse),
2848 .interrupt_mapping_54_select_pulse_out (default_grp_interrupt_mapping_54_select_pulse),
2849 .interrupt_mapping_55_select_pulse (interrupt_mapping_55_select_pulse),
2850 .interrupt_mapping_55_select_pulse_out (default_grp_interrupt_mapping_55_select_pulse),
2851 .interrupt_mapping_56_select_pulse (interrupt_mapping_56_select_pulse),
2852 .interrupt_mapping_56_select_pulse_out (default_grp_interrupt_mapping_56_select_pulse),
2853 .interrupt_mapping_57_select_pulse (interrupt_mapping_57_select_pulse),
2854 .interrupt_mapping_57_select_pulse_out (default_grp_interrupt_mapping_57_select_pulse),
2855 .interrupt_mapping_58_select_pulse (interrupt_mapping_58_select_pulse),
2856 .interrupt_mapping_58_select_pulse_out (default_grp_interrupt_mapping_58_select_pulse),
2857 .interrupt_mapping_59_select_pulse (interrupt_mapping_59_select_pulse),
2858 .interrupt_mapping_59_select_pulse_out (default_grp_interrupt_mapping_59_select_pulse),
2859 .interrupt_mapping_62_select_pulse (interrupt_mapping_62_select_pulse),
2860 .interrupt_mapping_62_select_pulse_out (default_grp_interrupt_mapping_62_select_pulse),
2861 .interrupt_mapping_63_select_pulse (interrupt_mapping_63_select_pulse),
2862 .interrupt_mapping_63_select_pulse_out (default_grp_interrupt_mapping_63_select_pulse),
2863 .clr_int_reg_20_select (clr_int_reg_20_select),
2864 .clr_int_reg_20_select_out (default_grp_clr_int_reg_20_select),
2865 .clr_int_reg_21_select (clr_int_reg_21_select),
2866 .clr_int_reg_21_select_out (default_grp_clr_int_reg_21_select),
2867 .clr_int_reg_22_select (clr_int_reg_22_select),
2868 .clr_int_reg_22_select_out (default_grp_clr_int_reg_22_select),
2869 .clr_int_reg_23_select (clr_int_reg_23_select),
2870 .clr_int_reg_23_select_out (default_grp_clr_int_reg_23_select),
2871 .clr_int_reg_24_select (clr_int_reg_24_select),
2872 .clr_int_reg_24_select_out (default_grp_clr_int_reg_24_select),
2873 .clr_int_reg_25_select (clr_int_reg_25_select),
2874 .clr_int_reg_25_select_out (default_grp_clr_int_reg_25_select),
2875 .clr_int_reg_26_select (clr_int_reg_26_select),
2876 .clr_int_reg_26_select_out (default_grp_clr_int_reg_26_select),
2877 .clr_int_reg_27_select (clr_int_reg_27_select),
2878 .clr_int_reg_27_select_out (default_grp_clr_int_reg_27_select),
2879 .clr_int_reg_28_select (clr_int_reg_28_select),
2880 .clr_int_reg_28_select_out (default_grp_clr_int_reg_28_select),
2881 .clr_int_reg_29_select (clr_int_reg_29_select),
2882 .clr_int_reg_29_select_out (default_grp_clr_int_reg_29_select),
2883 .clr_int_reg_30_select (clr_int_reg_30_select),
2884 .clr_int_reg_30_select_out (default_grp_clr_int_reg_30_select),
2885 .clr_int_reg_31_select (clr_int_reg_31_select),
2886 .clr_int_reg_31_select_out (default_grp_clr_int_reg_31_select),
2887 .clr_int_reg_32_select (clr_int_reg_32_select),
2888 .clr_int_reg_32_select_out (default_grp_clr_int_reg_32_select),
2889 .clr_int_reg_33_select (clr_int_reg_33_select),
2890 .clr_int_reg_33_select_out (default_grp_clr_int_reg_33_select),
2891 .clr_int_reg_34_select (clr_int_reg_34_select),
2892 .clr_int_reg_34_select_out (default_grp_clr_int_reg_34_select),
2893 .clr_int_reg_35_select (clr_int_reg_35_select),
2894 .clr_int_reg_35_select_out (default_grp_clr_int_reg_35_select),
2895 .clr_int_reg_36_select (clr_int_reg_36_select),
2896 .clr_int_reg_36_select_out (default_grp_clr_int_reg_36_select),
2897 .clr_int_reg_37_select (clr_int_reg_37_select),
2898 .clr_int_reg_37_select_out (default_grp_clr_int_reg_37_select),
2899 .clr_int_reg_38_select (clr_int_reg_38_select),
2900 .clr_int_reg_38_select_out (default_grp_clr_int_reg_38_select),
2901 .clr_int_reg_39_select (clr_int_reg_39_select),
2902 .clr_int_reg_39_select_out (default_grp_clr_int_reg_39_select),
2903 .clr_int_reg_40_select (clr_int_reg_40_select),
2904 .clr_int_reg_40_select_out (default_grp_clr_int_reg_40_select),
2905 .clr_int_reg_41_select (clr_int_reg_41_select),
2906 .clr_int_reg_41_select_out (default_grp_clr_int_reg_41_select),
2907 .clr_int_reg_42_select (clr_int_reg_42_select),
2908 .clr_int_reg_42_select_out (default_grp_clr_int_reg_42_select),
2909 .clr_int_reg_43_select (clr_int_reg_43_select),
2910 .clr_int_reg_43_select_out (default_grp_clr_int_reg_43_select),
2911 .clr_int_reg_44_select (clr_int_reg_44_select),
2912 .clr_int_reg_44_select_out (default_grp_clr_int_reg_44_select),
2913 .clr_int_reg_45_select (clr_int_reg_45_select),
2914 .clr_int_reg_45_select_out (default_grp_clr_int_reg_45_select),
2915 .clr_int_reg_46_select (clr_int_reg_46_select),
2916 .clr_int_reg_46_select_out (default_grp_clr_int_reg_46_select),
2917 .clr_int_reg_47_select (clr_int_reg_47_select),
2918 .clr_int_reg_47_select_out (default_grp_clr_int_reg_47_select),
2919 .clr_int_reg_48_select (clr_int_reg_48_select),
2920 .clr_int_reg_48_select_out (default_grp_clr_int_reg_48_select),
2921 .clr_int_reg_49_select (clr_int_reg_49_select),
2922 .clr_int_reg_49_select_out (default_grp_clr_int_reg_49_select),
2923 .clr_int_reg_50_select (clr_int_reg_50_select),
2924 .clr_int_reg_50_select_out (default_grp_clr_int_reg_50_select),
2925 .clr_int_reg_51_select (clr_int_reg_51_select),
2926 .clr_int_reg_51_select_out (default_grp_clr_int_reg_51_select),
2927 .clr_int_reg_52_select (clr_int_reg_52_select),
2928 .clr_int_reg_52_select_out (default_grp_clr_int_reg_52_select),
2929 .clr_int_reg_53_select (clr_int_reg_53_select),
2930 .clr_int_reg_53_select_out (default_grp_clr_int_reg_53_select),
2931 .clr_int_reg_54_select (clr_int_reg_54_select),
2932 .clr_int_reg_54_select_out (default_grp_clr_int_reg_54_select),
2933 .clr_int_reg_55_select (clr_int_reg_55_select),
2934 .clr_int_reg_55_select_out (default_grp_clr_int_reg_55_select),
2935 .clr_int_reg_56_select (clr_int_reg_56_select),
2936 .clr_int_reg_56_select_out (default_grp_clr_int_reg_56_select),
2937 .clr_int_reg_57_select (clr_int_reg_57_select),
2938 .clr_int_reg_57_select_out (default_grp_clr_int_reg_57_select),
2939 .clr_int_reg_58_select (clr_int_reg_58_select),
2940 .clr_int_reg_58_select_out (default_grp_clr_int_reg_58_select),
2941 .clr_int_reg_59_select (clr_int_reg_59_select),
2942 .clr_int_reg_59_select_out (default_grp_clr_int_reg_59_select),
2943 .clr_int_reg_62_select (clr_int_reg_62_select),
2944 .clr_int_reg_62_select_out (default_grp_clr_int_reg_62_select),
2945 .clr_int_reg_63_select (clr_int_reg_63_select),
2946 .clr_int_reg_63_select_out (default_grp_clr_int_reg_63_select),
2947 .interrupt_retry_timer_select_pulse (interrupt_retry_timer_select_pulse),
2948 .interrupt_retry_timer_select_pulse_out (default_grp_interrupt_retry_timer_select_pulse),
2949 .interrupt_state_status_1_select (interrupt_state_status_1_select),
2950 .interrupt_state_status_1_select_out (default_grp_interrupt_state_status_1_select),
2951 .interrupt_state_status_2_select (interrupt_state_status_2_select),
2952 .interrupt_state_status_2_select_out (default_grp_interrupt_state_status_2_select),
2953 .daemon_csrbus_wr_in (daemon_csrbus_wr),
2954 .daemon_csrbus_wr_out (stage_mux_only_daemon_csrbus_wr),
2955 .daemon_csrbus_wr_data_in (daemon_csrbus_wr_data),
2956 .daemon_csrbus_wr_data_out (stage_mux_only_daemon_csrbus_wr_data),
2957 .read_data_0_out (stage_mux_only_read_data_0_out),
2958 .rst_l (rst_l),
2959 .rst_l_out (stage_mux_only_rst_l)
2960 );
2961
2962//----- OUTPUT: csrbus_read_data
2963assign csrbus_read_data = stage_mux_only_read_data_0_out;
2964
2965endmodule // dmu_imu_iss_csr
Full OpenSPARC design & verification tarball including full HDL.