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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: dmu_imu_iss_defines.h | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | `ifdef FIRE_DLC_IMU_ISS_DEFINES | |
39 | `else | |
40 | `define FIRE_DLC_IMU_ISS_DEFINES | |
41 | ||
42 | `define FIRE_DLC_IMU_ISS_INSTANCE_ID_VALUE_A 1'h0 | |
43 | `define FIRE_DLC_IMU_ISS_INSTANCE_ID_VALUE_B 1'h1 | |
44 | ||
45 | //------------------------------------------------------- | |
46 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_20 | |
47 | //------------------------------------------------------- | |
48 | ||
49 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_HW_ADDR 27'b000000011000000001000010100 | |
50 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_20_ADDR 30'b000000011000000001000010100000 | |
51 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_20_HW_ADDR 27'b000000011100000001000010100 | |
52 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_20_ADDR 30'b000000011100000001000010100000 | |
53 | ||
54 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_WIDTH 64 | |
55 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_DEPTH 1 | |
56 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_SLC 63:0 | |
57 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_SLC 63:0 | |
58 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_POSITION 0 | |
59 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_LOW_ADDR_WIDTH 0 | |
60 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_ADDR_RANGE 26:0 | |
61 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
62 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
63 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
64 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
65 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
66 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
67 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
68 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
69 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
70 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
71 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
72 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INTERNAL_REG 1 | |
73 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_ZERO_TIME_OMNI 1 | |
74 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_NUM_FIELDS 4 | |
75 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_MDO_MODE_FID 0 | |
76 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_MDO_MODE_SLC 63:63 | |
77 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_MDO_MODE_WIDTH 1 | |
78 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_MDO_MODE_INT_SLC 0:0 | |
79 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_MDO_MODE_POSITION 63 | |
80 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
81 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
82 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_MDO_MODE_POR_VALUE 1'b0 | |
83 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_V_FID 1 | |
84 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_V_SLC 31:31 | |
85 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_V_WIDTH 1 | |
86 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_V_INT_SLC 0:0 | |
87 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_V_POSITION 31 | |
88 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
89 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
90 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_V_POR_VALUE 1'b0 | |
91 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_FID 2 | |
92 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_SLC 30:25 | |
93 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_WIDTH 6 | |
94 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_INT_SLC 5:0 | |
95 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_POSITION 25 | |
96 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
97 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
98 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_T_ID_POR_VALUE 6'b000000 | |
99 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_FID 3 | |
100 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_SLC 9:6 | |
101 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_WIDTH 4 | |
102 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_INT_SLC 3:0 | |
103 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_POSITION 6 | |
104 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
105 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
106 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_20_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
107 | ||
108 | //------------------------------------------------------- | |
109 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_21 | |
110 | //------------------------------------------------------- | |
111 | ||
112 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_HW_ADDR 27'b000000011000000001000010101 | |
113 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_21_ADDR 30'b000000011000000001000010101000 | |
114 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_21_HW_ADDR 27'b000000011100000001000010101 | |
115 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_21_ADDR 30'b000000011100000001000010101000 | |
116 | ||
117 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_WIDTH 64 | |
118 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_DEPTH 1 | |
119 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_SLC 63:0 | |
120 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_SLC 63:0 | |
121 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_POSITION 0 | |
122 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_LOW_ADDR_WIDTH 0 | |
123 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_ADDR_RANGE 26:0 | |
124 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
125 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
126 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
127 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
128 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
129 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
130 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
131 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
132 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
133 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
134 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
135 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INTERNAL_REG 1 | |
136 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_ZERO_TIME_OMNI 1 | |
137 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_NUM_FIELDS 4 | |
138 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_MDO_MODE_FID 0 | |
139 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_MDO_MODE_SLC 63:63 | |
140 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_MDO_MODE_WIDTH 1 | |
141 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_MDO_MODE_INT_SLC 0:0 | |
142 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_MDO_MODE_POSITION 63 | |
143 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
144 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
145 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_MDO_MODE_POR_VALUE 1'b0 | |
146 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_V_FID 1 | |
147 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_V_SLC 31:31 | |
148 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_V_WIDTH 1 | |
149 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_V_INT_SLC 0:0 | |
150 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_V_POSITION 31 | |
151 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
152 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
153 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_V_POR_VALUE 1'b0 | |
154 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_FID 2 | |
155 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_SLC 30:25 | |
156 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_WIDTH 6 | |
157 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_INT_SLC 5:0 | |
158 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_POSITION 25 | |
159 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
160 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
161 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_T_ID_POR_VALUE 6'b000000 | |
162 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_FID 3 | |
163 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_SLC 9:6 | |
164 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_WIDTH 4 | |
165 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_INT_SLC 3:0 | |
166 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_POSITION 6 | |
167 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
168 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
169 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_21_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
170 | ||
171 | //------------------------------------------------------- | |
172 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_22 | |
173 | //------------------------------------------------------- | |
174 | ||
175 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_HW_ADDR 27'b000000011000000001000010110 | |
176 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_22_ADDR 30'b000000011000000001000010110000 | |
177 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_22_HW_ADDR 27'b000000011100000001000010110 | |
178 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_22_ADDR 30'b000000011100000001000010110000 | |
179 | ||
180 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_WIDTH 64 | |
181 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_DEPTH 1 | |
182 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_SLC 63:0 | |
183 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_SLC 63:0 | |
184 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_POSITION 0 | |
185 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_LOW_ADDR_WIDTH 0 | |
186 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_ADDR_RANGE 26:0 | |
187 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
188 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
189 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
190 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
191 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
192 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
193 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
194 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
195 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
196 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
197 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
198 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INTERNAL_REG 1 | |
199 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_ZERO_TIME_OMNI 1 | |
200 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_NUM_FIELDS 4 | |
201 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_MDO_MODE_FID 0 | |
202 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_MDO_MODE_SLC 63:63 | |
203 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_MDO_MODE_WIDTH 1 | |
204 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_MDO_MODE_INT_SLC 0:0 | |
205 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_MDO_MODE_POSITION 63 | |
206 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
207 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
208 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_MDO_MODE_POR_VALUE 1'b0 | |
209 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_V_FID 1 | |
210 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_V_SLC 31:31 | |
211 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_V_WIDTH 1 | |
212 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_V_INT_SLC 0:0 | |
213 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_V_POSITION 31 | |
214 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
215 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
216 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_V_POR_VALUE 1'b0 | |
217 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_FID 2 | |
218 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_SLC 30:25 | |
219 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_WIDTH 6 | |
220 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_INT_SLC 5:0 | |
221 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_POSITION 25 | |
222 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
223 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
224 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_T_ID_POR_VALUE 6'b000000 | |
225 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_FID 3 | |
226 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_SLC 9:6 | |
227 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_WIDTH 4 | |
228 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_INT_SLC 3:0 | |
229 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_POSITION 6 | |
230 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
231 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
232 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_22_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
233 | ||
234 | //------------------------------------------------------- | |
235 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_23 | |
236 | //------------------------------------------------------- | |
237 | ||
238 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_HW_ADDR 27'b000000011000000001000010111 | |
239 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_23_ADDR 30'b000000011000000001000010111000 | |
240 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_23_HW_ADDR 27'b000000011100000001000010111 | |
241 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_23_ADDR 30'b000000011100000001000010111000 | |
242 | ||
243 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_WIDTH 64 | |
244 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_DEPTH 1 | |
245 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_SLC 63:0 | |
246 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_SLC 63:0 | |
247 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_POSITION 0 | |
248 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_LOW_ADDR_WIDTH 0 | |
249 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_ADDR_RANGE 26:0 | |
250 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
251 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
252 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
253 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
254 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
255 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
256 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
257 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
258 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
259 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
260 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
261 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INTERNAL_REG 1 | |
262 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_ZERO_TIME_OMNI 1 | |
263 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_NUM_FIELDS 4 | |
264 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_MDO_MODE_FID 0 | |
265 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_MDO_MODE_SLC 63:63 | |
266 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_MDO_MODE_WIDTH 1 | |
267 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_MDO_MODE_INT_SLC 0:0 | |
268 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_MDO_MODE_POSITION 63 | |
269 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
270 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
271 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_MDO_MODE_POR_VALUE 1'b0 | |
272 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_V_FID 1 | |
273 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_V_SLC 31:31 | |
274 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_V_WIDTH 1 | |
275 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_V_INT_SLC 0:0 | |
276 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_V_POSITION 31 | |
277 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
278 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
279 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_V_POR_VALUE 1'b0 | |
280 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_FID 2 | |
281 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_SLC 30:25 | |
282 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_WIDTH 6 | |
283 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_INT_SLC 5:0 | |
284 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_POSITION 25 | |
285 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
286 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
287 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_T_ID_POR_VALUE 6'b000000 | |
288 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_FID 3 | |
289 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_SLC 9:6 | |
290 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_WIDTH 4 | |
291 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_INT_SLC 3:0 | |
292 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_POSITION 6 | |
293 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
294 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
295 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_23_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
296 | ||
297 | //------------------------------------------------------- | |
298 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_24 | |
299 | //------------------------------------------------------- | |
300 | ||
301 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_HW_ADDR 27'b000000011000000001000011000 | |
302 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_24_ADDR 30'b000000011000000001000011000000 | |
303 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_24_HW_ADDR 27'b000000011100000001000011000 | |
304 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_24_ADDR 30'b000000011100000001000011000000 | |
305 | ||
306 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_WIDTH 64 | |
307 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_DEPTH 1 | |
308 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_SLC 63:0 | |
309 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_SLC 63:0 | |
310 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_POSITION 0 | |
311 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_LOW_ADDR_WIDTH 0 | |
312 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_ADDR_RANGE 26:0 | |
313 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
314 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
315 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
316 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
317 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
318 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
319 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
320 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
321 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
322 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
323 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
324 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INTERNAL_REG 1 | |
325 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_ZERO_TIME_OMNI 1 | |
326 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_NUM_FIELDS 4 | |
327 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_MDO_MODE_FID 0 | |
328 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_MDO_MODE_SLC 63:63 | |
329 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_MDO_MODE_WIDTH 1 | |
330 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_MDO_MODE_INT_SLC 0:0 | |
331 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_MDO_MODE_POSITION 63 | |
332 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
333 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
334 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_MDO_MODE_POR_VALUE 1'b0 | |
335 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_V_FID 1 | |
336 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_V_SLC 31:31 | |
337 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_V_WIDTH 1 | |
338 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_V_INT_SLC 0:0 | |
339 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_V_POSITION 31 | |
340 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
341 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
342 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_V_POR_VALUE 1'b0 | |
343 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_FID 2 | |
344 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_SLC 30:25 | |
345 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_WIDTH 6 | |
346 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_INT_SLC 5:0 | |
347 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_POSITION 25 | |
348 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
349 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
350 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_T_ID_POR_VALUE 6'b000000 | |
351 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_FID 3 | |
352 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_SLC 9:6 | |
353 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_WIDTH 4 | |
354 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_INT_SLC 3:0 | |
355 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_POSITION 6 | |
356 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
357 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
358 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_24_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
359 | ||
360 | //------------------------------------------------------- | |
361 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_25 | |
362 | //------------------------------------------------------- | |
363 | ||
364 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_HW_ADDR 27'b000000011000000001000011001 | |
365 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_25_ADDR 30'b000000011000000001000011001000 | |
366 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_25_HW_ADDR 27'b000000011100000001000011001 | |
367 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_25_ADDR 30'b000000011100000001000011001000 | |
368 | ||
369 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_WIDTH 64 | |
370 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_DEPTH 1 | |
371 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_SLC 63:0 | |
372 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_SLC 63:0 | |
373 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_POSITION 0 | |
374 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_LOW_ADDR_WIDTH 0 | |
375 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_ADDR_RANGE 26:0 | |
376 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
377 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
378 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
379 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
380 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
381 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
382 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
383 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
384 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
385 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
386 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
387 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INTERNAL_REG 1 | |
388 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_ZERO_TIME_OMNI 1 | |
389 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_NUM_FIELDS 4 | |
390 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_MDO_MODE_FID 0 | |
391 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_MDO_MODE_SLC 63:63 | |
392 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_MDO_MODE_WIDTH 1 | |
393 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_MDO_MODE_INT_SLC 0:0 | |
394 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_MDO_MODE_POSITION 63 | |
395 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
396 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
397 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_MDO_MODE_POR_VALUE 1'b0 | |
398 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_V_FID 1 | |
399 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_V_SLC 31:31 | |
400 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_V_WIDTH 1 | |
401 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_V_INT_SLC 0:0 | |
402 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_V_POSITION 31 | |
403 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
404 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
405 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_V_POR_VALUE 1'b0 | |
406 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_FID 2 | |
407 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_SLC 30:25 | |
408 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_WIDTH 6 | |
409 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_INT_SLC 5:0 | |
410 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_POSITION 25 | |
411 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
412 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
413 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_T_ID_POR_VALUE 6'b000000 | |
414 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_FID 3 | |
415 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_SLC 9:6 | |
416 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_WIDTH 4 | |
417 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_INT_SLC 3:0 | |
418 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_POSITION 6 | |
419 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
420 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
421 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_25_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
422 | ||
423 | //------------------------------------------------------- | |
424 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_26 | |
425 | //------------------------------------------------------- | |
426 | ||
427 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_HW_ADDR 27'b000000011000000001000011010 | |
428 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_26_ADDR 30'b000000011000000001000011010000 | |
429 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_26_HW_ADDR 27'b000000011100000001000011010 | |
430 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_26_ADDR 30'b000000011100000001000011010000 | |
431 | ||
432 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_WIDTH 64 | |
433 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_DEPTH 1 | |
434 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_SLC 63:0 | |
435 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_SLC 63:0 | |
436 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_POSITION 0 | |
437 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_LOW_ADDR_WIDTH 0 | |
438 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_ADDR_RANGE 26:0 | |
439 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
440 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
441 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
442 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
443 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
444 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
445 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
446 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
447 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
448 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
449 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
450 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INTERNAL_REG 1 | |
451 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_ZERO_TIME_OMNI 1 | |
452 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_NUM_FIELDS 4 | |
453 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_MDO_MODE_FID 0 | |
454 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_MDO_MODE_SLC 63:63 | |
455 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_MDO_MODE_WIDTH 1 | |
456 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_MDO_MODE_INT_SLC 0:0 | |
457 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_MDO_MODE_POSITION 63 | |
458 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
459 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
460 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_MDO_MODE_POR_VALUE 1'b0 | |
461 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_V_FID 1 | |
462 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_V_SLC 31:31 | |
463 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_V_WIDTH 1 | |
464 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_V_INT_SLC 0:0 | |
465 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_V_POSITION 31 | |
466 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
467 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
468 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_V_POR_VALUE 1'b0 | |
469 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_FID 2 | |
470 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_SLC 30:25 | |
471 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_WIDTH 6 | |
472 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_INT_SLC 5:0 | |
473 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_POSITION 25 | |
474 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
475 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
476 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_T_ID_POR_VALUE 6'b000000 | |
477 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_FID 3 | |
478 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_SLC 9:6 | |
479 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_WIDTH 4 | |
480 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_INT_SLC 3:0 | |
481 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_POSITION 6 | |
482 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
483 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
484 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_26_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
485 | ||
486 | //------------------------------------------------------- | |
487 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_27 | |
488 | //------------------------------------------------------- | |
489 | ||
490 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_HW_ADDR 27'b000000011000000001000011011 | |
491 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_27_ADDR 30'b000000011000000001000011011000 | |
492 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_27_HW_ADDR 27'b000000011100000001000011011 | |
493 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_27_ADDR 30'b000000011100000001000011011000 | |
494 | ||
495 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_WIDTH 64 | |
496 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_DEPTH 1 | |
497 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_SLC 63:0 | |
498 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_SLC 63:0 | |
499 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_POSITION 0 | |
500 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_LOW_ADDR_WIDTH 0 | |
501 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_ADDR_RANGE 26:0 | |
502 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
503 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
504 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
505 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
506 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
507 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
508 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
509 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
510 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
511 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
512 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
513 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INTERNAL_REG 1 | |
514 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_ZERO_TIME_OMNI 1 | |
515 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_NUM_FIELDS 4 | |
516 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_MDO_MODE_FID 0 | |
517 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_MDO_MODE_SLC 63:63 | |
518 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_MDO_MODE_WIDTH 1 | |
519 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_MDO_MODE_INT_SLC 0:0 | |
520 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_MDO_MODE_POSITION 63 | |
521 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
522 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
523 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_MDO_MODE_POR_VALUE 1'b0 | |
524 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_V_FID 1 | |
525 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_V_SLC 31:31 | |
526 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_V_WIDTH 1 | |
527 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_V_INT_SLC 0:0 | |
528 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_V_POSITION 31 | |
529 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
530 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
531 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_V_POR_VALUE 1'b0 | |
532 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_FID 2 | |
533 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_SLC 30:25 | |
534 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_WIDTH 6 | |
535 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_INT_SLC 5:0 | |
536 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_POSITION 25 | |
537 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
538 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
539 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_T_ID_POR_VALUE 6'b000000 | |
540 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_FID 3 | |
541 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_SLC 9:6 | |
542 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_WIDTH 4 | |
543 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_INT_SLC 3:0 | |
544 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_POSITION 6 | |
545 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
546 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
547 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_27_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
548 | ||
549 | //------------------------------------------------------- | |
550 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_28 | |
551 | //------------------------------------------------------- | |
552 | ||
553 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_HW_ADDR 27'b000000011000000001000011100 | |
554 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_28_ADDR 30'b000000011000000001000011100000 | |
555 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_28_HW_ADDR 27'b000000011100000001000011100 | |
556 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_28_ADDR 30'b000000011100000001000011100000 | |
557 | ||
558 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_WIDTH 64 | |
559 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_DEPTH 1 | |
560 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_SLC 63:0 | |
561 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_SLC 63:0 | |
562 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_POSITION 0 | |
563 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_LOW_ADDR_WIDTH 0 | |
564 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_ADDR_RANGE 26:0 | |
565 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
566 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
567 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
568 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
569 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
570 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
571 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
572 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
573 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
574 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
575 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
576 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INTERNAL_REG 1 | |
577 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_ZERO_TIME_OMNI 1 | |
578 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_NUM_FIELDS 4 | |
579 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_MDO_MODE_FID 0 | |
580 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_MDO_MODE_SLC 63:63 | |
581 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_MDO_MODE_WIDTH 1 | |
582 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_MDO_MODE_INT_SLC 0:0 | |
583 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_MDO_MODE_POSITION 63 | |
584 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
585 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
586 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_MDO_MODE_POR_VALUE 1'b0 | |
587 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_V_FID 1 | |
588 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_V_SLC 31:31 | |
589 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_V_WIDTH 1 | |
590 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_V_INT_SLC 0:0 | |
591 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_V_POSITION 31 | |
592 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
593 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
594 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_V_POR_VALUE 1'b0 | |
595 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_FID 2 | |
596 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_SLC 30:25 | |
597 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_WIDTH 6 | |
598 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_INT_SLC 5:0 | |
599 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_POSITION 25 | |
600 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
601 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
602 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_T_ID_POR_VALUE 6'b000000 | |
603 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_FID 3 | |
604 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_SLC 9:6 | |
605 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_WIDTH 4 | |
606 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_INT_SLC 3:0 | |
607 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_POSITION 6 | |
608 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
609 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
610 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_28_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
611 | ||
612 | //------------------------------------------------------- | |
613 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_29 | |
614 | //------------------------------------------------------- | |
615 | ||
616 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_HW_ADDR 27'b000000011000000001000011101 | |
617 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_29_ADDR 30'b000000011000000001000011101000 | |
618 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_29_HW_ADDR 27'b000000011100000001000011101 | |
619 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_29_ADDR 30'b000000011100000001000011101000 | |
620 | ||
621 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_WIDTH 64 | |
622 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_DEPTH 1 | |
623 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_SLC 63:0 | |
624 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_SLC 63:0 | |
625 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_POSITION 0 | |
626 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_LOW_ADDR_WIDTH 0 | |
627 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_ADDR_RANGE 26:0 | |
628 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
629 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
630 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
631 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
632 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
633 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
634 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
635 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
636 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
637 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
638 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
639 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INTERNAL_REG 1 | |
640 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_ZERO_TIME_OMNI 1 | |
641 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_NUM_FIELDS 4 | |
642 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_MDO_MODE_FID 0 | |
643 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_MDO_MODE_SLC 63:63 | |
644 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_MDO_MODE_WIDTH 1 | |
645 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_MDO_MODE_INT_SLC 0:0 | |
646 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_MDO_MODE_POSITION 63 | |
647 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
648 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
649 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_MDO_MODE_POR_VALUE 1'b0 | |
650 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_V_FID 1 | |
651 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_V_SLC 31:31 | |
652 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_V_WIDTH 1 | |
653 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_V_INT_SLC 0:0 | |
654 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_V_POSITION 31 | |
655 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
656 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
657 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_V_POR_VALUE 1'b0 | |
658 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_FID 2 | |
659 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_SLC 30:25 | |
660 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_WIDTH 6 | |
661 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_INT_SLC 5:0 | |
662 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_POSITION 25 | |
663 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
664 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
665 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_T_ID_POR_VALUE 6'b000000 | |
666 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_FID 3 | |
667 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_SLC 9:6 | |
668 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_WIDTH 4 | |
669 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_INT_SLC 3:0 | |
670 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_POSITION 6 | |
671 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
672 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
673 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_29_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
674 | ||
675 | //------------------------------------------------------- | |
676 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_30 | |
677 | //------------------------------------------------------- | |
678 | ||
679 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_HW_ADDR 27'b000000011000000001000011110 | |
680 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_30_ADDR 30'b000000011000000001000011110000 | |
681 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_30_HW_ADDR 27'b000000011100000001000011110 | |
682 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_30_ADDR 30'b000000011100000001000011110000 | |
683 | ||
684 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_WIDTH 64 | |
685 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_DEPTH 1 | |
686 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_SLC 63:0 | |
687 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_SLC 63:0 | |
688 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_POSITION 0 | |
689 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_LOW_ADDR_WIDTH 0 | |
690 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_ADDR_RANGE 26:0 | |
691 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
692 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
693 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
694 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
695 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
696 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
697 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
698 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
699 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
700 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
701 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
702 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INTERNAL_REG 1 | |
703 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_ZERO_TIME_OMNI 1 | |
704 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_NUM_FIELDS 4 | |
705 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_MDO_MODE_FID 0 | |
706 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_MDO_MODE_SLC 63:63 | |
707 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_MDO_MODE_WIDTH 1 | |
708 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_MDO_MODE_INT_SLC 0:0 | |
709 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_MDO_MODE_POSITION 63 | |
710 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
711 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
712 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_MDO_MODE_POR_VALUE 1'b0 | |
713 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_V_FID 1 | |
714 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_V_SLC 31:31 | |
715 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_V_WIDTH 1 | |
716 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_V_INT_SLC 0:0 | |
717 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_V_POSITION 31 | |
718 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
719 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
720 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_V_POR_VALUE 1'b0 | |
721 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_FID 2 | |
722 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_SLC 30:25 | |
723 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_WIDTH 6 | |
724 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_INT_SLC 5:0 | |
725 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_POSITION 25 | |
726 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
727 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
728 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_T_ID_POR_VALUE 6'b000000 | |
729 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_FID 3 | |
730 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_SLC 9:6 | |
731 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_WIDTH 4 | |
732 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_INT_SLC 3:0 | |
733 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_POSITION 6 | |
734 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
735 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
736 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_30_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
737 | ||
738 | //------------------------------------------------------- | |
739 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_31 | |
740 | //------------------------------------------------------- | |
741 | ||
742 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_HW_ADDR 27'b000000011000000001000011111 | |
743 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_31_ADDR 30'b000000011000000001000011111000 | |
744 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_31_HW_ADDR 27'b000000011100000001000011111 | |
745 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_31_ADDR 30'b000000011100000001000011111000 | |
746 | ||
747 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_WIDTH 64 | |
748 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_DEPTH 1 | |
749 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_SLC 63:0 | |
750 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_SLC 63:0 | |
751 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_POSITION 0 | |
752 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_LOW_ADDR_WIDTH 0 | |
753 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_ADDR_RANGE 26:0 | |
754 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
755 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
756 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
757 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
758 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
759 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
760 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
761 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
762 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
763 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
764 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
765 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INTERNAL_REG 1 | |
766 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_ZERO_TIME_OMNI 1 | |
767 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_NUM_FIELDS 4 | |
768 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_MDO_MODE_FID 0 | |
769 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_MDO_MODE_SLC 63:63 | |
770 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_MDO_MODE_WIDTH 1 | |
771 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_MDO_MODE_INT_SLC 0:0 | |
772 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_MDO_MODE_POSITION 63 | |
773 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
774 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
775 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_MDO_MODE_POR_VALUE 1'b0 | |
776 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_V_FID 1 | |
777 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_V_SLC 31:31 | |
778 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_V_WIDTH 1 | |
779 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_V_INT_SLC 0:0 | |
780 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_V_POSITION 31 | |
781 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
782 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
783 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_V_POR_VALUE 1'b0 | |
784 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_FID 2 | |
785 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_SLC 30:25 | |
786 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_WIDTH 6 | |
787 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_INT_SLC 5:0 | |
788 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_POSITION 25 | |
789 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
790 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
791 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_T_ID_POR_VALUE 6'b000000 | |
792 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_FID 3 | |
793 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_SLC 9:6 | |
794 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_WIDTH 4 | |
795 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_INT_SLC 3:0 | |
796 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_POSITION 6 | |
797 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
798 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
799 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_31_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
800 | ||
801 | //------------------------------------------------------- | |
802 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_32 | |
803 | //------------------------------------------------------- | |
804 | ||
805 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_HW_ADDR 27'b000000011000000001000100000 | |
806 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_32_ADDR 30'b000000011000000001000100000000 | |
807 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_32_HW_ADDR 27'b000000011100000001000100000 | |
808 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_32_ADDR 30'b000000011100000001000100000000 | |
809 | ||
810 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_WIDTH 64 | |
811 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_DEPTH 1 | |
812 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_SLC 63:0 | |
813 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_SLC 63:0 | |
814 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_POSITION 0 | |
815 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_LOW_ADDR_WIDTH 0 | |
816 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_ADDR_RANGE 26:0 | |
817 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
818 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
819 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
820 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
821 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
822 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
823 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
824 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
825 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
826 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
827 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
828 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INTERNAL_REG 1 | |
829 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_ZERO_TIME_OMNI 1 | |
830 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_NUM_FIELDS 4 | |
831 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_MDO_MODE_FID 0 | |
832 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_MDO_MODE_SLC 63:63 | |
833 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_MDO_MODE_WIDTH 1 | |
834 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_MDO_MODE_INT_SLC 0:0 | |
835 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_MDO_MODE_POSITION 63 | |
836 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
837 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
838 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_MDO_MODE_POR_VALUE 1'b0 | |
839 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_V_FID 1 | |
840 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_V_SLC 31:31 | |
841 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_V_WIDTH 1 | |
842 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_V_INT_SLC 0:0 | |
843 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_V_POSITION 31 | |
844 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
845 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
846 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_V_POR_VALUE 1'b0 | |
847 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_FID 2 | |
848 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_SLC 30:25 | |
849 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_WIDTH 6 | |
850 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_INT_SLC 5:0 | |
851 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_POSITION 25 | |
852 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
853 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
854 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_T_ID_POR_VALUE 6'b000000 | |
855 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_FID 3 | |
856 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_SLC 9:6 | |
857 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_WIDTH 4 | |
858 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_INT_SLC 3:0 | |
859 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_POSITION 6 | |
860 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
861 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
862 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_32_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
863 | ||
864 | //------------------------------------------------------- | |
865 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_33 | |
866 | //------------------------------------------------------- | |
867 | ||
868 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_HW_ADDR 27'b000000011000000001000100001 | |
869 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_33_ADDR 30'b000000011000000001000100001000 | |
870 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_33_HW_ADDR 27'b000000011100000001000100001 | |
871 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_33_ADDR 30'b000000011100000001000100001000 | |
872 | ||
873 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_WIDTH 64 | |
874 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_DEPTH 1 | |
875 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_SLC 63:0 | |
876 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_SLC 63:0 | |
877 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_POSITION 0 | |
878 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_LOW_ADDR_WIDTH 0 | |
879 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_ADDR_RANGE 26:0 | |
880 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
881 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
882 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
883 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
884 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
885 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
886 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
887 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
888 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
889 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
890 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
891 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INTERNAL_REG 1 | |
892 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_ZERO_TIME_OMNI 1 | |
893 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_NUM_FIELDS 4 | |
894 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_MDO_MODE_FID 0 | |
895 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_MDO_MODE_SLC 63:63 | |
896 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_MDO_MODE_WIDTH 1 | |
897 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_MDO_MODE_INT_SLC 0:0 | |
898 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_MDO_MODE_POSITION 63 | |
899 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
900 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
901 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_MDO_MODE_POR_VALUE 1'b0 | |
902 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_V_FID 1 | |
903 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_V_SLC 31:31 | |
904 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_V_WIDTH 1 | |
905 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_V_INT_SLC 0:0 | |
906 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_V_POSITION 31 | |
907 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
908 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
909 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_V_POR_VALUE 1'b0 | |
910 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_FID 2 | |
911 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_SLC 30:25 | |
912 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_WIDTH 6 | |
913 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_INT_SLC 5:0 | |
914 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_POSITION 25 | |
915 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
916 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
917 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_T_ID_POR_VALUE 6'b000000 | |
918 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_FID 3 | |
919 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_SLC 9:6 | |
920 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_WIDTH 4 | |
921 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_INT_SLC 3:0 | |
922 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_POSITION 6 | |
923 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
924 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
925 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_33_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
926 | ||
927 | //------------------------------------------------------- | |
928 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_34 | |
929 | //------------------------------------------------------- | |
930 | ||
931 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_HW_ADDR 27'b000000011000000001000100010 | |
932 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_34_ADDR 30'b000000011000000001000100010000 | |
933 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_34_HW_ADDR 27'b000000011100000001000100010 | |
934 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_34_ADDR 30'b000000011100000001000100010000 | |
935 | ||
936 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_WIDTH 64 | |
937 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_DEPTH 1 | |
938 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_SLC 63:0 | |
939 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_SLC 63:0 | |
940 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_POSITION 0 | |
941 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_LOW_ADDR_WIDTH 0 | |
942 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_ADDR_RANGE 26:0 | |
943 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
944 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
945 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
946 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
947 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
948 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
949 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
950 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
951 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
952 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
953 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
954 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INTERNAL_REG 1 | |
955 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_ZERO_TIME_OMNI 1 | |
956 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_NUM_FIELDS 4 | |
957 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_MDO_MODE_FID 0 | |
958 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_MDO_MODE_SLC 63:63 | |
959 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_MDO_MODE_WIDTH 1 | |
960 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_MDO_MODE_INT_SLC 0:0 | |
961 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_MDO_MODE_POSITION 63 | |
962 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
963 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
964 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_MDO_MODE_POR_VALUE 1'b0 | |
965 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_V_FID 1 | |
966 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_V_SLC 31:31 | |
967 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_V_WIDTH 1 | |
968 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_V_INT_SLC 0:0 | |
969 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_V_POSITION 31 | |
970 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
971 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
972 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_V_POR_VALUE 1'b0 | |
973 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_FID 2 | |
974 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_SLC 30:25 | |
975 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_WIDTH 6 | |
976 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_INT_SLC 5:0 | |
977 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_POSITION 25 | |
978 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
979 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
980 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_T_ID_POR_VALUE 6'b000000 | |
981 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_FID 3 | |
982 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_SLC 9:6 | |
983 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_WIDTH 4 | |
984 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_INT_SLC 3:0 | |
985 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_POSITION 6 | |
986 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
987 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
988 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_34_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
989 | ||
990 | //------------------------------------------------------- | |
991 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_35 | |
992 | //------------------------------------------------------- | |
993 | ||
994 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_HW_ADDR 27'b000000011000000001000100011 | |
995 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_35_ADDR 30'b000000011000000001000100011000 | |
996 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_35_HW_ADDR 27'b000000011100000001000100011 | |
997 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_35_ADDR 30'b000000011100000001000100011000 | |
998 | ||
999 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_WIDTH 64 | |
1000 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_DEPTH 1 | |
1001 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_SLC 63:0 | |
1002 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_SLC 63:0 | |
1003 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_POSITION 0 | |
1004 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_LOW_ADDR_WIDTH 0 | |
1005 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_ADDR_RANGE 26:0 | |
1006 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1007 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1008 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1009 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1010 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1011 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1012 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1013 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1014 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1015 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1016 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1017 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INTERNAL_REG 1 | |
1018 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_ZERO_TIME_OMNI 1 | |
1019 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_NUM_FIELDS 4 | |
1020 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_MDO_MODE_FID 0 | |
1021 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_MDO_MODE_SLC 63:63 | |
1022 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_MDO_MODE_WIDTH 1 | |
1023 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_MDO_MODE_INT_SLC 0:0 | |
1024 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_MDO_MODE_POSITION 63 | |
1025 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1026 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1027 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_MDO_MODE_POR_VALUE 1'b0 | |
1028 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_V_FID 1 | |
1029 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_V_SLC 31:31 | |
1030 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_V_WIDTH 1 | |
1031 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_V_INT_SLC 0:0 | |
1032 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_V_POSITION 31 | |
1033 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1034 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1035 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_V_POR_VALUE 1'b0 | |
1036 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_FID 2 | |
1037 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_SLC 30:25 | |
1038 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_WIDTH 6 | |
1039 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_INT_SLC 5:0 | |
1040 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_POSITION 25 | |
1041 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1042 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1043 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_T_ID_POR_VALUE 6'b000000 | |
1044 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_FID 3 | |
1045 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_SLC 9:6 | |
1046 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_WIDTH 4 | |
1047 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_INT_SLC 3:0 | |
1048 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_POSITION 6 | |
1049 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1050 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1051 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_35_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1052 | ||
1053 | //------------------------------------------------------- | |
1054 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_36 | |
1055 | //------------------------------------------------------- | |
1056 | ||
1057 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_HW_ADDR 27'b000000011000000001000100100 | |
1058 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_36_ADDR 30'b000000011000000001000100100000 | |
1059 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_36_HW_ADDR 27'b000000011100000001000100100 | |
1060 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_36_ADDR 30'b000000011100000001000100100000 | |
1061 | ||
1062 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_WIDTH 64 | |
1063 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_DEPTH 1 | |
1064 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_SLC 63:0 | |
1065 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_SLC 63:0 | |
1066 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_POSITION 0 | |
1067 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_LOW_ADDR_WIDTH 0 | |
1068 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_ADDR_RANGE 26:0 | |
1069 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1070 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1071 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1072 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1073 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1074 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1075 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1076 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1077 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1078 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1079 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1080 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INTERNAL_REG 1 | |
1081 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_ZERO_TIME_OMNI 1 | |
1082 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_NUM_FIELDS 4 | |
1083 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_MDO_MODE_FID 0 | |
1084 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_MDO_MODE_SLC 63:63 | |
1085 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_MDO_MODE_WIDTH 1 | |
1086 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_MDO_MODE_INT_SLC 0:0 | |
1087 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_MDO_MODE_POSITION 63 | |
1088 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1089 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1090 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_MDO_MODE_POR_VALUE 1'b0 | |
1091 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_V_FID 1 | |
1092 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_V_SLC 31:31 | |
1093 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_V_WIDTH 1 | |
1094 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_V_INT_SLC 0:0 | |
1095 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_V_POSITION 31 | |
1096 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1097 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1098 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_V_POR_VALUE 1'b0 | |
1099 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_FID 2 | |
1100 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_SLC 30:25 | |
1101 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_WIDTH 6 | |
1102 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_INT_SLC 5:0 | |
1103 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_POSITION 25 | |
1104 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1105 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1106 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_T_ID_POR_VALUE 6'b000000 | |
1107 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_FID 3 | |
1108 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_SLC 9:6 | |
1109 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_WIDTH 4 | |
1110 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_INT_SLC 3:0 | |
1111 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_POSITION 6 | |
1112 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1113 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1114 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_36_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1115 | ||
1116 | //------------------------------------------------------- | |
1117 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_37 | |
1118 | //------------------------------------------------------- | |
1119 | ||
1120 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_HW_ADDR 27'b000000011000000001000100101 | |
1121 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_37_ADDR 30'b000000011000000001000100101000 | |
1122 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_37_HW_ADDR 27'b000000011100000001000100101 | |
1123 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_37_ADDR 30'b000000011100000001000100101000 | |
1124 | ||
1125 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_WIDTH 64 | |
1126 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_DEPTH 1 | |
1127 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_SLC 63:0 | |
1128 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_SLC 63:0 | |
1129 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_POSITION 0 | |
1130 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_LOW_ADDR_WIDTH 0 | |
1131 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_ADDR_RANGE 26:0 | |
1132 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1133 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1134 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1135 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1136 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1137 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1138 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1139 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1140 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1141 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1142 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1143 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INTERNAL_REG 1 | |
1144 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_ZERO_TIME_OMNI 1 | |
1145 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_NUM_FIELDS 4 | |
1146 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_MDO_MODE_FID 0 | |
1147 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_MDO_MODE_SLC 63:63 | |
1148 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_MDO_MODE_WIDTH 1 | |
1149 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_MDO_MODE_INT_SLC 0:0 | |
1150 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_MDO_MODE_POSITION 63 | |
1151 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1152 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1153 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_MDO_MODE_POR_VALUE 1'b0 | |
1154 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_V_FID 1 | |
1155 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_V_SLC 31:31 | |
1156 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_V_WIDTH 1 | |
1157 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_V_INT_SLC 0:0 | |
1158 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_V_POSITION 31 | |
1159 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1160 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1161 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_V_POR_VALUE 1'b0 | |
1162 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_FID 2 | |
1163 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_SLC 30:25 | |
1164 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_WIDTH 6 | |
1165 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_INT_SLC 5:0 | |
1166 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_POSITION 25 | |
1167 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1168 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1169 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_T_ID_POR_VALUE 6'b000000 | |
1170 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_FID 3 | |
1171 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_SLC 9:6 | |
1172 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_WIDTH 4 | |
1173 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_INT_SLC 3:0 | |
1174 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_POSITION 6 | |
1175 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1176 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1177 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_37_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1178 | ||
1179 | //------------------------------------------------------- | |
1180 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_38 | |
1181 | //------------------------------------------------------- | |
1182 | ||
1183 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_HW_ADDR 27'b000000011000000001000100110 | |
1184 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_38_ADDR 30'b000000011000000001000100110000 | |
1185 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_38_HW_ADDR 27'b000000011100000001000100110 | |
1186 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_38_ADDR 30'b000000011100000001000100110000 | |
1187 | ||
1188 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_WIDTH 64 | |
1189 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_DEPTH 1 | |
1190 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_SLC 63:0 | |
1191 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_SLC 63:0 | |
1192 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_POSITION 0 | |
1193 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_LOW_ADDR_WIDTH 0 | |
1194 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_ADDR_RANGE 26:0 | |
1195 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1196 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1197 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1198 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1199 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1200 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1201 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1202 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1203 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1204 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1205 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1206 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INTERNAL_REG 1 | |
1207 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_ZERO_TIME_OMNI 1 | |
1208 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_NUM_FIELDS 4 | |
1209 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_MDO_MODE_FID 0 | |
1210 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_MDO_MODE_SLC 63:63 | |
1211 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_MDO_MODE_WIDTH 1 | |
1212 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_MDO_MODE_INT_SLC 0:0 | |
1213 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_MDO_MODE_POSITION 63 | |
1214 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1215 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1216 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_MDO_MODE_POR_VALUE 1'b0 | |
1217 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_V_FID 1 | |
1218 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_V_SLC 31:31 | |
1219 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_V_WIDTH 1 | |
1220 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_V_INT_SLC 0:0 | |
1221 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_V_POSITION 31 | |
1222 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1223 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1224 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_V_POR_VALUE 1'b0 | |
1225 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_FID 2 | |
1226 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_SLC 30:25 | |
1227 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_WIDTH 6 | |
1228 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_INT_SLC 5:0 | |
1229 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_POSITION 25 | |
1230 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1231 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1232 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_T_ID_POR_VALUE 6'b000000 | |
1233 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_FID 3 | |
1234 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_SLC 9:6 | |
1235 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_WIDTH 4 | |
1236 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_INT_SLC 3:0 | |
1237 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_POSITION 6 | |
1238 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1239 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1240 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_38_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1241 | ||
1242 | //------------------------------------------------------- | |
1243 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_39 | |
1244 | //------------------------------------------------------- | |
1245 | ||
1246 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_HW_ADDR 27'b000000011000000001000100111 | |
1247 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_39_ADDR 30'b000000011000000001000100111000 | |
1248 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_39_HW_ADDR 27'b000000011100000001000100111 | |
1249 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_39_ADDR 30'b000000011100000001000100111000 | |
1250 | ||
1251 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_WIDTH 64 | |
1252 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_DEPTH 1 | |
1253 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_SLC 63:0 | |
1254 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_SLC 63:0 | |
1255 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_POSITION 0 | |
1256 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_LOW_ADDR_WIDTH 0 | |
1257 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_ADDR_RANGE 26:0 | |
1258 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1259 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1260 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1261 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1262 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1263 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1264 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1265 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1266 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1267 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1268 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1269 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INTERNAL_REG 1 | |
1270 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_ZERO_TIME_OMNI 1 | |
1271 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_NUM_FIELDS 4 | |
1272 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_MDO_MODE_FID 0 | |
1273 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_MDO_MODE_SLC 63:63 | |
1274 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_MDO_MODE_WIDTH 1 | |
1275 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_MDO_MODE_INT_SLC 0:0 | |
1276 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_MDO_MODE_POSITION 63 | |
1277 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1278 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1279 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_MDO_MODE_POR_VALUE 1'b0 | |
1280 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_V_FID 1 | |
1281 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_V_SLC 31:31 | |
1282 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_V_WIDTH 1 | |
1283 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_V_INT_SLC 0:0 | |
1284 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_V_POSITION 31 | |
1285 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1286 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1287 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_V_POR_VALUE 1'b0 | |
1288 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_FID 2 | |
1289 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_SLC 30:25 | |
1290 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_WIDTH 6 | |
1291 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_INT_SLC 5:0 | |
1292 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_POSITION 25 | |
1293 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1294 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1295 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_T_ID_POR_VALUE 6'b000000 | |
1296 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_FID 3 | |
1297 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_SLC 9:6 | |
1298 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_WIDTH 4 | |
1299 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_INT_SLC 3:0 | |
1300 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_POSITION 6 | |
1301 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1302 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1303 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_39_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1304 | ||
1305 | //------------------------------------------------------- | |
1306 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_40 | |
1307 | //------------------------------------------------------- | |
1308 | ||
1309 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_HW_ADDR 27'b000000011000000001000101000 | |
1310 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_40_ADDR 30'b000000011000000001000101000000 | |
1311 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_40_HW_ADDR 27'b000000011100000001000101000 | |
1312 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_40_ADDR 30'b000000011100000001000101000000 | |
1313 | ||
1314 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_WIDTH 64 | |
1315 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_DEPTH 1 | |
1316 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_SLC 63:0 | |
1317 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_SLC 63:0 | |
1318 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_POSITION 0 | |
1319 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_LOW_ADDR_WIDTH 0 | |
1320 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_ADDR_RANGE 26:0 | |
1321 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1322 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1323 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1324 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1325 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1326 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1327 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1328 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1329 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1330 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1331 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1332 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INTERNAL_REG 1 | |
1333 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_ZERO_TIME_OMNI 1 | |
1334 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_NUM_FIELDS 4 | |
1335 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_MDO_MODE_FID 0 | |
1336 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_MDO_MODE_SLC 63:63 | |
1337 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_MDO_MODE_WIDTH 1 | |
1338 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_MDO_MODE_INT_SLC 0:0 | |
1339 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_MDO_MODE_POSITION 63 | |
1340 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1341 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1342 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_MDO_MODE_POR_VALUE 1'b0 | |
1343 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_V_FID 1 | |
1344 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_V_SLC 31:31 | |
1345 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_V_WIDTH 1 | |
1346 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_V_INT_SLC 0:0 | |
1347 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_V_POSITION 31 | |
1348 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1349 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1350 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_V_POR_VALUE 1'b0 | |
1351 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_FID 2 | |
1352 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_SLC 30:25 | |
1353 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_WIDTH 6 | |
1354 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_INT_SLC 5:0 | |
1355 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_POSITION 25 | |
1356 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1357 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1358 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_T_ID_POR_VALUE 6'b000000 | |
1359 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_FID 3 | |
1360 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_SLC 9:6 | |
1361 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_WIDTH 4 | |
1362 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_INT_SLC 3:0 | |
1363 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_POSITION 6 | |
1364 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1365 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1366 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_40_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1367 | ||
1368 | //------------------------------------------------------- | |
1369 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_41 | |
1370 | //------------------------------------------------------- | |
1371 | ||
1372 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_HW_ADDR 27'b000000011000000001000101001 | |
1373 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_41_ADDR 30'b000000011000000001000101001000 | |
1374 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_41_HW_ADDR 27'b000000011100000001000101001 | |
1375 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_41_ADDR 30'b000000011100000001000101001000 | |
1376 | ||
1377 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_WIDTH 64 | |
1378 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_DEPTH 1 | |
1379 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_SLC 63:0 | |
1380 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_SLC 63:0 | |
1381 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_POSITION 0 | |
1382 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_LOW_ADDR_WIDTH 0 | |
1383 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_ADDR_RANGE 26:0 | |
1384 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1385 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1386 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1387 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1388 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1389 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1390 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1391 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1392 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1393 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1394 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1395 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INTERNAL_REG 1 | |
1396 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_ZERO_TIME_OMNI 1 | |
1397 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_NUM_FIELDS 4 | |
1398 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_MDO_MODE_FID 0 | |
1399 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_MDO_MODE_SLC 63:63 | |
1400 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_MDO_MODE_WIDTH 1 | |
1401 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_MDO_MODE_INT_SLC 0:0 | |
1402 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_MDO_MODE_POSITION 63 | |
1403 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1404 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1405 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_MDO_MODE_POR_VALUE 1'b0 | |
1406 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_V_FID 1 | |
1407 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_V_SLC 31:31 | |
1408 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_V_WIDTH 1 | |
1409 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_V_INT_SLC 0:0 | |
1410 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_V_POSITION 31 | |
1411 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1412 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1413 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_V_POR_VALUE 1'b0 | |
1414 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_FID 2 | |
1415 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_SLC 30:25 | |
1416 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_WIDTH 6 | |
1417 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_INT_SLC 5:0 | |
1418 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_POSITION 25 | |
1419 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1420 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1421 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_T_ID_POR_VALUE 6'b000000 | |
1422 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_FID 3 | |
1423 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_SLC 9:6 | |
1424 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_WIDTH 4 | |
1425 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_INT_SLC 3:0 | |
1426 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_POSITION 6 | |
1427 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1428 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1429 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_41_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1430 | ||
1431 | //------------------------------------------------------- | |
1432 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_42 | |
1433 | //------------------------------------------------------- | |
1434 | ||
1435 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_HW_ADDR 27'b000000011000000001000101010 | |
1436 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_42_ADDR 30'b000000011000000001000101010000 | |
1437 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_42_HW_ADDR 27'b000000011100000001000101010 | |
1438 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_42_ADDR 30'b000000011100000001000101010000 | |
1439 | ||
1440 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_WIDTH 64 | |
1441 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_DEPTH 1 | |
1442 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_SLC 63:0 | |
1443 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_SLC 63:0 | |
1444 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_POSITION 0 | |
1445 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_LOW_ADDR_WIDTH 0 | |
1446 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_ADDR_RANGE 26:0 | |
1447 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1448 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1449 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1450 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1451 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1452 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1453 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1454 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1455 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1456 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1457 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1458 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INTERNAL_REG 1 | |
1459 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_ZERO_TIME_OMNI 1 | |
1460 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_NUM_FIELDS 4 | |
1461 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_MDO_MODE_FID 0 | |
1462 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_MDO_MODE_SLC 63:63 | |
1463 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_MDO_MODE_WIDTH 1 | |
1464 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_MDO_MODE_INT_SLC 0:0 | |
1465 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_MDO_MODE_POSITION 63 | |
1466 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1467 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1468 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_MDO_MODE_POR_VALUE 1'b0 | |
1469 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_V_FID 1 | |
1470 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_V_SLC 31:31 | |
1471 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_V_WIDTH 1 | |
1472 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_V_INT_SLC 0:0 | |
1473 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_V_POSITION 31 | |
1474 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1475 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1476 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_V_POR_VALUE 1'b0 | |
1477 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_FID 2 | |
1478 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_SLC 30:25 | |
1479 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_WIDTH 6 | |
1480 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_INT_SLC 5:0 | |
1481 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_POSITION 25 | |
1482 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1483 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1484 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_T_ID_POR_VALUE 6'b000000 | |
1485 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_FID 3 | |
1486 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_SLC 9:6 | |
1487 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_WIDTH 4 | |
1488 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_INT_SLC 3:0 | |
1489 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_POSITION 6 | |
1490 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1491 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1492 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_42_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1493 | ||
1494 | //------------------------------------------------------- | |
1495 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_43 | |
1496 | //------------------------------------------------------- | |
1497 | ||
1498 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_HW_ADDR 27'b000000011000000001000101011 | |
1499 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_43_ADDR 30'b000000011000000001000101011000 | |
1500 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_43_HW_ADDR 27'b000000011100000001000101011 | |
1501 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_43_ADDR 30'b000000011100000001000101011000 | |
1502 | ||
1503 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_WIDTH 64 | |
1504 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_DEPTH 1 | |
1505 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_SLC 63:0 | |
1506 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_SLC 63:0 | |
1507 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_POSITION 0 | |
1508 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_LOW_ADDR_WIDTH 0 | |
1509 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_ADDR_RANGE 26:0 | |
1510 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1511 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1512 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1513 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1514 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1515 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1516 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1517 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1518 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1519 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1520 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1521 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INTERNAL_REG 1 | |
1522 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_ZERO_TIME_OMNI 1 | |
1523 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_NUM_FIELDS 4 | |
1524 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_MDO_MODE_FID 0 | |
1525 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_MDO_MODE_SLC 63:63 | |
1526 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_MDO_MODE_WIDTH 1 | |
1527 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_MDO_MODE_INT_SLC 0:0 | |
1528 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_MDO_MODE_POSITION 63 | |
1529 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1530 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1531 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_MDO_MODE_POR_VALUE 1'b0 | |
1532 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_V_FID 1 | |
1533 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_V_SLC 31:31 | |
1534 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_V_WIDTH 1 | |
1535 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_V_INT_SLC 0:0 | |
1536 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_V_POSITION 31 | |
1537 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1538 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1539 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_V_POR_VALUE 1'b0 | |
1540 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_FID 2 | |
1541 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_SLC 30:25 | |
1542 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_WIDTH 6 | |
1543 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_INT_SLC 5:0 | |
1544 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_POSITION 25 | |
1545 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1546 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1547 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_T_ID_POR_VALUE 6'b000000 | |
1548 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_FID 3 | |
1549 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_SLC 9:6 | |
1550 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_WIDTH 4 | |
1551 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_INT_SLC 3:0 | |
1552 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_POSITION 6 | |
1553 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1554 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1555 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_43_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1556 | ||
1557 | //------------------------------------------------------- | |
1558 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_44 | |
1559 | //------------------------------------------------------- | |
1560 | ||
1561 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_HW_ADDR 27'b000000011000000001000101100 | |
1562 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_44_ADDR 30'b000000011000000001000101100000 | |
1563 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_44_HW_ADDR 27'b000000011100000001000101100 | |
1564 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_44_ADDR 30'b000000011100000001000101100000 | |
1565 | ||
1566 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_WIDTH 64 | |
1567 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_DEPTH 1 | |
1568 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_SLC 63:0 | |
1569 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_SLC 63:0 | |
1570 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_POSITION 0 | |
1571 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_LOW_ADDR_WIDTH 0 | |
1572 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_ADDR_RANGE 26:0 | |
1573 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1574 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1575 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1576 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1577 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1578 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1579 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1580 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1581 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1582 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1583 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1584 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INTERNAL_REG 1 | |
1585 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_ZERO_TIME_OMNI 1 | |
1586 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_NUM_FIELDS 4 | |
1587 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_MDO_MODE_FID 0 | |
1588 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_MDO_MODE_SLC 63:63 | |
1589 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_MDO_MODE_WIDTH 1 | |
1590 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_MDO_MODE_INT_SLC 0:0 | |
1591 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_MDO_MODE_POSITION 63 | |
1592 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1593 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1594 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_MDO_MODE_POR_VALUE 1'b0 | |
1595 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_V_FID 1 | |
1596 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_V_SLC 31:31 | |
1597 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_V_WIDTH 1 | |
1598 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_V_INT_SLC 0:0 | |
1599 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_V_POSITION 31 | |
1600 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1601 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1602 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_V_POR_VALUE 1'b0 | |
1603 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_FID 2 | |
1604 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_SLC 30:25 | |
1605 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_WIDTH 6 | |
1606 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_INT_SLC 5:0 | |
1607 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_POSITION 25 | |
1608 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1609 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1610 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_T_ID_POR_VALUE 6'b000000 | |
1611 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_FID 3 | |
1612 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_SLC 9:6 | |
1613 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_WIDTH 4 | |
1614 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_INT_SLC 3:0 | |
1615 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_POSITION 6 | |
1616 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1617 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1618 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_44_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1619 | ||
1620 | //------------------------------------------------------- | |
1621 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_45 | |
1622 | //------------------------------------------------------- | |
1623 | ||
1624 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_HW_ADDR 27'b000000011000000001000101101 | |
1625 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_45_ADDR 30'b000000011000000001000101101000 | |
1626 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_45_HW_ADDR 27'b000000011100000001000101101 | |
1627 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_45_ADDR 30'b000000011100000001000101101000 | |
1628 | ||
1629 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_WIDTH 64 | |
1630 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_DEPTH 1 | |
1631 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_SLC 63:0 | |
1632 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_SLC 63:0 | |
1633 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_POSITION 0 | |
1634 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_LOW_ADDR_WIDTH 0 | |
1635 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_ADDR_RANGE 26:0 | |
1636 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1637 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1638 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1639 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1640 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1641 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1642 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1643 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1644 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1645 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1646 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1647 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INTERNAL_REG 1 | |
1648 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_ZERO_TIME_OMNI 1 | |
1649 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_NUM_FIELDS 4 | |
1650 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_MDO_MODE_FID 0 | |
1651 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_MDO_MODE_SLC 63:63 | |
1652 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_MDO_MODE_WIDTH 1 | |
1653 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_MDO_MODE_INT_SLC 0:0 | |
1654 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_MDO_MODE_POSITION 63 | |
1655 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1656 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1657 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_MDO_MODE_POR_VALUE 1'b0 | |
1658 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_V_FID 1 | |
1659 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_V_SLC 31:31 | |
1660 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_V_WIDTH 1 | |
1661 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_V_INT_SLC 0:0 | |
1662 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_V_POSITION 31 | |
1663 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1664 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1665 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_V_POR_VALUE 1'b0 | |
1666 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_FID 2 | |
1667 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_SLC 30:25 | |
1668 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_WIDTH 6 | |
1669 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_INT_SLC 5:0 | |
1670 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_POSITION 25 | |
1671 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1672 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1673 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_T_ID_POR_VALUE 6'b000000 | |
1674 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_FID 3 | |
1675 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_SLC 9:6 | |
1676 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_WIDTH 4 | |
1677 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_INT_SLC 3:0 | |
1678 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_POSITION 6 | |
1679 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1680 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1681 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_45_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1682 | ||
1683 | //------------------------------------------------------- | |
1684 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_46 | |
1685 | //------------------------------------------------------- | |
1686 | ||
1687 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_HW_ADDR 27'b000000011000000001000101110 | |
1688 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_46_ADDR 30'b000000011000000001000101110000 | |
1689 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_46_HW_ADDR 27'b000000011100000001000101110 | |
1690 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_46_ADDR 30'b000000011100000001000101110000 | |
1691 | ||
1692 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_WIDTH 64 | |
1693 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_DEPTH 1 | |
1694 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_SLC 63:0 | |
1695 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_SLC 63:0 | |
1696 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_POSITION 0 | |
1697 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_LOW_ADDR_WIDTH 0 | |
1698 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_ADDR_RANGE 26:0 | |
1699 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1700 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1701 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1702 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1703 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1704 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1705 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1706 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1707 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1708 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1709 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1710 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INTERNAL_REG 1 | |
1711 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_ZERO_TIME_OMNI 1 | |
1712 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_NUM_FIELDS 4 | |
1713 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_MDO_MODE_FID 0 | |
1714 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_MDO_MODE_SLC 63:63 | |
1715 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_MDO_MODE_WIDTH 1 | |
1716 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_MDO_MODE_INT_SLC 0:0 | |
1717 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_MDO_MODE_POSITION 63 | |
1718 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1719 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1720 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_MDO_MODE_POR_VALUE 1'b0 | |
1721 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_V_FID 1 | |
1722 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_V_SLC 31:31 | |
1723 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_V_WIDTH 1 | |
1724 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_V_INT_SLC 0:0 | |
1725 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_V_POSITION 31 | |
1726 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1727 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1728 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_V_POR_VALUE 1'b0 | |
1729 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_FID 2 | |
1730 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_SLC 30:25 | |
1731 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_WIDTH 6 | |
1732 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_INT_SLC 5:0 | |
1733 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_POSITION 25 | |
1734 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1735 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1736 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_T_ID_POR_VALUE 6'b000000 | |
1737 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_FID 3 | |
1738 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_SLC 9:6 | |
1739 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_WIDTH 4 | |
1740 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_INT_SLC 3:0 | |
1741 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_POSITION 6 | |
1742 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1743 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1744 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_46_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1745 | ||
1746 | //------------------------------------------------------- | |
1747 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_47 | |
1748 | //------------------------------------------------------- | |
1749 | ||
1750 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_HW_ADDR 27'b000000011000000001000101111 | |
1751 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_47_ADDR 30'b000000011000000001000101111000 | |
1752 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_47_HW_ADDR 27'b000000011100000001000101111 | |
1753 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_47_ADDR 30'b000000011100000001000101111000 | |
1754 | ||
1755 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_WIDTH 64 | |
1756 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_DEPTH 1 | |
1757 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_SLC 63:0 | |
1758 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_SLC 63:0 | |
1759 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_POSITION 0 | |
1760 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_LOW_ADDR_WIDTH 0 | |
1761 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_ADDR_RANGE 26:0 | |
1762 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1763 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1764 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1765 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1766 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1767 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1768 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1769 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1770 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1771 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1772 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1773 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INTERNAL_REG 1 | |
1774 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_ZERO_TIME_OMNI 1 | |
1775 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_NUM_FIELDS 4 | |
1776 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_MDO_MODE_FID 0 | |
1777 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_MDO_MODE_SLC 63:63 | |
1778 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_MDO_MODE_WIDTH 1 | |
1779 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_MDO_MODE_INT_SLC 0:0 | |
1780 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_MDO_MODE_POSITION 63 | |
1781 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1782 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1783 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_MDO_MODE_POR_VALUE 1'b0 | |
1784 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_V_FID 1 | |
1785 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_V_SLC 31:31 | |
1786 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_V_WIDTH 1 | |
1787 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_V_INT_SLC 0:0 | |
1788 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_V_POSITION 31 | |
1789 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1790 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1791 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_V_POR_VALUE 1'b0 | |
1792 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_FID 2 | |
1793 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_SLC 30:25 | |
1794 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_WIDTH 6 | |
1795 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_INT_SLC 5:0 | |
1796 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_POSITION 25 | |
1797 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1798 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1799 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_T_ID_POR_VALUE 6'b000000 | |
1800 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_FID 3 | |
1801 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_SLC 9:6 | |
1802 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_WIDTH 4 | |
1803 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_INT_SLC 3:0 | |
1804 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_POSITION 6 | |
1805 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1806 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1807 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_47_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1808 | ||
1809 | //------------------------------------------------------- | |
1810 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_48 | |
1811 | //------------------------------------------------------- | |
1812 | ||
1813 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_HW_ADDR 27'b000000011000000001000110000 | |
1814 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_48_ADDR 30'b000000011000000001000110000000 | |
1815 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_48_HW_ADDR 27'b000000011100000001000110000 | |
1816 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_48_ADDR 30'b000000011100000001000110000000 | |
1817 | ||
1818 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_WIDTH 64 | |
1819 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_DEPTH 1 | |
1820 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_SLC 63:0 | |
1821 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_SLC 63:0 | |
1822 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_POSITION 0 | |
1823 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_LOW_ADDR_WIDTH 0 | |
1824 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_ADDR_RANGE 26:0 | |
1825 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1826 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1827 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1828 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1829 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1830 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1831 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1832 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1833 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1834 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1835 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1836 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INTERNAL_REG 1 | |
1837 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_ZERO_TIME_OMNI 1 | |
1838 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_NUM_FIELDS 4 | |
1839 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_MDO_MODE_FID 0 | |
1840 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_MDO_MODE_SLC 63:63 | |
1841 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_MDO_MODE_WIDTH 1 | |
1842 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_MDO_MODE_INT_SLC 0:0 | |
1843 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_MDO_MODE_POSITION 63 | |
1844 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1845 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1846 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_MDO_MODE_POR_VALUE 1'b0 | |
1847 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_V_FID 1 | |
1848 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_V_SLC 31:31 | |
1849 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_V_WIDTH 1 | |
1850 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_V_INT_SLC 0:0 | |
1851 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_V_POSITION 31 | |
1852 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1853 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1854 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_V_POR_VALUE 1'b0 | |
1855 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_FID 2 | |
1856 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_SLC 30:25 | |
1857 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_WIDTH 6 | |
1858 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_INT_SLC 5:0 | |
1859 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_POSITION 25 | |
1860 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1861 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1862 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_T_ID_POR_VALUE 6'b000000 | |
1863 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_FID 3 | |
1864 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_SLC 9:6 | |
1865 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_WIDTH 4 | |
1866 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_INT_SLC 3:0 | |
1867 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_POSITION 6 | |
1868 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1869 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1870 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_48_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1871 | ||
1872 | //------------------------------------------------------- | |
1873 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_49 | |
1874 | //------------------------------------------------------- | |
1875 | ||
1876 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_HW_ADDR 27'b000000011000000001000110001 | |
1877 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_49_ADDR 30'b000000011000000001000110001000 | |
1878 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_49_HW_ADDR 27'b000000011100000001000110001 | |
1879 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_49_ADDR 30'b000000011100000001000110001000 | |
1880 | ||
1881 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_WIDTH 64 | |
1882 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_DEPTH 1 | |
1883 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_SLC 63:0 | |
1884 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_SLC 63:0 | |
1885 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_POSITION 0 | |
1886 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_LOW_ADDR_WIDTH 0 | |
1887 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_ADDR_RANGE 26:0 | |
1888 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1889 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1890 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1891 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1892 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1893 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1894 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1895 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1896 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1897 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1898 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1899 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INTERNAL_REG 1 | |
1900 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_ZERO_TIME_OMNI 1 | |
1901 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_NUM_FIELDS 4 | |
1902 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_MDO_MODE_FID 0 | |
1903 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_MDO_MODE_SLC 63:63 | |
1904 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_MDO_MODE_WIDTH 1 | |
1905 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_MDO_MODE_INT_SLC 0:0 | |
1906 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_MDO_MODE_POSITION 63 | |
1907 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1908 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1909 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_MDO_MODE_POR_VALUE 1'b0 | |
1910 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_V_FID 1 | |
1911 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_V_SLC 31:31 | |
1912 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_V_WIDTH 1 | |
1913 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_V_INT_SLC 0:0 | |
1914 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_V_POSITION 31 | |
1915 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1916 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1917 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_V_POR_VALUE 1'b0 | |
1918 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_FID 2 | |
1919 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_SLC 30:25 | |
1920 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_WIDTH 6 | |
1921 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_INT_SLC 5:0 | |
1922 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_POSITION 25 | |
1923 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1924 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1925 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_T_ID_POR_VALUE 6'b000000 | |
1926 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_FID 3 | |
1927 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_SLC 9:6 | |
1928 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_WIDTH 4 | |
1929 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_INT_SLC 3:0 | |
1930 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_POSITION 6 | |
1931 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1932 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1933 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_49_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1934 | ||
1935 | //------------------------------------------------------- | |
1936 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_50 | |
1937 | //------------------------------------------------------- | |
1938 | ||
1939 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_HW_ADDR 27'b000000011000000001000110010 | |
1940 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_50_ADDR 30'b000000011000000001000110010000 | |
1941 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_50_HW_ADDR 27'b000000011100000001000110010 | |
1942 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_50_ADDR 30'b000000011100000001000110010000 | |
1943 | ||
1944 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_WIDTH 64 | |
1945 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_DEPTH 1 | |
1946 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_SLC 63:0 | |
1947 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_SLC 63:0 | |
1948 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_POSITION 0 | |
1949 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_LOW_ADDR_WIDTH 0 | |
1950 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_ADDR_RANGE 26:0 | |
1951 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1952 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1953 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1954 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1955 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1956 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1957 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1958 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
1959 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
1960 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1961 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1962 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INTERNAL_REG 1 | |
1963 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_ZERO_TIME_OMNI 1 | |
1964 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_NUM_FIELDS 4 | |
1965 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_MDO_MODE_FID 0 | |
1966 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_MDO_MODE_SLC 63:63 | |
1967 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_MDO_MODE_WIDTH 1 | |
1968 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_MDO_MODE_INT_SLC 0:0 | |
1969 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_MDO_MODE_POSITION 63 | |
1970 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
1971 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1972 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_MDO_MODE_POR_VALUE 1'b0 | |
1973 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_V_FID 1 | |
1974 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_V_SLC 31:31 | |
1975 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_V_WIDTH 1 | |
1976 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_V_INT_SLC 0:0 | |
1977 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_V_POSITION 31 | |
1978 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
1979 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1980 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_V_POR_VALUE 1'b0 | |
1981 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_FID 2 | |
1982 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_SLC 30:25 | |
1983 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_WIDTH 6 | |
1984 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_INT_SLC 5:0 | |
1985 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_POSITION 25 | |
1986 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
1987 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1988 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_T_ID_POR_VALUE 6'b000000 | |
1989 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_FID 3 | |
1990 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_SLC 9:6 | |
1991 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_WIDTH 4 | |
1992 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_INT_SLC 3:0 | |
1993 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_POSITION 6 | |
1994 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
1995 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
1996 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_50_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
1997 | ||
1998 | //------------------------------------------------------- | |
1999 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_51 | |
2000 | //------------------------------------------------------- | |
2001 | ||
2002 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_HW_ADDR 27'b000000011000000001000110011 | |
2003 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_51_ADDR 30'b000000011000000001000110011000 | |
2004 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_51_HW_ADDR 27'b000000011100000001000110011 | |
2005 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_51_ADDR 30'b000000011100000001000110011000 | |
2006 | ||
2007 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_WIDTH 64 | |
2008 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_DEPTH 1 | |
2009 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_SLC 63:0 | |
2010 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_SLC 63:0 | |
2011 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_POSITION 0 | |
2012 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_LOW_ADDR_WIDTH 0 | |
2013 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_ADDR_RANGE 26:0 | |
2014 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2015 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2016 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2017 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2018 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2019 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2020 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2021 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2022 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2023 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2024 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2025 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INTERNAL_REG 1 | |
2026 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_ZERO_TIME_OMNI 1 | |
2027 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_NUM_FIELDS 4 | |
2028 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_MDO_MODE_FID 0 | |
2029 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_MDO_MODE_SLC 63:63 | |
2030 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_MDO_MODE_WIDTH 1 | |
2031 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_MDO_MODE_INT_SLC 0:0 | |
2032 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_MDO_MODE_POSITION 63 | |
2033 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2034 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2035 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_MDO_MODE_POR_VALUE 1'b0 | |
2036 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_V_FID 1 | |
2037 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_V_SLC 31:31 | |
2038 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_V_WIDTH 1 | |
2039 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_V_INT_SLC 0:0 | |
2040 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_V_POSITION 31 | |
2041 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2042 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2043 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_V_POR_VALUE 1'b0 | |
2044 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_FID 2 | |
2045 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_SLC 30:25 | |
2046 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_WIDTH 6 | |
2047 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_INT_SLC 5:0 | |
2048 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_POSITION 25 | |
2049 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2050 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2051 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_T_ID_POR_VALUE 6'b000000 | |
2052 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_FID 3 | |
2053 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_SLC 9:6 | |
2054 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_WIDTH 4 | |
2055 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_INT_SLC 3:0 | |
2056 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_POSITION 6 | |
2057 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2058 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2059 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_51_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2060 | ||
2061 | //------------------------------------------------------- | |
2062 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_52 | |
2063 | //------------------------------------------------------- | |
2064 | ||
2065 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_HW_ADDR 27'b000000011000000001000110100 | |
2066 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_52_ADDR 30'b000000011000000001000110100000 | |
2067 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_52_HW_ADDR 27'b000000011100000001000110100 | |
2068 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_52_ADDR 30'b000000011100000001000110100000 | |
2069 | ||
2070 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_WIDTH 64 | |
2071 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_DEPTH 1 | |
2072 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_SLC 63:0 | |
2073 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_SLC 63:0 | |
2074 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_POSITION 0 | |
2075 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_LOW_ADDR_WIDTH 0 | |
2076 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_ADDR_RANGE 26:0 | |
2077 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2078 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2079 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2080 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2081 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2082 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2083 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2084 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2085 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2086 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2087 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2088 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INTERNAL_REG 1 | |
2089 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_ZERO_TIME_OMNI 1 | |
2090 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_NUM_FIELDS 4 | |
2091 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_MDO_MODE_FID 0 | |
2092 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_MDO_MODE_SLC 63:63 | |
2093 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_MDO_MODE_WIDTH 1 | |
2094 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_MDO_MODE_INT_SLC 0:0 | |
2095 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_MDO_MODE_POSITION 63 | |
2096 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2097 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2098 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_MDO_MODE_POR_VALUE 1'b0 | |
2099 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_V_FID 1 | |
2100 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_V_SLC 31:31 | |
2101 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_V_WIDTH 1 | |
2102 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_V_INT_SLC 0:0 | |
2103 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_V_POSITION 31 | |
2104 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2105 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2106 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_V_POR_VALUE 1'b0 | |
2107 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_FID 2 | |
2108 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_SLC 30:25 | |
2109 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_WIDTH 6 | |
2110 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_INT_SLC 5:0 | |
2111 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_POSITION 25 | |
2112 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2113 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2114 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_T_ID_POR_VALUE 6'b000000 | |
2115 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_FID 3 | |
2116 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_SLC 9:6 | |
2117 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_WIDTH 4 | |
2118 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_INT_SLC 3:0 | |
2119 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_POSITION 6 | |
2120 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2121 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2122 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_52_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2123 | ||
2124 | //------------------------------------------------------- | |
2125 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_53 | |
2126 | //------------------------------------------------------- | |
2127 | ||
2128 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_HW_ADDR 27'b000000011000000001000110101 | |
2129 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_53_ADDR 30'b000000011000000001000110101000 | |
2130 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_53_HW_ADDR 27'b000000011100000001000110101 | |
2131 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_53_ADDR 30'b000000011100000001000110101000 | |
2132 | ||
2133 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_WIDTH 64 | |
2134 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_DEPTH 1 | |
2135 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_SLC 63:0 | |
2136 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_SLC 63:0 | |
2137 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_POSITION 0 | |
2138 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_LOW_ADDR_WIDTH 0 | |
2139 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_ADDR_RANGE 26:0 | |
2140 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2141 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2142 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2143 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2144 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2145 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2146 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2147 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2148 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2149 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2150 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2151 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INTERNAL_REG 1 | |
2152 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_ZERO_TIME_OMNI 1 | |
2153 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_NUM_FIELDS 4 | |
2154 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_MDO_MODE_FID 0 | |
2155 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_MDO_MODE_SLC 63:63 | |
2156 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_MDO_MODE_WIDTH 1 | |
2157 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_MDO_MODE_INT_SLC 0:0 | |
2158 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_MDO_MODE_POSITION 63 | |
2159 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2160 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2161 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_MDO_MODE_POR_VALUE 1'b0 | |
2162 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_V_FID 1 | |
2163 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_V_SLC 31:31 | |
2164 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_V_WIDTH 1 | |
2165 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_V_INT_SLC 0:0 | |
2166 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_V_POSITION 31 | |
2167 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2168 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2169 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_V_POR_VALUE 1'b0 | |
2170 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_FID 2 | |
2171 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_SLC 30:25 | |
2172 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_WIDTH 6 | |
2173 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_INT_SLC 5:0 | |
2174 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_POSITION 25 | |
2175 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2176 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2177 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_T_ID_POR_VALUE 6'b000000 | |
2178 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_FID 3 | |
2179 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_SLC 9:6 | |
2180 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_WIDTH 4 | |
2181 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_INT_SLC 3:0 | |
2182 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_POSITION 6 | |
2183 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2184 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2185 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_53_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2186 | ||
2187 | //------------------------------------------------------- | |
2188 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_54 | |
2189 | //------------------------------------------------------- | |
2190 | ||
2191 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_HW_ADDR 27'b000000011000000001000110110 | |
2192 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_54_ADDR 30'b000000011000000001000110110000 | |
2193 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_54_HW_ADDR 27'b000000011100000001000110110 | |
2194 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_54_ADDR 30'b000000011100000001000110110000 | |
2195 | ||
2196 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_WIDTH 64 | |
2197 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_DEPTH 1 | |
2198 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_SLC 63:0 | |
2199 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_SLC 63:0 | |
2200 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_POSITION 0 | |
2201 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_LOW_ADDR_WIDTH 0 | |
2202 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_ADDR_RANGE 26:0 | |
2203 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2204 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2205 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2206 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2207 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2208 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2209 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2210 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2211 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2212 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2213 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2214 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INTERNAL_REG 1 | |
2215 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_ZERO_TIME_OMNI 1 | |
2216 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_NUM_FIELDS 4 | |
2217 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_MDO_MODE_FID 0 | |
2218 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_MDO_MODE_SLC 63:63 | |
2219 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_MDO_MODE_WIDTH 1 | |
2220 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_MDO_MODE_INT_SLC 0:0 | |
2221 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_MDO_MODE_POSITION 63 | |
2222 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2223 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2224 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_MDO_MODE_POR_VALUE 1'b0 | |
2225 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_V_FID 1 | |
2226 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_V_SLC 31:31 | |
2227 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_V_WIDTH 1 | |
2228 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_V_INT_SLC 0:0 | |
2229 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_V_POSITION 31 | |
2230 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2231 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2232 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_V_POR_VALUE 1'b0 | |
2233 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_FID 2 | |
2234 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_SLC 30:25 | |
2235 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_WIDTH 6 | |
2236 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_INT_SLC 5:0 | |
2237 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_POSITION 25 | |
2238 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2239 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2240 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_T_ID_POR_VALUE 6'b000000 | |
2241 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_FID 3 | |
2242 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_SLC 9:6 | |
2243 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_WIDTH 4 | |
2244 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_INT_SLC 3:0 | |
2245 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_POSITION 6 | |
2246 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2247 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2248 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_54_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2249 | ||
2250 | //------------------------------------------------------- | |
2251 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_55 | |
2252 | //------------------------------------------------------- | |
2253 | ||
2254 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_HW_ADDR 27'b000000011000000001000110111 | |
2255 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_55_ADDR 30'b000000011000000001000110111000 | |
2256 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_55_HW_ADDR 27'b000000011100000001000110111 | |
2257 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_55_ADDR 30'b000000011100000001000110111000 | |
2258 | ||
2259 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_WIDTH 64 | |
2260 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_DEPTH 1 | |
2261 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_SLC 63:0 | |
2262 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_SLC 63:0 | |
2263 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_POSITION 0 | |
2264 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_LOW_ADDR_WIDTH 0 | |
2265 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_ADDR_RANGE 26:0 | |
2266 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2267 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2268 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2269 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2270 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2271 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2272 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2273 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2274 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2275 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2276 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2277 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INTERNAL_REG 1 | |
2278 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_ZERO_TIME_OMNI 1 | |
2279 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_NUM_FIELDS 4 | |
2280 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_MDO_MODE_FID 0 | |
2281 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_MDO_MODE_SLC 63:63 | |
2282 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_MDO_MODE_WIDTH 1 | |
2283 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_MDO_MODE_INT_SLC 0:0 | |
2284 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_MDO_MODE_POSITION 63 | |
2285 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2286 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2287 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_MDO_MODE_POR_VALUE 1'b0 | |
2288 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_V_FID 1 | |
2289 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_V_SLC 31:31 | |
2290 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_V_WIDTH 1 | |
2291 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_V_INT_SLC 0:0 | |
2292 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_V_POSITION 31 | |
2293 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2294 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2295 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_V_POR_VALUE 1'b0 | |
2296 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_FID 2 | |
2297 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_SLC 30:25 | |
2298 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_WIDTH 6 | |
2299 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_INT_SLC 5:0 | |
2300 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_POSITION 25 | |
2301 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2302 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2303 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_T_ID_POR_VALUE 6'b000000 | |
2304 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_FID 3 | |
2305 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_SLC 9:6 | |
2306 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_WIDTH 4 | |
2307 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_INT_SLC 3:0 | |
2308 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_POSITION 6 | |
2309 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2310 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2311 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_55_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2312 | ||
2313 | //------------------------------------------------------- | |
2314 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_56 | |
2315 | //------------------------------------------------------- | |
2316 | ||
2317 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_HW_ADDR 27'b000000011000000001000111000 | |
2318 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_56_ADDR 30'b000000011000000001000111000000 | |
2319 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_56_HW_ADDR 27'b000000011100000001000111000 | |
2320 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_56_ADDR 30'b000000011100000001000111000000 | |
2321 | ||
2322 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_WIDTH 64 | |
2323 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_DEPTH 1 | |
2324 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_SLC 63:0 | |
2325 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_SLC 63:0 | |
2326 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_POSITION 0 | |
2327 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_LOW_ADDR_WIDTH 0 | |
2328 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_ADDR_RANGE 26:0 | |
2329 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2330 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2331 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2332 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2333 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2334 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2335 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2336 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2337 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2338 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2339 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2340 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INTERNAL_REG 1 | |
2341 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_ZERO_TIME_OMNI 1 | |
2342 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_NUM_FIELDS 4 | |
2343 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_MDO_MODE_FID 0 | |
2344 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_MDO_MODE_SLC 63:63 | |
2345 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_MDO_MODE_WIDTH 1 | |
2346 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_MDO_MODE_INT_SLC 0:0 | |
2347 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_MDO_MODE_POSITION 63 | |
2348 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2349 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2350 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_MDO_MODE_POR_VALUE 1'b0 | |
2351 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_V_FID 1 | |
2352 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_V_SLC 31:31 | |
2353 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_V_WIDTH 1 | |
2354 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_V_INT_SLC 0:0 | |
2355 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_V_POSITION 31 | |
2356 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2357 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2358 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_V_POR_VALUE 1'b0 | |
2359 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_FID 2 | |
2360 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_SLC 30:25 | |
2361 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_WIDTH 6 | |
2362 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_INT_SLC 5:0 | |
2363 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_POSITION 25 | |
2364 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2365 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2366 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_T_ID_POR_VALUE 6'b000000 | |
2367 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_FID 3 | |
2368 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_SLC 9:6 | |
2369 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_WIDTH 4 | |
2370 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_INT_SLC 3:0 | |
2371 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_POSITION 6 | |
2372 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2373 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2374 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_56_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2375 | ||
2376 | //------------------------------------------------------- | |
2377 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_57 | |
2378 | //------------------------------------------------------- | |
2379 | ||
2380 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_HW_ADDR 27'b000000011000000001000111001 | |
2381 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_57_ADDR 30'b000000011000000001000111001000 | |
2382 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_57_HW_ADDR 27'b000000011100000001000111001 | |
2383 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_57_ADDR 30'b000000011100000001000111001000 | |
2384 | ||
2385 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_WIDTH 64 | |
2386 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_DEPTH 1 | |
2387 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_SLC 63:0 | |
2388 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_SLC 63:0 | |
2389 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_POSITION 0 | |
2390 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_LOW_ADDR_WIDTH 0 | |
2391 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_ADDR_RANGE 26:0 | |
2392 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2393 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2394 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2395 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2396 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2397 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2398 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2399 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2400 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2401 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2402 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2403 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INTERNAL_REG 1 | |
2404 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_ZERO_TIME_OMNI 1 | |
2405 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_NUM_FIELDS 4 | |
2406 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_MDO_MODE_FID 0 | |
2407 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_MDO_MODE_SLC 63:63 | |
2408 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_MDO_MODE_WIDTH 1 | |
2409 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_MDO_MODE_INT_SLC 0:0 | |
2410 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_MDO_MODE_POSITION 63 | |
2411 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2412 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2413 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_MDO_MODE_POR_VALUE 1'b0 | |
2414 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_V_FID 1 | |
2415 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_V_SLC 31:31 | |
2416 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_V_WIDTH 1 | |
2417 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_V_INT_SLC 0:0 | |
2418 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_V_POSITION 31 | |
2419 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2420 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2421 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_V_POR_VALUE 1'b0 | |
2422 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_FID 2 | |
2423 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_SLC 30:25 | |
2424 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_WIDTH 6 | |
2425 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_INT_SLC 5:0 | |
2426 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_POSITION 25 | |
2427 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2428 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2429 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_T_ID_POR_VALUE 6'b000000 | |
2430 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_FID 3 | |
2431 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_SLC 9:6 | |
2432 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_WIDTH 4 | |
2433 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_INT_SLC 3:0 | |
2434 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_POSITION 6 | |
2435 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2436 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2437 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_57_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2438 | ||
2439 | //------------------------------------------------------- | |
2440 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_58 | |
2441 | //------------------------------------------------------- | |
2442 | ||
2443 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_HW_ADDR 27'b000000011000000001000111010 | |
2444 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_58_ADDR 30'b000000011000000001000111010000 | |
2445 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_58_HW_ADDR 27'b000000011100000001000111010 | |
2446 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_58_ADDR 30'b000000011100000001000111010000 | |
2447 | ||
2448 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_WIDTH 64 | |
2449 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_DEPTH 1 | |
2450 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_SLC 63:0 | |
2451 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_SLC 63:0 | |
2452 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_POSITION 0 | |
2453 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_LOW_ADDR_WIDTH 0 | |
2454 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_ADDR_RANGE 26:0 | |
2455 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2456 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2457 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2458 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2459 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2460 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2461 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2462 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2463 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2464 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2465 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2466 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INTERNAL_REG 1 | |
2467 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_ZERO_TIME_OMNI 1 | |
2468 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_NUM_FIELDS 4 | |
2469 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_MDO_MODE_FID 0 | |
2470 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_MDO_MODE_SLC 63:63 | |
2471 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_MDO_MODE_WIDTH 1 | |
2472 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_MDO_MODE_INT_SLC 0:0 | |
2473 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_MDO_MODE_POSITION 63 | |
2474 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2475 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2476 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_MDO_MODE_POR_VALUE 1'b0 | |
2477 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_V_FID 1 | |
2478 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_V_SLC 31:31 | |
2479 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_V_WIDTH 1 | |
2480 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_V_INT_SLC 0:0 | |
2481 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_V_POSITION 31 | |
2482 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2483 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2484 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_V_POR_VALUE 1'b0 | |
2485 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_FID 2 | |
2486 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_SLC 30:25 | |
2487 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_WIDTH 6 | |
2488 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_INT_SLC 5:0 | |
2489 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_POSITION 25 | |
2490 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2491 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2492 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_T_ID_POR_VALUE 6'b000000 | |
2493 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_FID 3 | |
2494 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_SLC 9:6 | |
2495 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_WIDTH 4 | |
2496 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_INT_SLC 3:0 | |
2497 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_POSITION 6 | |
2498 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2499 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2500 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_58_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2501 | ||
2502 | //------------------------------------------------------- | |
2503 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_59 | |
2504 | //------------------------------------------------------- | |
2505 | ||
2506 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_HW_ADDR 27'b000000011000000001000111011 | |
2507 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_59_ADDR 30'b000000011000000001000111011000 | |
2508 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_59_HW_ADDR 27'b000000011100000001000111011 | |
2509 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_59_ADDR 30'b000000011100000001000111011000 | |
2510 | ||
2511 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_WIDTH 64 | |
2512 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_DEPTH 1 | |
2513 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_SLC 63:0 | |
2514 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_SLC 63:0 | |
2515 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_POSITION 0 | |
2516 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_LOW_ADDR_WIDTH 0 | |
2517 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_ADDR_RANGE 26:0 | |
2518 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2519 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2520 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2521 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2522 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2523 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2524 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2525 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2526 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2527 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2528 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2529 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INTERNAL_REG 1 | |
2530 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_ZERO_TIME_OMNI 1 | |
2531 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_NUM_FIELDS 4 | |
2532 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_MDO_MODE_FID 0 | |
2533 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_MDO_MODE_SLC 63:63 | |
2534 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_MDO_MODE_WIDTH 1 | |
2535 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_MDO_MODE_INT_SLC 0:0 | |
2536 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_MDO_MODE_POSITION 63 | |
2537 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2538 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2539 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_MDO_MODE_POR_VALUE 1'b0 | |
2540 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_V_FID 1 | |
2541 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_V_SLC 31:31 | |
2542 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_V_WIDTH 1 | |
2543 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_V_INT_SLC 0:0 | |
2544 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_V_POSITION 31 | |
2545 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2546 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2547 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_V_POR_VALUE 1'b0 | |
2548 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_FID 2 | |
2549 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_SLC 30:25 | |
2550 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_WIDTH 6 | |
2551 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_INT_SLC 5:0 | |
2552 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_POSITION 25 | |
2553 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2554 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2555 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_T_ID_POR_VALUE 6'b000000 | |
2556 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_FID 3 | |
2557 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_SLC 9:6 | |
2558 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_WIDTH 4 | |
2559 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_INT_SLC 3:0 | |
2560 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_POSITION 6 | |
2561 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2562 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2563 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_59_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2564 | ||
2565 | //------------------------------------------------------- | |
2566 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_62 | |
2567 | //------------------------------------------------------- | |
2568 | ||
2569 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_HW_ADDR 27'b000000011000000001000111110 | |
2570 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_62_ADDR 30'b000000011000000001000111110000 | |
2571 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_62_HW_ADDR 27'b000000011100000001000111110 | |
2572 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_62_ADDR 30'b000000011100000001000111110000 | |
2573 | ||
2574 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_WIDTH 64 | |
2575 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_DEPTH 1 | |
2576 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_SLC 63:0 | |
2577 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_SLC 63:0 | |
2578 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_POSITION 0 | |
2579 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_LOW_ADDR_WIDTH 0 | |
2580 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_ADDR_RANGE 26:0 | |
2581 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2582 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2583 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2584 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2585 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2586 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2587 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2588 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2589 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2590 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2591 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2592 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INTERNAL_REG 1 | |
2593 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_ZERO_TIME_OMNI 1 | |
2594 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_NUM_FIELDS 4 | |
2595 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_MDO_MODE_FID 0 | |
2596 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_MDO_MODE_SLC 63:63 | |
2597 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_MDO_MODE_WIDTH 1 | |
2598 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_MDO_MODE_INT_SLC 0:0 | |
2599 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_MDO_MODE_POSITION 63 | |
2600 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2601 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2602 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_MDO_MODE_POR_VALUE 1'b0 | |
2603 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_V_FID 1 | |
2604 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_V_SLC 31:31 | |
2605 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_V_WIDTH 1 | |
2606 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_V_INT_SLC 0:0 | |
2607 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_V_POSITION 31 | |
2608 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2609 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2610 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_V_POR_VALUE 1'b0 | |
2611 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_FID 2 | |
2612 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_SLC 30:25 | |
2613 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_WIDTH 6 | |
2614 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_INT_SLC 5:0 | |
2615 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_POSITION 25 | |
2616 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2617 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2618 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_T_ID_POR_VALUE 6'b000000 | |
2619 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_FID 3 | |
2620 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_SLC 9:6 | |
2621 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_WIDTH 4 | |
2622 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_INT_SLC 3:0 | |
2623 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_POSITION 6 | |
2624 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2625 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2626 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_62_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2627 | ||
2628 | //------------------------------------------------------- | |
2629 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_mapping_63 | |
2630 | //------------------------------------------------------- | |
2631 | ||
2632 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_HW_ADDR 27'b000000011000000001000111111 | |
2633 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_MAPPING_63_ADDR 30'b000000011000000001000111111000 | |
2634 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_63_HW_ADDR 27'b000000011100000001000111111 | |
2635 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_MAPPING_63_ADDR 30'b000000011100000001000111111000 | |
2636 | ||
2637 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_WIDTH 64 | |
2638 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_DEPTH 1 | |
2639 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_SLC 63:0 | |
2640 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_SLC 63:0 | |
2641 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_POSITION 0 | |
2642 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_LOW_ADDR_WIDTH 0 | |
2643 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_ADDR_RANGE 26:0 | |
2644 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_READ_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2645 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2646 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_WRITE_MASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2647 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2648 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2649 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2650 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2651 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_RMASK 64'b1000000000000000000000000000000011111110000000000000001111000000 | |
2652 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_RESERVED_BIT_MASK 64'b0111111111111111111111111111111100000001111111111111110000111111 | |
2653 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2654 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2655 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INTERNAL_REG 1 | |
2656 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_ZERO_TIME_OMNI 1 | |
2657 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_NUM_FIELDS 4 | |
2658 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_MDO_MODE_FID 0 | |
2659 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_MDO_MODE_SLC 63:63 | |
2660 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_MDO_MODE_WIDTH 1 | |
2661 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_MDO_MODE_INT_SLC 0:0 | |
2662 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_MDO_MODE_POSITION 63 | |
2663 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_MDO_MODE_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000 | |
2664 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_MDO_MODE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2665 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_MDO_MODE_POR_VALUE 1'b0 | |
2666 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_V_FID 1 | |
2667 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_V_SLC 31:31 | |
2668 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_V_WIDTH 1 | |
2669 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_V_INT_SLC 0:0 | |
2670 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_V_POSITION 31 | |
2671 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_V_FMASK 64'b0000000000000000000000000000000010000000000000000000000000000000 | |
2672 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2673 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_V_POR_VALUE 1'b0 | |
2674 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_FID 2 | |
2675 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_SLC 30:25 | |
2676 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_WIDTH 6 | |
2677 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_INT_SLC 5:0 | |
2678 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_POSITION 25 | |
2679 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_FMASK 64'b0000000000000000000000000000000001111110000000000000000000000000 | |
2680 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2681 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_T_ID_POR_VALUE 6'b000000 | |
2682 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_FID 3 | |
2683 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_SLC 9:6 | |
2684 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_WIDTH 4 | |
2685 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_INT_SLC 3:0 | |
2686 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_POSITION 6 | |
2687 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_FMASK 64'b0000000000000000000000000000000000000000000000000000001111000000 | |
2688 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2689 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_MAPPING_63_INT_CNTRL_NUM_POR_VALUE 4'b0000 | |
2690 | ||
2691 | //------------------------------------------------------- | |
2692 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_20 | |
2693 | //------------------------------------------------------- | |
2694 | ||
2695 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_HW_ADDR 27'b000000011000000001010010100 | |
2696 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_20_ADDR 30'b000000011000000001010010100000 | |
2697 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_20_HW_ADDR 27'b000000011100000001010010100 | |
2698 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_20_ADDR 30'b000000011100000001010010100000 | |
2699 | ||
2700 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_WIDTH 64 | |
2701 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_DEPTH 1 | |
2702 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_SLC 63:0 | |
2703 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INT_SLC 63:0 | |
2704 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_POSITION 0 | |
2705 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_LOW_ADDR_WIDTH 0 | |
2706 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_ADDR_RANGE 26:0 | |
2707 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2708 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2709 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2710 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2711 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2712 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2713 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2714 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2715 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
2716 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2717 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2718 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INTERNAL_REG 0 | |
2719 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_EXTERNAL_DECODE_REG 1 | |
2720 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_ZERO_TIME_OMNI 0 | |
2721 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_NUM_FIELDS 1 | |
2722 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INT_STATE_FID 0 | |
2723 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INT_STATE_SLC 1:0 | |
2724 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INT_STATE_WIDTH 2 | |
2725 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INT_STATE_INT_SLC 1:0 | |
2726 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INT_STATE_POSITION 0 | |
2727 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2728 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2729 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_20_INT_STATE_POR_VALUE 2'b00 | |
2730 | ||
2731 | //------------------------------------------------------- | |
2732 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_21 | |
2733 | //------------------------------------------------------- | |
2734 | ||
2735 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_HW_ADDR 27'b000000011000000001010010101 | |
2736 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_21_ADDR 30'b000000011000000001010010101000 | |
2737 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_21_HW_ADDR 27'b000000011100000001010010101 | |
2738 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_21_ADDR 30'b000000011100000001010010101000 | |
2739 | ||
2740 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_WIDTH 64 | |
2741 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_DEPTH 1 | |
2742 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_SLC 63:0 | |
2743 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INT_SLC 63:0 | |
2744 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_POSITION 0 | |
2745 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_LOW_ADDR_WIDTH 0 | |
2746 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_ADDR_RANGE 26:0 | |
2747 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2748 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2749 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2750 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2751 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2752 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2753 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2754 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2755 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
2756 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2757 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2758 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INTERNAL_REG 0 | |
2759 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_EXTERNAL_DECODE_REG 1 | |
2760 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_ZERO_TIME_OMNI 0 | |
2761 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_NUM_FIELDS 1 | |
2762 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INT_STATE_FID 0 | |
2763 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INT_STATE_SLC 1:0 | |
2764 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INT_STATE_WIDTH 2 | |
2765 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INT_STATE_INT_SLC 1:0 | |
2766 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INT_STATE_POSITION 0 | |
2767 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2768 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2769 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_21_INT_STATE_POR_VALUE 2'b00 | |
2770 | ||
2771 | //------------------------------------------------------- | |
2772 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_22 | |
2773 | //------------------------------------------------------- | |
2774 | ||
2775 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_HW_ADDR 27'b000000011000000001010010110 | |
2776 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_22_ADDR 30'b000000011000000001010010110000 | |
2777 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_22_HW_ADDR 27'b000000011100000001010010110 | |
2778 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_22_ADDR 30'b000000011100000001010010110000 | |
2779 | ||
2780 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_WIDTH 64 | |
2781 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_DEPTH 1 | |
2782 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_SLC 63:0 | |
2783 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INT_SLC 63:0 | |
2784 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_POSITION 0 | |
2785 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_LOW_ADDR_WIDTH 0 | |
2786 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_ADDR_RANGE 26:0 | |
2787 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2788 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2789 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2790 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2791 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2792 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2793 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2794 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2795 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
2796 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2797 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2798 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INTERNAL_REG 0 | |
2799 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_EXTERNAL_DECODE_REG 1 | |
2800 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_ZERO_TIME_OMNI 0 | |
2801 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_NUM_FIELDS 1 | |
2802 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INT_STATE_FID 0 | |
2803 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INT_STATE_SLC 1:0 | |
2804 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INT_STATE_WIDTH 2 | |
2805 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INT_STATE_INT_SLC 1:0 | |
2806 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INT_STATE_POSITION 0 | |
2807 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2808 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2809 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_22_INT_STATE_POR_VALUE 2'b00 | |
2810 | ||
2811 | //------------------------------------------------------- | |
2812 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_23 | |
2813 | //------------------------------------------------------- | |
2814 | ||
2815 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_HW_ADDR 27'b000000011000000001010010111 | |
2816 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_23_ADDR 30'b000000011000000001010010111000 | |
2817 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_23_HW_ADDR 27'b000000011100000001010010111 | |
2818 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_23_ADDR 30'b000000011100000001010010111000 | |
2819 | ||
2820 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_WIDTH 64 | |
2821 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_DEPTH 1 | |
2822 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_SLC 63:0 | |
2823 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INT_SLC 63:0 | |
2824 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_POSITION 0 | |
2825 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_LOW_ADDR_WIDTH 0 | |
2826 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_ADDR_RANGE 26:0 | |
2827 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2828 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2829 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2830 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2831 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2832 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2833 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2834 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2835 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
2836 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2837 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2838 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INTERNAL_REG 0 | |
2839 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_EXTERNAL_DECODE_REG 1 | |
2840 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_ZERO_TIME_OMNI 0 | |
2841 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_NUM_FIELDS 1 | |
2842 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INT_STATE_FID 0 | |
2843 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INT_STATE_SLC 1:0 | |
2844 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INT_STATE_WIDTH 2 | |
2845 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INT_STATE_INT_SLC 1:0 | |
2846 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INT_STATE_POSITION 0 | |
2847 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2848 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2849 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_23_INT_STATE_POR_VALUE 2'b00 | |
2850 | ||
2851 | //------------------------------------------------------- | |
2852 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_24 | |
2853 | //------------------------------------------------------- | |
2854 | ||
2855 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_HW_ADDR 27'b000000011000000001010011000 | |
2856 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_24_ADDR 30'b000000011000000001010011000000 | |
2857 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_24_HW_ADDR 27'b000000011100000001010011000 | |
2858 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_24_ADDR 30'b000000011100000001010011000000 | |
2859 | ||
2860 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_WIDTH 64 | |
2861 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_DEPTH 1 | |
2862 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_SLC 63:0 | |
2863 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INT_SLC 63:0 | |
2864 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_POSITION 0 | |
2865 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_LOW_ADDR_WIDTH 0 | |
2866 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_ADDR_RANGE 26:0 | |
2867 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2868 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2869 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2870 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2871 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2872 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2873 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2874 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2875 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
2876 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2877 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2878 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INTERNAL_REG 0 | |
2879 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_EXTERNAL_DECODE_REG 1 | |
2880 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_ZERO_TIME_OMNI 0 | |
2881 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_NUM_FIELDS 1 | |
2882 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INT_STATE_FID 0 | |
2883 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INT_STATE_SLC 1:0 | |
2884 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INT_STATE_WIDTH 2 | |
2885 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INT_STATE_INT_SLC 1:0 | |
2886 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INT_STATE_POSITION 0 | |
2887 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2888 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2889 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_24_INT_STATE_POR_VALUE 2'b00 | |
2890 | ||
2891 | //------------------------------------------------------- | |
2892 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_25 | |
2893 | //------------------------------------------------------- | |
2894 | ||
2895 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_HW_ADDR 27'b000000011000000001010011001 | |
2896 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_25_ADDR 30'b000000011000000001010011001000 | |
2897 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_25_HW_ADDR 27'b000000011100000001010011001 | |
2898 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_25_ADDR 30'b000000011100000001010011001000 | |
2899 | ||
2900 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_WIDTH 64 | |
2901 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_DEPTH 1 | |
2902 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_SLC 63:0 | |
2903 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INT_SLC 63:0 | |
2904 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_POSITION 0 | |
2905 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_LOW_ADDR_WIDTH 0 | |
2906 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_ADDR_RANGE 26:0 | |
2907 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2908 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2909 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2910 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2911 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2912 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2913 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2914 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2915 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
2916 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2917 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2918 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INTERNAL_REG 0 | |
2919 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_EXTERNAL_DECODE_REG 1 | |
2920 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_ZERO_TIME_OMNI 0 | |
2921 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_NUM_FIELDS 1 | |
2922 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INT_STATE_FID 0 | |
2923 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INT_STATE_SLC 1:0 | |
2924 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INT_STATE_WIDTH 2 | |
2925 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INT_STATE_INT_SLC 1:0 | |
2926 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INT_STATE_POSITION 0 | |
2927 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2928 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2929 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_25_INT_STATE_POR_VALUE 2'b00 | |
2930 | ||
2931 | //------------------------------------------------------- | |
2932 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_26 | |
2933 | //------------------------------------------------------- | |
2934 | ||
2935 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_HW_ADDR 27'b000000011000000001010011010 | |
2936 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_26_ADDR 30'b000000011000000001010011010000 | |
2937 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_26_HW_ADDR 27'b000000011100000001010011010 | |
2938 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_26_ADDR 30'b000000011100000001010011010000 | |
2939 | ||
2940 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_WIDTH 64 | |
2941 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_DEPTH 1 | |
2942 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_SLC 63:0 | |
2943 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INT_SLC 63:0 | |
2944 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_POSITION 0 | |
2945 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_LOW_ADDR_WIDTH 0 | |
2946 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_ADDR_RANGE 26:0 | |
2947 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2948 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2949 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2950 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2951 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2952 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2953 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2954 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2955 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
2956 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2957 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2958 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INTERNAL_REG 0 | |
2959 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_EXTERNAL_DECODE_REG 1 | |
2960 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_ZERO_TIME_OMNI 0 | |
2961 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_NUM_FIELDS 1 | |
2962 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INT_STATE_FID 0 | |
2963 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INT_STATE_SLC 1:0 | |
2964 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INT_STATE_WIDTH 2 | |
2965 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INT_STATE_INT_SLC 1:0 | |
2966 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INT_STATE_POSITION 0 | |
2967 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2968 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2969 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_26_INT_STATE_POR_VALUE 2'b00 | |
2970 | ||
2971 | //------------------------------------------------------- | |
2972 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_27 | |
2973 | //------------------------------------------------------- | |
2974 | ||
2975 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_HW_ADDR 27'b000000011000000001010011011 | |
2976 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_27_ADDR 30'b000000011000000001010011011000 | |
2977 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_27_HW_ADDR 27'b000000011100000001010011011 | |
2978 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_27_ADDR 30'b000000011100000001010011011000 | |
2979 | ||
2980 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_WIDTH 64 | |
2981 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_DEPTH 1 | |
2982 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_SLC 63:0 | |
2983 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INT_SLC 63:0 | |
2984 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_POSITION 0 | |
2985 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_LOW_ADDR_WIDTH 0 | |
2986 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_ADDR_RANGE 26:0 | |
2987 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2988 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2989 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2990 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2991 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2992 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2993 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2994 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2995 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
2996 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
2997 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
2998 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INTERNAL_REG 0 | |
2999 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_EXTERNAL_DECODE_REG 1 | |
3000 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_ZERO_TIME_OMNI 0 | |
3001 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_NUM_FIELDS 1 | |
3002 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INT_STATE_FID 0 | |
3003 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INT_STATE_SLC 1:0 | |
3004 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INT_STATE_WIDTH 2 | |
3005 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INT_STATE_INT_SLC 1:0 | |
3006 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INT_STATE_POSITION 0 | |
3007 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3008 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3009 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_27_INT_STATE_POR_VALUE 2'b00 | |
3010 | ||
3011 | //------------------------------------------------------- | |
3012 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_28 | |
3013 | //------------------------------------------------------- | |
3014 | ||
3015 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_HW_ADDR 27'b000000011000000001010011100 | |
3016 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_28_ADDR 30'b000000011000000001010011100000 | |
3017 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_28_HW_ADDR 27'b000000011100000001010011100 | |
3018 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_28_ADDR 30'b000000011100000001010011100000 | |
3019 | ||
3020 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_WIDTH 64 | |
3021 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_DEPTH 1 | |
3022 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_SLC 63:0 | |
3023 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INT_SLC 63:0 | |
3024 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_POSITION 0 | |
3025 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_LOW_ADDR_WIDTH 0 | |
3026 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_ADDR_RANGE 26:0 | |
3027 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3028 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3029 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3030 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3031 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3032 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3033 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3034 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3035 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3036 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3037 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3038 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INTERNAL_REG 0 | |
3039 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_EXTERNAL_DECODE_REG 1 | |
3040 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_ZERO_TIME_OMNI 0 | |
3041 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_NUM_FIELDS 1 | |
3042 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INT_STATE_FID 0 | |
3043 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INT_STATE_SLC 1:0 | |
3044 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INT_STATE_WIDTH 2 | |
3045 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INT_STATE_INT_SLC 1:0 | |
3046 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INT_STATE_POSITION 0 | |
3047 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3048 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3049 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_28_INT_STATE_POR_VALUE 2'b00 | |
3050 | ||
3051 | //------------------------------------------------------- | |
3052 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_29 | |
3053 | //------------------------------------------------------- | |
3054 | ||
3055 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_HW_ADDR 27'b000000011000000001010011101 | |
3056 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_29_ADDR 30'b000000011000000001010011101000 | |
3057 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_29_HW_ADDR 27'b000000011100000001010011101 | |
3058 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_29_ADDR 30'b000000011100000001010011101000 | |
3059 | ||
3060 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_WIDTH 64 | |
3061 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_DEPTH 1 | |
3062 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_SLC 63:0 | |
3063 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INT_SLC 63:0 | |
3064 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_POSITION 0 | |
3065 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_LOW_ADDR_WIDTH 0 | |
3066 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_ADDR_RANGE 26:0 | |
3067 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3068 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3069 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3070 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3071 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3072 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3073 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3074 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3075 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3076 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3077 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3078 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INTERNAL_REG 0 | |
3079 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_EXTERNAL_DECODE_REG 1 | |
3080 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_ZERO_TIME_OMNI 0 | |
3081 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_NUM_FIELDS 1 | |
3082 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INT_STATE_FID 0 | |
3083 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INT_STATE_SLC 1:0 | |
3084 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INT_STATE_WIDTH 2 | |
3085 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INT_STATE_INT_SLC 1:0 | |
3086 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INT_STATE_POSITION 0 | |
3087 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3088 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3089 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_29_INT_STATE_POR_VALUE 2'b00 | |
3090 | ||
3091 | //------------------------------------------------------- | |
3092 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_30 | |
3093 | //------------------------------------------------------- | |
3094 | ||
3095 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_HW_ADDR 27'b000000011000000001010011110 | |
3096 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_30_ADDR 30'b000000011000000001010011110000 | |
3097 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_30_HW_ADDR 27'b000000011100000001010011110 | |
3098 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_30_ADDR 30'b000000011100000001010011110000 | |
3099 | ||
3100 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_WIDTH 64 | |
3101 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_DEPTH 1 | |
3102 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_SLC 63:0 | |
3103 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INT_SLC 63:0 | |
3104 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_POSITION 0 | |
3105 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_LOW_ADDR_WIDTH 0 | |
3106 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_ADDR_RANGE 26:0 | |
3107 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3108 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3109 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3110 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3111 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3112 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3113 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3114 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3115 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3116 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3117 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3118 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INTERNAL_REG 0 | |
3119 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_EXTERNAL_DECODE_REG 1 | |
3120 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_ZERO_TIME_OMNI 0 | |
3121 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_NUM_FIELDS 1 | |
3122 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INT_STATE_FID 0 | |
3123 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INT_STATE_SLC 1:0 | |
3124 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INT_STATE_WIDTH 2 | |
3125 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INT_STATE_INT_SLC 1:0 | |
3126 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INT_STATE_POSITION 0 | |
3127 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3128 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3129 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_30_INT_STATE_POR_VALUE 2'b00 | |
3130 | ||
3131 | //------------------------------------------------------- | |
3132 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_31 | |
3133 | //------------------------------------------------------- | |
3134 | ||
3135 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_HW_ADDR 27'b000000011000000001010011111 | |
3136 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_31_ADDR 30'b000000011000000001010011111000 | |
3137 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_31_HW_ADDR 27'b000000011100000001010011111 | |
3138 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_31_ADDR 30'b000000011100000001010011111000 | |
3139 | ||
3140 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_WIDTH 64 | |
3141 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_DEPTH 1 | |
3142 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_SLC 63:0 | |
3143 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INT_SLC 63:0 | |
3144 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_POSITION 0 | |
3145 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_LOW_ADDR_WIDTH 0 | |
3146 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_ADDR_RANGE 26:0 | |
3147 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3148 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3149 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3150 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3151 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3152 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3153 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3154 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3155 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3156 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3157 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3158 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INTERNAL_REG 0 | |
3159 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_EXTERNAL_DECODE_REG 1 | |
3160 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_ZERO_TIME_OMNI 0 | |
3161 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_NUM_FIELDS 1 | |
3162 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INT_STATE_FID 0 | |
3163 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INT_STATE_SLC 1:0 | |
3164 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INT_STATE_WIDTH 2 | |
3165 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INT_STATE_INT_SLC 1:0 | |
3166 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INT_STATE_POSITION 0 | |
3167 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3168 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3169 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_31_INT_STATE_POR_VALUE 2'b00 | |
3170 | ||
3171 | //------------------------------------------------------- | |
3172 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_32 | |
3173 | //------------------------------------------------------- | |
3174 | ||
3175 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_HW_ADDR 27'b000000011000000001010100000 | |
3176 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_32_ADDR 30'b000000011000000001010100000000 | |
3177 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_32_HW_ADDR 27'b000000011100000001010100000 | |
3178 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_32_ADDR 30'b000000011100000001010100000000 | |
3179 | ||
3180 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_WIDTH 64 | |
3181 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_DEPTH 1 | |
3182 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_SLC 63:0 | |
3183 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INT_SLC 63:0 | |
3184 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_POSITION 0 | |
3185 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_LOW_ADDR_WIDTH 0 | |
3186 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_ADDR_RANGE 26:0 | |
3187 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3188 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3189 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3190 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3191 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3192 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3193 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3194 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3195 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3196 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3197 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3198 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INTERNAL_REG 0 | |
3199 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_EXTERNAL_DECODE_REG 1 | |
3200 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_ZERO_TIME_OMNI 0 | |
3201 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_NUM_FIELDS 1 | |
3202 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INT_STATE_FID 0 | |
3203 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INT_STATE_SLC 1:0 | |
3204 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INT_STATE_WIDTH 2 | |
3205 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INT_STATE_INT_SLC 1:0 | |
3206 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INT_STATE_POSITION 0 | |
3207 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3208 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3209 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_32_INT_STATE_POR_VALUE 2'b00 | |
3210 | ||
3211 | //------------------------------------------------------- | |
3212 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_33 | |
3213 | //------------------------------------------------------- | |
3214 | ||
3215 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_HW_ADDR 27'b000000011000000001010100001 | |
3216 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_33_ADDR 30'b000000011000000001010100001000 | |
3217 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_33_HW_ADDR 27'b000000011100000001010100001 | |
3218 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_33_ADDR 30'b000000011100000001010100001000 | |
3219 | ||
3220 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_WIDTH 64 | |
3221 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_DEPTH 1 | |
3222 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_SLC 63:0 | |
3223 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INT_SLC 63:0 | |
3224 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_POSITION 0 | |
3225 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_LOW_ADDR_WIDTH 0 | |
3226 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_ADDR_RANGE 26:0 | |
3227 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3228 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3229 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3230 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3231 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3232 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3233 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3234 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3235 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3236 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3237 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3238 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INTERNAL_REG 0 | |
3239 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_EXTERNAL_DECODE_REG 1 | |
3240 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_ZERO_TIME_OMNI 0 | |
3241 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_NUM_FIELDS 1 | |
3242 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INT_STATE_FID 0 | |
3243 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INT_STATE_SLC 1:0 | |
3244 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INT_STATE_WIDTH 2 | |
3245 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INT_STATE_INT_SLC 1:0 | |
3246 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INT_STATE_POSITION 0 | |
3247 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3248 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3249 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_33_INT_STATE_POR_VALUE 2'b00 | |
3250 | ||
3251 | //------------------------------------------------------- | |
3252 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_34 | |
3253 | //------------------------------------------------------- | |
3254 | ||
3255 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_HW_ADDR 27'b000000011000000001010100010 | |
3256 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_34_ADDR 30'b000000011000000001010100010000 | |
3257 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_34_HW_ADDR 27'b000000011100000001010100010 | |
3258 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_34_ADDR 30'b000000011100000001010100010000 | |
3259 | ||
3260 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_WIDTH 64 | |
3261 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_DEPTH 1 | |
3262 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_SLC 63:0 | |
3263 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INT_SLC 63:0 | |
3264 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_POSITION 0 | |
3265 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_LOW_ADDR_WIDTH 0 | |
3266 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_ADDR_RANGE 26:0 | |
3267 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3268 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3269 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3270 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3271 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3272 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3273 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3274 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3275 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3276 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3277 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3278 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INTERNAL_REG 0 | |
3279 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_EXTERNAL_DECODE_REG 1 | |
3280 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_ZERO_TIME_OMNI 0 | |
3281 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_NUM_FIELDS 1 | |
3282 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INT_STATE_FID 0 | |
3283 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INT_STATE_SLC 1:0 | |
3284 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INT_STATE_WIDTH 2 | |
3285 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INT_STATE_INT_SLC 1:0 | |
3286 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INT_STATE_POSITION 0 | |
3287 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3288 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3289 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_34_INT_STATE_POR_VALUE 2'b00 | |
3290 | ||
3291 | //------------------------------------------------------- | |
3292 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_35 | |
3293 | //------------------------------------------------------- | |
3294 | ||
3295 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_HW_ADDR 27'b000000011000000001010100011 | |
3296 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_35_ADDR 30'b000000011000000001010100011000 | |
3297 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_35_HW_ADDR 27'b000000011100000001010100011 | |
3298 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_35_ADDR 30'b000000011100000001010100011000 | |
3299 | ||
3300 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_WIDTH 64 | |
3301 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_DEPTH 1 | |
3302 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_SLC 63:0 | |
3303 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INT_SLC 63:0 | |
3304 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_POSITION 0 | |
3305 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_LOW_ADDR_WIDTH 0 | |
3306 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_ADDR_RANGE 26:0 | |
3307 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3308 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3309 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3310 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3311 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3312 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3313 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3314 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3315 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3316 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3317 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3318 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INTERNAL_REG 0 | |
3319 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_EXTERNAL_DECODE_REG 1 | |
3320 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_ZERO_TIME_OMNI 0 | |
3321 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_NUM_FIELDS 1 | |
3322 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INT_STATE_FID 0 | |
3323 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INT_STATE_SLC 1:0 | |
3324 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INT_STATE_WIDTH 2 | |
3325 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INT_STATE_INT_SLC 1:0 | |
3326 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INT_STATE_POSITION 0 | |
3327 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3328 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3329 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_35_INT_STATE_POR_VALUE 2'b00 | |
3330 | ||
3331 | //------------------------------------------------------- | |
3332 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_36 | |
3333 | //------------------------------------------------------- | |
3334 | ||
3335 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_HW_ADDR 27'b000000011000000001010100100 | |
3336 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_36_ADDR 30'b000000011000000001010100100000 | |
3337 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_36_HW_ADDR 27'b000000011100000001010100100 | |
3338 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_36_ADDR 30'b000000011100000001010100100000 | |
3339 | ||
3340 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_WIDTH 64 | |
3341 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_DEPTH 1 | |
3342 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_SLC 63:0 | |
3343 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INT_SLC 63:0 | |
3344 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_POSITION 0 | |
3345 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_LOW_ADDR_WIDTH 0 | |
3346 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_ADDR_RANGE 26:0 | |
3347 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3348 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3349 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3350 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3351 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3352 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3353 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3354 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3355 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3356 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3357 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3358 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INTERNAL_REG 0 | |
3359 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_EXTERNAL_DECODE_REG 1 | |
3360 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_ZERO_TIME_OMNI 0 | |
3361 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_NUM_FIELDS 1 | |
3362 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INT_STATE_FID 0 | |
3363 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INT_STATE_SLC 1:0 | |
3364 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INT_STATE_WIDTH 2 | |
3365 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INT_STATE_INT_SLC 1:0 | |
3366 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INT_STATE_POSITION 0 | |
3367 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3368 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3369 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_36_INT_STATE_POR_VALUE 2'b00 | |
3370 | ||
3371 | //------------------------------------------------------- | |
3372 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_37 | |
3373 | //------------------------------------------------------- | |
3374 | ||
3375 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_HW_ADDR 27'b000000011000000001010100101 | |
3376 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_37_ADDR 30'b000000011000000001010100101000 | |
3377 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_37_HW_ADDR 27'b000000011100000001010100101 | |
3378 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_37_ADDR 30'b000000011100000001010100101000 | |
3379 | ||
3380 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_WIDTH 64 | |
3381 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_DEPTH 1 | |
3382 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_SLC 63:0 | |
3383 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INT_SLC 63:0 | |
3384 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_POSITION 0 | |
3385 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_LOW_ADDR_WIDTH 0 | |
3386 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_ADDR_RANGE 26:0 | |
3387 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3388 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3389 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3390 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3391 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3392 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3393 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3394 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3395 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3396 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3397 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3398 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INTERNAL_REG 0 | |
3399 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_EXTERNAL_DECODE_REG 1 | |
3400 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_ZERO_TIME_OMNI 0 | |
3401 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_NUM_FIELDS 1 | |
3402 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INT_STATE_FID 0 | |
3403 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INT_STATE_SLC 1:0 | |
3404 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INT_STATE_WIDTH 2 | |
3405 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INT_STATE_INT_SLC 1:0 | |
3406 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INT_STATE_POSITION 0 | |
3407 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3408 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3409 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_37_INT_STATE_POR_VALUE 2'b00 | |
3410 | ||
3411 | //------------------------------------------------------- | |
3412 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_38 | |
3413 | //------------------------------------------------------- | |
3414 | ||
3415 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_HW_ADDR 27'b000000011000000001010100110 | |
3416 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_38_ADDR 30'b000000011000000001010100110000 | |
3417 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_38_HW_ADDR 27'b000000011100000001010100110 | |
3418 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_38_ADDR 30'b000000011100000001010100110000 | |
3419 | ||
3420 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_WIDTH 64 | |
3421 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_DEPTH 1 | |
3422 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_SLC 63:0 | |
3423 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INT_SLC 63:0 | |
3424 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_POSITION 0 | |
3425 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_LOW_ADDR_WIDTH 0 | |
3426 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_ADDR_RANGE 26:0 | |
3427 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3428 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3429 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3430 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3431 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3432 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3433 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3434 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3435 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3436 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3437 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3438 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INTERNAL_REG 0 | |
3439 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_EXTERNAL_DECODE_REG 1 | |
3440 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_ZERO_TIME_OMNI 0 | |
3441 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_NUM_FIELDS 1 | |
3442 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INT_STATE_FID 0 | |
3443 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INT_STATE_SLC 1:0 | |
3444 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INT_STATE_WIDTH 2 | |
3445 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INT_STATE_INT_SLC 1:0 | |
3446 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INT_STATE_POSITION 0 | |
3447 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3448 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3449 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_38_INT_STATE_POR_VALUE 2'b00 | |
3450 | ||
3451 | //------------------------------------------------------- | |
3452 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_39 | |
3453 | //------------------------------------------------------- | |
3454 | ||
3455 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_HW_ADDR 27'b000000011000000001010100111 | |
3456 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_39_ADDR 30'b000000011000000001010100111000 | |
3457 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_39_HW_ADDR 27'b000000011100000001010100111 | |
3458 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_39_ADDR 30'b000000011100000001010100111000 | |
3459 | ||
3460 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_WIDTH 64 | |
3461 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_DEPTH 1 | |
3462 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_SLC 63:0 | |
3463 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INT_SLC 63:0 | |
3464 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_POSITION 0 | |
3465 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_LOW_ADDR_WIDTH 0 | |
3466 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_ADDR_RANGE 26:0 | |
3467 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3468 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3469 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3470 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3471 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3472 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3473 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3474 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3475 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3476 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3477 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3478 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INTERNAL_REG 0 | |
3479 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_EXTERNAL_DECODE_REG 1 | |
3480 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_ZERO_TIME_OMNI 0 | |
3481 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_NUM_FIELDS 1 | |
3482 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INT_STATE_FID 0 | |
3483 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INT_STATE_SLC 1:0 | |
3484 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INT_STATE_WIDTH 2 | |
3485 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INT_STATE_INT_SLC 1:0 | |
3486 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INT_STATE_POSITION 0 | |
3487 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3488 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3489 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_39_INT_STATE_POR_VALUE 2'b00 | |
3490 | ||
3491 | //------------------------------------------------------- | |
3492 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_40 | |
3493 | //------------------------------------------------------- | |
3494 | ||
3495 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_HW_ADDR 27'b000000011000000001010101000 | |
3496 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_40_ADDR 30'b000000011000000001010101000000 | |
3497 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_40_HW_ADDR 27'b000000011100000001010101000 | |
3498 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_40_ADDR 30'b000000011100000001010101000000 | |
3499 | ||
3500 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_WIDTH 64 | |
3501 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_DEPTH 1 | |
3502 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_SLC 63:0 | |
3503 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INT_SLC 63:0 | |
3504 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_POSITION 0 | |
3505 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_LOW_ADDR_WIDTH 0 | |
3506 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_ADDR_RANGE 26:0 | |
3507 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3508 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3509 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3510 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3511 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3512 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3513 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3514 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3515 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3516 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3517 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3518 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INTERNAL_REG 0 | |
3519 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_EXTERNAL_DECODE_REG 1 | |
3520 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_ZERO_TIME_OMNI 0 | |
3521 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_NUM_FIELDS 1 | |
3522 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INT_STATE_FID 0 | |
3523 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INT_STATE_SLC 1:0 | |
3524 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INT_STATE_WIDTH 2 | |
3525 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INT_STATE_INT_SLC 1:0 | |
3526 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INT_STATE_POSITION 0 | |
3527 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3528 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3529 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_40_INT_STATE_POR_VALUE 2'b00 | |
3530 | ||
3531 | //------------------------------------------------------- | |
3532 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_41 | |
3533 | //------------------------------------------------------- | |
3534 | ||
3535 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_HW_ADDR 27'b000000011000000001010101001 | |
3536 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_41_ADDR 30'b000000011000000001010101001000 | |
3537 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_41_HW_ADDR 27'b000000011100000001010101001 | |
3538 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_41_ADDR 30'b000000011100000001010101001000 | |
3539 | ||
3540 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_WIDTH 64 | |
3541 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_DEPTH 1 | |
3542 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_SLC 63:0 | |
3543 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INT_SLC 63:0 | |
3544 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_POSITION 0 | |
3545 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_LOW_ADDR_WIDTH 0 | |
3546 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_ADDR_RANGE 26:0 | |
3547 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3548 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3549 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3550 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3551 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3552 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3553 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3554 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3555 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3556 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3557 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3558 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INTERNAL_REG 0 | |
3559 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_EXTERNAL_DECODE_REG 1 | |
3560 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_ZERO_TIME_OMNI 0 | |
3561 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_NUM_FIELDS 1 | |
3562 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INT_STATE_FID 0 | |
3563 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INT_STATE_SLC 1:0 | |
3564 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INT_STATE_WIDTH 2 | |
3565 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INT_STATE_INT_SLC 1:0 | |
3566 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INT_STATE_POSITION 0 | |
3567 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3568 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3569 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_41_INT_STATE_POR_VALUE 2'b00 | |
3570 | ||
3571 | //------------------------------------------------------- | |
3572 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_42 | |
3573 | //------------------------------------------------------- | |
3574 | ||
3575 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_HW_ADDR 27'b000000011000000001010101010 | |
3576 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_42_ADDR 30'b000000011000000001010101010000 | |
3577 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_42_HW_ADDR 27'b000000011100000001010101010 | |
3578 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_42_ADDR 30'b000000011100000001010101010000 | |
3579 | ||
3580 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_WIDTH 64 | |
3581 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_DEPTH 1 | |
3582 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_SLC 63:0 | |
3583 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INT_SLC 63:0 | |
3584 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_POSITION 0 | |
3585 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_LOW_ADDR_WIDTH 0 | |
3586 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_ADDR_RANGE 26:0 | |
3587 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3588 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3589 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3590 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3591 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3592 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3593 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3594 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3595 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3596 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3597 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3598 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INTERNAL_REG 0 | |
3599 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_EXTERNAL_DECODE_REG 1 | |
3600 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_ZERO_TIME_OMNI 0 | |
3601 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_NUM_FIELDS 1 | |
3602 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INT_STATE_FID 0 | |
3603 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INT_STATE_SLC 1:0 | |
3604 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INT_STATE_WIDTH 2 | |
3605 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INT_STATE_INT_SLC 1:0 | |
3606 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INT_STATE_POSITION 0 | |
3607 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3608 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3609 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_42_INT_STATE_POR_VALUE 2'b00 | |
3610 | ||
3611 | //------------------------------------------------------- | |
3612 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_43 | |
3613 | //------------------------------------------------------- | |
3614 | ||
3615 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_HW_ADDR 27'b000000011000000001010101011 | |
3616 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_43_ADDR 30'b000000011000000001010101011000 | |
3617 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_43_HW_ADDR 27'b000000011100000001010101011 | |
3618 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_43_ADDR 30'b000000011100000001010101011000 | |
3619 | ||
3620 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_WIDTH 64 | |
3621 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_DEPTH 1 | |
3622 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_SLC 63:0 | |
3623 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INT_SLC 63:0 | |
3624 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_POSITION 0 | |
3625 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_LOW_ADDR_WIDTH 0 | |
3626 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_ADDR_RANGE 26:0 | |
3627 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3628 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3629 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3630 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3631 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3632 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3633 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3634 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3635 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3636 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3637 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3638 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INTERNAL_REG 0 | |
3639 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_EXTERNAL_DECODE_REG 1 | |
3640 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_ZERO_TIME_OMNI 0 | |
3641 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_NUM_FIELDS 1 | |
3642 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INT_STATE_FID 0 | |
3643 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INT_STATE_SLC 1:0 | |
3644 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INT_STATE_WIDTH 2 | |
3645 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INT_STATE_INT_SLC 1:0 | |
3646 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INT_STATE_POSITION 0 | |
3647 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3648 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3649 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_43_INT_STATE_POR_VALUE 2'b00 | |
3650 | ||
3651 | //------------------------------------------------------- | |
3652 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_44 | |
3653 | //------------------------------------------------------- | |
3654 | ||
3655 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_HW_ADDR 27'b000000011000000001010101100 | |
3656 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_44_ADDR 30'b000000011000000001010101100000 | |
3657 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_44_HW_ADDR 27'b000000011100000001010101100 | |
3658 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_44_ADDR 30'b000000011100000001010101100000 | |
3659 | ||
3660 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_WIDTH 64 | |
3661 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_DEPTH 1 | |
3662 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_SLC 63:0 | |
3663 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INT_SLC 63:0 | |
3664 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_POSITION 0 | |
3665 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_LOW_ADDR_WIDTH 0 | |
3666 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_ADDR_RANGE 26:0 | |
3667 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3668 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3669 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3670 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3671 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3672 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3673 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3674 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3675 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3676 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3677 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3678 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INTERNAL_REG 0 | |
3679 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_EXTERNAL_DECODE_REG 1 | |
3680 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_ZERO_TIME_OMNI 0 | |
3681 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_NUM_FIELDS 1 | |
3682 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INT_STATE_FID 0 | |
3683 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INT_STATE_SLC 1:0 | |
3684 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INT_STATE_WIDTH 2 | |
3685 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INT_STATE_INT_SLC 1:0 | |
3686 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INT_STATE_POSITION 0 | |
3687 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3688 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3689 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_44_INT_STATE_POR_VALUE 2'b00 | |
3690 | ||
3691 | //------------------------------------------------------- | |
3692 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_45 | |
3693 | //------------------------------------------------------- | |
3694 | ||
3695 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_HW_ADDR 27'b000000011000000001010101101 | |
3696 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_45_ADDR 30'b000000011000000001010101101000 | |
3697 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_45_HW_ADDR 27'b000000011100000001010101101 | |
3698 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_45_ADDR 30'b000000011100000001010101101000 | |
3699 | ||
3700 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_WIDTH 64 | |
3701 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_DEPTH 1 | |
3702 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_SLC 63:0 | |
3703 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INT_SLC 63:0 | |
3704 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_POSITION 0 | |
3705 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_LOW_ADDR_WIDTH 0 | |
3706 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_ADDR_RANGE 26:0 | |
3707 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3708 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3709 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3710 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3711 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3712 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3713 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3714 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3715 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3716 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3717 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3718 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INTERNAL_REG 0 | |
3719 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_EXTERNAL_DECODE_REG 1 | |
3720 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_ZERO_TIME_OMNI 0 | |
3721 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_NUM_FIELDS 1 | |
3722 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INT_STATE_FID 0 | |
3723 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INT_STATE_SLC 1:0 | |
3724 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INT_STATE_WIDTH 2 | |
3725 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INT_STATE_INT_SLC 1:0 | |
3726 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INT_STATE_POSITION 0 | |
3727 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3728 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3729 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_45_INT_STATE_POR_VALUE 2'b00 | |
3730 | ||
3731 | //------------------------------------------------------- | |
3732 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_46 | |
3733 | //------------------------------------------------------- | |
3734 | ||
3735 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_HW_ADDR 27'b000000011000000001010101110 | |
3736 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_46_ADDR 30'b000000011000000001010101110000 | |
3737 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_46_HW_ADDR 27'b000000011100000001010101110 | |
3738 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_46_ADDR 30'b000000011100000001010101110000 | |
3739 | ||
3740 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_WIDTH 64 | |
3741 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_DEPTH 1 | |
3742 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_SLC 63:0 | |
3743 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INT_SLC 63:0 | |
3744 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_POSITION 0 | |
3745 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_LOW_ADDR_WIDTH 0 | |
3746 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_ADDR_RANGE 26:0 | |
3747 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3748 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3749 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3750 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3751 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3752 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3753 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3754 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3755 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3756 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3757 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3758 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INTERNAL_REG 0 | |
3759 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_EXTERNAL_DECODE_REG 1 | |
3760 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_ZERO_TIME_OMNI 0 | |
3761 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_NUM_FIELDS 1 | |
3762 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INT_STATE_FID 0 | |
3763 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INT_STATE_SLC 1:0 | |
3764 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INT_STATE_WIDTH 2 | |
3765 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INT_STATE_INT_SLC 1:0 | |
3766 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INT_STATE_POSITION 0 | |
3767 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3768 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3769 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_46_INT_STATE_POR_VALUE 2'b00 | |
3770 | ||
3771 | //------------------------------------------------------- | |
3772 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_47 | |
3773 | //------------------------------------------------------- | |
3774 | ||
3775 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_HW_ADDR 27'b000000011000000001010101111 | |
3776 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_47_ADDR 30'b000000011000000001010101111000 | |
3777 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_47_HW_ADDR 27'b000000011100000001010101111 | |
3778 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_47_ADDR 30'b000000011100000001010101111000 | |
3779 | ||
3780 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_WIDTH 64 | |
3781 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_DEPTH 1 | |
3782 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_SLC 63:0 | |
3783 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INT_SLC 63:0 | |
3784 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_POSITION 0 | |
3785 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_LOW_ADDR_WIDTH 0 | |
3786 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_ADDR_RANGE 26:0 | |
3787 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3788 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3789 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3790 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3791 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3792 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3793 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3794 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3795 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3796 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3797 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3798 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INTERNAL_REG 0 | |
3799 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_EXTERNAL_DECODE_REG 1 | |
3800 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_ZERO_TIME_OMNI 0 | |
3801 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_NUM_FIELDS 1 | |
3802 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INT_STATE_FID 0 | |
3803 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INT_STATE_SLC 1:0 | |
3804 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INT_STATE_WIDTH 2 | |
3805 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INT_STATE_INT_SLC 1:0 | |
3806 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INT_STATE_POSITION 0 | |
3807 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3808 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3809 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_47_INT_STATE_POR_VALUE 2'b00 | |
3810 | ||
3811 | //------------------------------------------------------- | |
3812 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_48 | |
3813 | //------------------------------------------------------- | |
3814 | ||
3815 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_HW_ADDR 27'b000000011000000001010110000 | |
3816 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_48_ADDR 30'b000000011000000001010110000000 | |
3817 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_48_HW_ADDR 27'b000000011100000001010110000 | |
3818 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_48_ADDR 30'b000000011100000001010110000000 | |
3819 | ||
3820 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_WIDTH 64 | |
3821 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_DEPTH 1 | |
3822 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_SLC 63:0 | |
3823 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INT_SLC 63:0 | |
3824 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_POSITION 0 | |
3825 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_LOW_ADDR_WIDTH 0 | |
3826 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_ADDR_RANGE 26:0 | |
3827 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3828 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3829 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3830 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3831 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3832 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3833 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3834 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3835 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3836 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3837 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3838 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INTERNAL_REG 0 | |
3839 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_EXTERNAL_DECODE_REG 1 | |
3840 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_ZERO_TIME_OMNI 0 | |
3841 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_NUM_FIELDS 1 | |
3842 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INT_STATE_FID 0 | |
3843 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INT_STATE_SLC 1:0 | |
3844 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INT_STATE_WIDTH 2 | |
3845 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INT_STATE_INT_SLC 1:0 | |
3846 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INT_STATE_POSITION 0 | |
3847 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3848 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3849 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_48_INT_STATE_POR_VALUE 2'b00 | |
3850 | ||
3851 | //------------------------------------------------------- | |
3852 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_49 | |
3853 | //------------------------------------------------------- | |
3854 | ||
3855 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_HW_ADDR 27'b000000011000000001010110001 | |
3856 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_49_ADDR 30'b000000011000000001010110001000 | |
3857 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_49_HW_ADDR 27'b000000011100000001010110001 | |
3858 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_49_ADDR 30'b000000011100000001010110001000 | |
3859 | ||
3860 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_WIDTH 64 | |
3861 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_DEPTH 1 | |
3862 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_SLC 63:0 | |
3863 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INT_SLC 63:0 | |
3864 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_POSITION 0 | |
3865 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_LOW_ADDR_WIDTH 0 | |
3866 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_ADDR_RANGE 26:0 | |
3867 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3868 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3869 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3870 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3871 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3872 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3873 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3874 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3875 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3876 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3877 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3878 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INTERNAL_REG 0 | |
3879 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_EXTERNAL_DECODE_REG 1 | |
3880 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_ZERO_TIME_OMNI 0 | |
3881 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_NUM_FIELDS 1 | |
3882 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INT_STATE_FID 0 | |
3883 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INT_STATE_SLC 1:0 | |
3884 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INT_STATE_WIDTH 2 | |
3885 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INT_STATE_INT_SLC 1:0 | |
3886 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INT_STATE_POSITION 0 | |
3887 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3888 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3889 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_49_INT_STATE_POR_VALUE 2'b00 | |
3890 | ||
3891 | //------------------------------------------------------- | |
3892 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_50 | |
3893 | //------------------------------------------------------- | |
3894 | ||
3895 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_HW_ADDR 27'b000000011000000001010110010 | |
3896 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_50_ADDR 30'b000000011000000001010110010000 | |
3897 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_50_HW_ADDR 27'b000000011100000001010110010 | |
3898 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_50_ADDR 30'b000000011100000001010110010000 | |
3899 | ||
3900 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_WIDTH 64 | |
3901 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_DEPTH 1 | |
3902 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_SLC 63:0 | |
3903 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INT_SLC 63:0 | |
3904 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_POSITION 0 | |
3905 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_LOW_ADDR_WIDTH 0 | |
3906 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_ADDR_RANGE 26:0 | |
3907 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3908 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3909 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3910 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3911 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3912 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3913 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3914 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3915 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3916 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3917 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3918 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INTERNAL_REG 0 | |
3919 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_EXTERNAL_DECODE_REG 1 | |
3920 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_ZERO_TIME_OMNI 0 | |
3921 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_NUM_FIELDS 1 | |
3922 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INT_STATE_FID 0 | |
3923 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INT_STATE_SLC 1:0 | |
3924 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INT_STATE_WIDTH 2 | |
3925 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INT_STATE_INT_SLC 1:0 | |
3926 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INT_STATE_POSITION 0 | |
3927 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3928 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3929 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_50_INT_STATE_POR_VALUE 2'b00 | |
3930 | ||
3931 | //------------------------------------------------------- | |
3932 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_51 | |
3933 | //------------------------------------------------------- | |
3934 | ||
3935 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_HW_ADDR 27'b000000011000000001010110011 | |
3936 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_51_ADDR 30'b000000011000000001010110011000 | |
3937 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_51_HW_ADDR 27'b000000011100000001010110011 | |
3938 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_51_ADDR 30'b000000011100000001010110011000 | |
3939 | ||
3940 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_WIDTH 64 | |
3941 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_DEPTH 1 | |
3942 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_SLC 63:0 | |
3943 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INT_SLC 63:0 | |
3944 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_POSITION 0 | |
3945 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_LOW_ADDR_WIDTH 0 | |
3946 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_ADDR_RANGE 26:0 | |
3947 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3948 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3949 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3950 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3951 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3952 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3953 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3954 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3955 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3956 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3957 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3958 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INTERNAL_REG 0 | |
3959 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_EXTERNAL_DECODE_REG 1 | |
3960 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_ZERO_TIME_OMNI 0 | |
3961 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_NUM_FIELDS 1 | |
3962 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INT_STATE_FID 0 | |
3963 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INT_STATE_SLC 1:0 | |
3964 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INT_STATE_WIDTH 2 | |
3965 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INT_STATE_INT_SLC 1:0 | |
3966 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INT_STATE_POSITION 0 | |
3967 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3968 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3969 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_51_INT_STATE_POR_VALUE 2'b00 | |
3970 | ||
3971 | //------------------------------------------------------- | |
3972 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_52 | |
3973 | //------------------------------------------------------- | |
3974 | ||
3975 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_HW_ADDR 27'b000000011000000001010110100 | |
3976 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_52_ADDR 30'b000000011000000001010110100000 | |
3977 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_52_HW_ADDR 27'b000000011100000001010110100 | |
3978 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_52_ADDR 30'b000000011100000001010110100000 | |
3979 | ||
3980 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_WIDTH 64 | |
3981 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_DEPTH 1 | |
3982 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_SLC 63:0 | |
3983 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INT_SLC 63:0 | |
3984 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_POSITION 0 | |
3985 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_LOW_ADDR_WIDTH 0 | |
3986 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_ADDR_RANGE 26:0 | |
3987 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3988 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3989 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3990 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3991 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3992 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3993 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3994 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3995 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
3996 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
3997 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
3998 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INTERNAL_REG 0 | |
3999 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_EXTERNAL_DECODE_REG 1 | |
4000 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_ZERO_TIME_OMNI 0 | |
4001 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_NUM_FIELDS 1 | |
4002 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INT_STATE_FID 0 | |
4003 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INT_STATE_SLC 1:0 | |
4004 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INT_STATE_WIDTH 2 | |
4005 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INT_STATE_INT_SLC 1:0 | |
4006 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INT_STATE_POSITION 0 | |
4007 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4008 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4009 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_52_INT_STATE_POR_VALUE 2'b00 | |
4010 | ||
4011 | //------------------------------------------------------- | |
4012 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_53 | |
4013 | //------------------------------------------------------- | |
4014 | ||
4015 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_HW_ADDR 27'b000000011000000001010110101 | |
4016 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_53_ADDR 30'b000000011000000001010110101000 | |
4017 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_53_HW_ADDR 27'b000000011100000001010110101 | |
4018 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_53_ADDR 30'b000000011100000001010110101000 | |
4019 | ||
4020 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_WIDTH 64 | |
4021 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_DEPTH 1 | |
4022 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_SLC 63:0 | |
4023 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INT_SLC 63:0 | |
4024 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_POSITION 0 | |
4025 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_LOW_ADDR_WIDTH 0 | |
4026 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_ADDR_RANGE 26:0 | |
4027 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4028 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4029 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4030 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4031 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4032 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4033 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4034 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4035 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
4036 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4037 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4038 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INTERNAL_REG 0 | |
4039 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_EXTERNAL_DECODE_REG 1 | |
4040 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_ZERO_TIME_OMNI 0 | |
4041 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_NUM_FIELDS 1 | |
4042 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INT_STATE_FID 0 | |
4043 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INT_STATE_SLC 1:0 | |
4044 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INT_STATE_WIDTH 2 | |
4045 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INT_STATE_INT_SLC 1:0 | |
4046 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INT_STATE_POSITION 0 | |
4047 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4048 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4049 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_53_INT_STATE_POR_VALUE 2'b00 | |
4050 | ||
4051 | //------------------------------------------------------- | |
4052 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_54 | |
4053 | //------------------------------------------------------- | |
4054 | ||
4055 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_HW_ADDR 27'b000000011000000001010110110 | |
4056 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_54_ADDR 30'b000000011000000001010110110000 | |
4057 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_54_HW_ADDR 27'b000000011100000001010110110 | |
4058 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_54_ADDR 30'b000000011100000001010110110000 | |
4059 | ||
4060 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_WIDTH 64 | |
4061 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_DEPTH 1 | |
4062 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_SLC 63:0 | |
4063 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INT_SLC 63:0 | |
4064 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_POSITION 0 | |
4065 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_LOW_ADDR_WIDTH 0 | |
4066 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_ADDR_RANGE 26:0 | |
4067 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4068 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4069 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4070 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4071 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4072 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4073 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4074 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4075 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
4076 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4077 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4078 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INTERNAL_REG 0 | |
4079 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_EXTERNAL_DECODE_REG 1 | |
4080 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_ZERO_TIME_OMNI 0 | |
4081 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_NUM_FIELDS 1 | |
4082 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INT_STATE_FID 0 | |
4083 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INT_STATE_SLC 1:0 | |
4084 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INT_STATE_WIDTH 2 | |
4085 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INT_STATE_INT_SLC 1:0 | |
4086 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INT_STATE_POSITION 0 | |
4087 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4088 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4089 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_54_INT_STATE_POR_VALUE 2'b00 | |
4090 | ||
4091 | //------------------------------------------------------- | |
4092 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_55 | |
4093 | //------------------------------------------------------- | |
4094 | ||
4095 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_HW_ADDR 27'b000000011000000001010110111 | |
4096 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_55_ADDR 30'b000000011000000001010110111000 | |
4097 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_55_HW_ADDR 27'b000000011100000001010110111 | |
4098 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_55_ADDR 30'b000000011100000001010110111000 | |
4099 | ||
4100 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_WIDTH 64 | |
4101 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_DEPTH 1 | |
4102 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_SLC 63:0 | |
4103 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INT_SLC 63:0 | |
4104 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_POSITION 0 | |
4105 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_LOW_ADDR_WIDTH 0 | |
4106 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_ADDR_RANGE 26:0 | |
4107 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4108 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4109 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4110 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4111 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4112 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4113 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4114 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4115 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
4116 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4117 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4118 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INTERNAL_REG 0 | |
4119 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_EXTERNAL_DECODE_REG 1 | |
4120 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_ZERO_TIME_OMNI 0 | |
4121 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_NUM_FIELDS 1 | |
4122 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INT_STATE_FID 0 | |
4123 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INT_STATE_SLC 1:0 | |
4124 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INT_STATE_WIDTH 2 | |
4125 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INT_STATE_INT_SLC 1:0 | |
4126 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INT_STATE_POSITION 0 | |
4127 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4128 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4129 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_55_INT_STATE_POR_VALUE 2'b00 | |
4130 | ||
4131 | //------------------------------------------------------- | |
4132 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_56 | |
4133 | //------------------------------------------------------- | |
4134 | ||
4135 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_HW_ADDR 27'b000000011000000001010111000 | |
4136 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_56_ADDR 30'b000000011000000001010111000000 | |
4137 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_56_HW_ADDR 27'b000000011100000001010111000 | |
4138 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_56_ADDR 30'b000000011100000001010111000000 | |
4139 | ||
4140 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_WIDTH 64 | |
4141 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_DEPTH 1 | |
4142 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_SLC 63:0 | |
4143 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INT_SLC 63:0 | |
4144 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_POSITION 0 | |
4145 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_LOW_ADDR_WIDTH 0 | |
4146 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_ADDR_RANGE 26:0 | |
4147 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4148 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4149 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4150 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4151 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4152 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4153 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4154 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4155 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
4156 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4157 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4158 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INTERNAL_REG 0 | |
4159 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_EXTERNAL_DECODE_REG 1 | |
4160 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_ZERO_TIME_OMNI 0 | |
4161 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_NUM_FIELDS 1 | |
4162 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INT_STATE_FID 0 | |
4163 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INT_STATE_SLC 1:0 | |
4164 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INT_STATE_WIDTH 2 | |
4165 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INT_STATE_INT_SLC 1:0 | |
4166 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INT_STATE_POSITION 0 | |
4167 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4168 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4169 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_56_INT_STATE_POR_VALUE 2'b00 | |
4170 | ||
4171 | //------------------------------------------------------- | |
4172 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_57 | |
4173 | //------------------------------------------------------- | |
4174 | ||
4175 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_HW_ADDR 27'b000000011000000001010111001 | |
4176 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_57_ADDR 30'b000000011000000001010111001000 | |
4177 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_57_HW_ADDR 27'b000000011100000001010111001 | |
4178 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_57_ADDR 30'b000000011100000001010111001000 | |
4179 | ||
4180 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_WIDTH 64 | |
4181 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_DEPTH 1 | |
4182 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_SLC 63:0 | |
4183 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INT_SLC 63:0 | |
4184 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_POSITION 0 | |
4185 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_LOW_ADDR_WIDTH 0 | |
4186 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_ADDR_RANGE 26:0 | |
4187 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4188 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4189 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4190 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4191 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4192 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4193 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4194 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4195 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
4196 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4197 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4198 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INTERNAL_REG 0 | |
4199 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_EXTERNAL_DECODE_REG 1 | |
4200 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_ZERO_TIME_OMNI 0 | |
4201 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_NUM_FIELDS 1 | |
4202 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INT_STATE_FID 0 | |
4203 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INT_STATE_SLC 1:0 | |
4204 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INT_STATE_WIDTH 2 | |
4205 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INT_STATE_INT_SLC 1:0 | |
4206 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INT_STATE_POSITION 0 | |
4207 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4208 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4209 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_57_INT_STATE_POR_VALUE 2'b00 | |
4210 | ||
4211 | //------------------------------------------------------- | |
4212 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_58 | |
4213 | //------------------------------------------------------- | |
4214 | ||
4215 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_HW_ADDR 27'b000000011000000001010111010 | |
4216 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_58_ADDR 30'b000000011000000001010111010000 | |
4217 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_58_HW_ADDR 27'b000000011100000001010111010 | |
4218 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_58_ADDR 30'b000000011100000001010111010000 | |
4219 | ||
4220 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_WIDTH 64 | |
4221 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_DEPTH 1 | |
4222 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_SLC 63:0 | |
4223 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INT_SLC 63:0 | |
4224 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_POSITION 0 | |
4225 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_LOW_ADDR_WIDTH 0 | |
4226 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_ADDR_RANGE 26:0 | |
4227 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4228 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4229 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4230 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4231 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4232 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4233 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4234 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4235 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
4236 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4237 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4238 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INTERNAL_REG 0 | |
4239 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_EXTERNAL_DECODE_REG 1 | |
4240 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_ZERO_TIME_OMNI 0 | |
4241 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_NUM_FIELDS 1 | |
4242 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INT_STATE_FID 0 | |
4243 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INT_STATE_SLC 1:0 | |
4244 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INT_STATE_WIDTH 2 | |
4245 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INT_STATE_INT_SLC 1:0 | |
4246 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INT_STATE_POSITION 0 | |
4247 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4248 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4249 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_58_INT_STATE_POR_VALUE 2'b00 | |
4250 | ||
4251 | //------------------------------------------------------- | |
4252 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_59 | |
4253 | //------------------------------------------------------- | |
4254 | ||
4255 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_HW_ADDR 27'b000000011000000001010111011 | |
4256 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_59_ADDR 30'b000000011000000001010111011000 | |
4257 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_59_HW_ADDR 27'b000000011100000001010111011 | |
4258 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_59_ADDR 30'b000000011100000001010111011000 | |
4259 | ||
4260 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_WIDTH 64 | |
4261 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_DEPTH 1 | |
4262 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_SLC 63:0 | |
4263 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INT_SLC 63:0 | |
4264 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_POSITION 0 | |
4265 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_LOW_ADDR_WIDTH 0 | |
4266 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_ADDR_RANGE 26:0 | |
4267 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4268 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4269 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4270 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4271 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4272 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4273 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4274 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4275 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
4276 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4277 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4278 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INTERNAL_REG 0 | |
4279 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_EXTERNAL_DECODE_REG 1 | |
4280 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_ZERO_TIME_OMNI 0 | |
4281 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_NUM_FIELDS 1 | |
4282 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INT_STATE_FID 0 | |
4283 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INT_STATE_SLC 1:0 | |
4284 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INT_STATE_WIDTH 2 | |
4285 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INT_STATE_INT_SLC 1:0 | |
4286 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INT_STATE_POSITION 0 | |
4287 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4288 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4289 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_59_INT_STATE_POR_VALUE 2'b00 | |
4290 | ||
4291 | //------------------------------------------------------- | |
4292 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_62 | |
4293 | //------------------------------------------------------- | |
4294 | ||
4295 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_HW_ADDR 27'b000000011000000001010111110 | |
4296 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_62_ADDR 30'b000000011000000001010111110000 | |
4297 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_62_HW_ADDR 27'b000000011100000001010111110 | |
4298 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_62_ADDR 30'b000000011100000001010111110000 | |
4299 | ||
4300 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_WIDTH 64 | |
4301 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_DEPTH 1 | |
4302 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_SLC 63:0 | |
4303 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INT_SLC 63:0 | |
4304 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_POSITION 0 | |
4305 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_LOW_ADDR_WIDTH 0 | |
4306 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_ADDR_RANGE 26:0 | |
4307 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4308 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4309 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4310 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4311 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4312 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4313 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4314 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4315 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
4316 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4317 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4318 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INTERNAL_REG 0 | |
4319 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_EXTERNAL_DECODE_REG 1 | |
4320 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_ZERO_TIME_OMNI 0 | |
4321 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_NUM_FIELDS 1 | |
4322 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INT_STATE_FID 0 | |
4323 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INT_STATE_SLC 1:0 | |
4324 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INT_STATE_WIDTH 2 | |
4325 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INT_STATE_INT_SLC 1:0 | |
4326 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INT_STATE_POSITION 0 | |
4327 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4328 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4329 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_62_INT_STATE_POR_VALUE 2'b00 | |
4330 | ||
4331 | //------------------------------------------------------- | |
4332 | //----- Variable definitions for register fire_dlc_imu_iss_csr_clr_int_reg_63 | |
4333 | //------------------------------------------------------- | |
4334 | ||
4335 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_HW_ADDR 27'b000000011000000001010111111 | |
4336 | `define FIRE_DLC_IMU_ISS_CSR_A_CLR_INT_REG_63_ADDR 30'b000000011000000001010111111000 | |
4337 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_63_HW_ADDR 27'b000000011100000001010111111 | |
4338 | `define FIRE_DLC_IMU_ISS_CSR_B_CLR_INT_REG_63_ADDR 30'b000000011100000001010111111000 | |
4339 | ||
4340 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_WIDTH 64 | |
4341 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_DEPTH 1 | |
4342 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_SLC 63:0 | |
4343 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INT_SLC 63:0 | |
4344 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_POSITION 0 | |
4345 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_LOW_ADDR_WIDTH 0 | |
4346 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_ADDR_RANGE 26:0 | |
4347 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4348 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4349 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4350 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4351 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4352 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4353 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4354 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4355 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100 | |
4356 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4357 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4358 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INTERNAL_REG 0 | |
4359 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_EXTERNAL_DECODE_REG 1 | |
4360 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_ZERO_TIME_OMNI 0 | |
4361 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_NUM_FIELDS 1 | |
4362 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INT_STATE_FID 0 | |
4363 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INT_STATE_SLC 1:0 | |
4364 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INT_STATE_WIDTH 2 | |
4365 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INT_STATE_INT_SLC 1:0 | |
4366 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INT_STATE_POSITION 0 | |
4367 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INT_STATE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4368 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INT_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011 | |
4369 | `define FIRE_DLC_IMU_ISS_CSR_CLR_INT_REG_63_INT_STATE_POR_VALUE 2'b00 | |
4370 | ||
4371 | //------------------------------------------------------- | |
4372 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_retry_timer | |
4373 | //------------------------------------------------------- | |
4374 | ||
4375 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_HW_ADDR 27'b000000011000000001101000000 | |
4376 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_RETRY_TIMER_ADDR 30'b000000011000000001101000000000 | |
4377 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_RETRY_TIMER_HW_ADDR 27'b000000011100000001101000000 | |
4378 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_RETRY_TIMER_ADDR 30'b000000011100000001101000000000 | |
4379 | ||
4380 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WIDTH 64 | |
4381 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_DEPTH 1 | |
4382 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_SLC 63:0 | |
4383 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_INT_SLC 63:0 | |
4384 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_POSITION 0 | |
4385 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LOW_ADDR_WIDTH 0 | |
4386 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_ADDR_RANGE 26:0 | |
4387 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_READ_MASK 64'b0000000000000000000000000000000000000001111111111111111111111111 | |
4388 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4389 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WRITE_MASK 64'b0000000000000000000000000000000000000001111111111111111111111111 | |
4390 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4391 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4392 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4393 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4394 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_RMASK 64'b0000000000000000000000000000000000000001111111111111111111111111 | |
4395 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111110000000000000000000000000 | |
4396 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4397 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4398 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_INTERNAL_REG 1 | |
4399 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_ZERO_TIME_OMNI 1 | |
4400 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_NUM_FIELDS 1 | |
4401 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_FID 0 | |
4402 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_SLC 24:0 | |
4403 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_WIDTH 25 | |
4404 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_INT_SLC 24:0 | |
4405 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_POSITION 0 | |
4406 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_FMASK 64'b0000000000000000000000000000000000000001111111111111111111111111 | |
4407 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4408 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_RETRY_TIMER_LIMIT_POR_VALUE 25'b0000000000000000000000000 | |
4409 | ||
4410 | //------------------------------------------------------- | |
4411 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_state_status_1 | |
4412 | //------------------------------------------------------- | |
4413 | ||
4414 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_HW_ADDR 27'b000000011000000001101000010 | |
4415 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_1_ADDR 30'b000000011000000001101000010000 | |
4416 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_STATE_STATUS_1_HW_ADDR 27'b000000011100000001101000010 | |
4417 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_STATE_STATUS_1_ADDR 30'b000000011100000001101000010000 | |
4418 | ||
4419 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_WIDTH 64 | |
4420 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_DEPTH 1 | |
4421 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_SLC 63:0 | |
4422 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_INT_SLC 63:0 | |
4423 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_POSITION 0 | |
4424 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_LOW_ADDR_WIDTH 0 | |
4425 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_ADDR_RANGE 26:0 | |
4426 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_READ_MASK 64'b1111111111111111111111110000000000000000000000000000000000000000 | |
4427 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_READ_ONLY_MASK 64'b1111111111111111111111110000000000000000000000000000000000000000 | |
4428 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4429 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4430 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4431 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4432 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4433 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_RMASK 64'b1111111111111111111111110000000000000000000000000000000000000000 | |
4434 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_RESERVED_BIT_MASK 64'b0000000000000000000000001111111111111111111111111111111111111111 | |
4435 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4436 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4437 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_INTERNAL_REG 0 | |
4438 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_EXTERNAL_DECODE_REG 1 | |
4439 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_ZERO_TIME_OMNI 0 | |
4440 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_NUM_FIELDS 1 | |
4441 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_STATE_FID 0 | |
4442 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_STATE_SLC 63:40 | |
4443 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_STATE_WIDTH 24 | |
4444 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_STATE_INT_SLC 23:0 | |
4445 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_STATE_POSITION 40 | |
4446 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_STATE_FMASK 64'b1111111111111111111111110000000000000000000000000000000000000000 | |
4447 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4448 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_1_STATE_POR_VALUE 24'b000000000000000000000000 | |
4449 | ||
4450 | //------------------------------------------------------- | |
4451 | //----- Variable definitions for register fire_dlc_imu_iss_csr_interrupt_state_status_2 | |
4452 | //------------------------------------------------------- | |
4453 | ||
4454 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_HW_ADDR 27'b000000011000000001101000011 | |
4455 | `define FIRE_DLC_IMU_ISS_CSR_A_INTERRUPT_STATE_STATUS_2_ADDR 30'b000000011000000001101000011000 | |
4456 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_STATE_STATUS_2_HW_ADDR 27'b000000011100000001101000011 | |
4457 | `define FIRE_DLC_IMU_ISS_CSR_B_INTERRUPT_STATE_STATUS_2_ADDR 30'b000000011100000001101000011000 | |
4458 | ||
4459 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_WIDTH 64 | |
4460 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_DEPTH 1 | |
4461 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_SLC 63:0 | |
4462 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_INT_SLC 63:0 | |
4463 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_POSITION 0 | |
4464 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_LOW_ADDR_WIDTH 0 | |
4465 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_ADDR_RANGE 26:0 | |
4466 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111 | |
4467 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_READ_ONLY_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111 | |
4468 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4469 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4470 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4471 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4472 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4473 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111111 | |
4474 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4475 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4476 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4477 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_INTERNAL_REG 0 | |
4478 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_EXTERNAL_DECODE_REG 1 | |
4479 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_ZERO_TIME_OMNI 0 | |
4480 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_NUM_FIELDS 1 | |
4481 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_STATE_FID 0 | |
4482 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_STATE_SLC 63:0 | |
4483 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_STATE_WIDTH 64 | |
4484 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_STATE_INT_SLC 63:0 | |
4485 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_STATE_POSITION 0 | |
4486 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_STATE_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111111 | |
4487 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_STATE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4488 | `define FIRE_DLC_IMU_ISS_CSR_INTERRUPT_STATE_STATUS_2_STATE_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
4489 | ||
4490 | ||
4491 | `endif |