Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_rds_msi_csrpipe_3.v

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// OpenSPARC T2 Processor File: dmu_imu_rds_msi_csrpipe_3.v
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module dmu_imu_rds_msi_csrpipe_3 
	(
	clk,
	rst_l,
	reg_in,
	reg_out,
	data0,
	data1,
	data2,
	sel0,
	sel1,
	sel2,
	out
	);

//====================================================================
//     Polarity declarations
//====================================================================
input  clk;  // Clock signal
input  rst_l;  // Reset signal
input  reg_in;  // Set to constant. 0: sel* non-reg  1: sel* reg
input  reg_out;  // Set to constant. 0: out non-reg   1: out registered
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] data0;  // Read data
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] data1;  // Read data
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] data2;  // Read data
input  sel0;  // Set to 1 if reg_in==0
input  sel1;  // Set to 1 if reg_in==0
input  sel2;  // Set to 1 if reg_in==0
output [`FIRE_CSRBUS_DATA_WIDTH-1:0] out;  // Read data out

//====================================================================
//     Type declarations
//====================================================================
wire clk;  // Clock signal
wire rst_l;  // Reset signal
wire reg_in;  // Set to constant. 0: sel* non-reg  1: sel* reg
wire reg_out;  // Set to constant. 0: out non-reg   1: out registered
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data0;  // Read data
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data1;  // Read data
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] data2;  // Read data
wire sel0;  // Set to 1 if reg_in==0
wire sel1;  // Set to 1 if reg_in==0
wire sel2;  // Set to 1 if reg_in==0
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] out;  // Read data out

//====================================================================
//     Local variables
//====================================================================
reg [`FIRE_CSRBUS_DATA_WIDTH-1:0] out_p1;
reg sel0_p1;
reg sel1_p1;
reg sel2_p1;

//====================================================================
//     Logic
//====================================================================
//select required ?
wire sel0_int=reg_in?sel0_p1:sel0;
wire sel1_int=reg_in?sel1_p1:sel1;
wire sel2_int=reg_in?sel2_p1:sel2;

//generate AND/OR
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] out_d = 
      {`FIRE_CSRBUS_DATA_WIDTH { sel0_int } } & data0 |
      {`FIRE_CSRBUS_DATA_WIDTH { sel1_int } } & data1 |
      {`FIRE_CSRBUS_DATA_WIDTH { sel2_int } } & data2;

//reg out or combo
assign out=reg_out?out_p1:out_d;

//pipe control/data
always @(posedge clk)
  begin
     if(~rst_l)
       begin
          sel0_p1<=1'b0;
          sel1_p1<=1'b0;
          sel2_p1<=1'b0;
          out_p1<=`FIRE_CSRBUS_DATA_WIDTH'b0;
        end
      else
        begin
          sel0_p1<=sel0;
          sel1_p1<=sel1;
          sel2_p1<=sel2;
          out_p1<=out_d;
        end
  end

endmodule // dmu_imu_rds_msi_csrpipe_3