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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_imu_rds_msi_defines.h
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AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: dmu_imu_rds_msi_defines.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`ifdef FIRE_DLC_IMU_RDS_MSI_DEFINES
39`else
40`define FIRE_DLC_IMU_RDS_MSI_DEFINES
41
42`define FIRE_DLC_IMU_RDS_MSI_CSRBUS_EXT_ADDR_WIDTH 8
43`define FIRE_DLC_IMU_RDS_MSI_CSRBUS_EXT_ADDR_RANGE 7:0
44
45`define FIRE_DLC_IMU_RDS_MSI_INSTANCE_ID_VALUE_A 1'h0
46`define FIRE_DLC_IMU_RDS_MSI_INSTANCE_ID_VALUE_B 1'h1
47
48//-------------------------------------------------------
49//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_msi_mapping
50//-------------------------------------------------------
51
52`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_HW_ADDR 27'b000000011000100000000000000
53`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_ADDR 30'b000000011000100000000000000000
54`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_MAPPING_HW_ADDR 27'b000000011100100000000000000
55`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_MAPPING_ADDR 30'b000000011100100000000000000000
56
57`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_WIDTH 64
58`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_DEPTH 256
59`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_SLC 63:0
60`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_INT_SLC 63:0
61`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_POSITION 0
62`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_LOW_ADDR_WIDTH 8
63`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_SEL_RANGE 7:0
64`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_ADDR_RANGE 26:8
65`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_READ_MASK 64'b1100000000000000000000000000000000000000000000000000000000111111
66`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_READ_ONLY_MASK 64'b0100000000000000000000000000000000000000000000000000000000000000
67`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_WRITE_MASK 64'b1000000000000000000000000000000000000000000000000000000000111111
68`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
69`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
70`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
71`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
72`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_RMASK 64'b1100000000000000000000000000000000000000000000000000000000111111
73`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_RESERVED_BIT_MASK 64'b0011111111111111111111111111111111111111111111111111111111000000
74`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_HW_LD_MASK 64'b0100000000000000000000000000000000000000000000000000000000000000
75`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
76`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_INTERNAL_REG 0
77`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EXTERNAL_DECODE_REG 0
78`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_ZERO_TIME_OMNI 0
79`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_NUM_FIELDS 3
80`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_FID 0
81`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_SLC 63:63
82`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_WIDTH 1
83`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_INT_SLC 0:0
84`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_POSITION 63
85`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000
86`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
87`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_POR_VALUE 1'b0
88`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_FID 1
89`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_SLC 62:62
90`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_WIDTH 1
91`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_INT_SLC 0:0
92`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_POSITION 62
93`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_FMASK 64'b0100000000000000000000000000000000000000000000000000000000000000
94`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_HW_LD_MASK 64'b0100000000000000000000000000000000000000000000000000000000000000
95`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_POR_VALUE 1'b0
96`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_FID 2
97`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_SLC 5:0
98`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_WIDTH 6
99`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_INT_SLC 5:0
100`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_POSITION 0
101`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000111111
102`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
103`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_POR_VALUE 6'b000000
104
105//-------------------------------------------------------
106//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_msi_clear_reg_rw1c_alias
107//-------------------------------------------------------
108
109`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_HW_ADDR 27'b000000011000101000000000000
110`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_ADDR 30'b000000011000101000000000000000
111`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1C_ALIAS_HW_ADDR 27'b000000011100101000000000000
112`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1C_ALIAS_ADDR 30'b000000011100101000000000000000
113
114`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_WIDTH 64
115`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_DEPTH 256
116`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_SLC 63:0
117`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_INT_SLC 63:0
118`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_POSITION 0
119`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_LOW_ADDR_WIDTH 8
120`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_SEL_RANGE 7:0
121`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_ADDR_RANGE 26:8
122`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_READ_MASK 64'b0100000000000000000000000000000000000000000000000000000000000000
123`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
124`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
125`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
126`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
127`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_CLEAR_MASK 64'b0100000000000000000000000000000000000000000000000000000000000000
128`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
129`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_RMASK 64'b0100000000000000000000000000000000000000000000000000000000000000
130`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_RESERVED_BIT_MASK 64'b1011111111111111111111111111111111111111111111111111111111111111
131`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
132`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
133`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_INTERNAL_REG 0
134`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EXTERNAL_DECODE_REG 0
135`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_ZERO_TIME_OMNI 0
136`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_NUM_FIELDS 1
137`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_FID 0
138`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_SLC 62:62
139`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_WIDTH 1
140`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_INT_SLC 0:0
141`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_POSITION 62
142`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_FMASK 64'b0100000000000000000000000000000000000000000000000000000000000000
143`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
144`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_POR_VALUE 1'b0
145
146//-------------------------------------------------------
147//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_msi_clear_reg_rw1s_alias
148//-------------------------------------------------------
149
150`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_HW_ADDR 27'b000000011000101000100000000
151`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_ADDR 30'b000000011000101000100000000000
152`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1S_ALIAS_HW_ADDR 27'b000000011100101000100000000
153`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1S_ALIAS_ADDR 30'b000000011100101000100000000000
154
155`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_WIDTH 64
156`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_DEPTH 256
157`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_SLC 63:0
158`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_INT_SLC 63:0
159`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_POSITION 0
160`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_LOW_ADDR_WIDTH 8
161`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_SEL_RANGE 7:0
162`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_ADDR_RANGE 26:8
163`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_READ_MASK 64'b0100000000000000000000000000000000000000000000000000000000000000
164`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
165`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
166`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
167`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_SET_MASK 64'b0100000000000000000000000000000000000000000000000000000000000000
168`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
169`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
170`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_RMASK 64'b0100000000000000000000000000000000000000000000000000000000000000
171`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_RESERVED_BIT_MASK 64'b1011111111111111111111111111111111111111111111111111111111111111
172`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
173`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
174`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_INTERNAL_REG 0
175`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EXTERNAL_DECODE_REG 0
176`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_ZERO_TIME_OMNI 0
177`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_NUM_FIELDS 1
178`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_FID 0
179`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_SLC 62:62
180`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_WIDTH 1
181`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_INT_SLC 0:0
182`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_POSITION 62
183`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_FMASK 64'b0100000000000000000000000000000000000000000000000000000000000000
184`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
185`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_POR_VALUE 1'b0
186
187//-------------------------------------------------------
188//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_int_mondo_data_0_reg
189//-------------------------------------------------------
190
191`define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_HW_ADDR 27'b000000011000101100000000000
192`define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_ADDR 30'b000000011000101100000000000000
193`define FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_0_REG_HW_ADDR 27'b000000011100101100000000000
194`define FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_0_REG_ADDR 30'b000000011100101100000000000000
195
196`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WIDTH 64
197`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DEPTH 1
198`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_SLC 63:0
199`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_INT_SLC 63:0
200`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_POSITION 0
201`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_LOW_ADDR_WIDTH 0
202`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_ADDR_RANGE 26:0
203`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111000000
204`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
205`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111000000
206`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
207`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
208`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
209`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
210`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_RMASK 64'b1111111111111111111111111111111111111111111111111111111111000000
211`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000111111
212`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
213`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
214`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_INTERNAL_REG 1
215`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_ZERO_TIME_OMNI 1
216`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_NUM_FIELDS 1
217`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_FID 0
218`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_SLC 63:6
219`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_WIDTH 58
220`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_INT_SLC 57:0
221`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_POSITION 6
222`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_FMASK 64'b1111111111111111111111111111111111111111111111111111111111000000
223`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
224`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_POR_VALUE 58'b0000000000000000000000000000000000000000000000000000000000
225
226//-------------------------------------------------------
227//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_int_mondo_data_1_reg
228//-------------------------------------------------------
229
230`define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_HW_ADDR 27'b000000011000101100000000001
231`define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_ADDR 30'b000000011000101100000000001000
232`define FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_1_REG_HW_ADDR 27'b000000011100101100000000001
233`define FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_1_REG_ADDR 30'b000000011100101100000000001000
234
235`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WIDTH 64
236`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DEPTH 1
237`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_SLC 63:0
238`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_INT_SLC 63:0
239`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_POSITION 0
240`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_LOW_ADDR_WIDTH 0
241`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_ADDR_RANGE 26:0
242`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
243`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
244`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
245`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
246`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
247`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
248`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
249`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
250`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
251`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
252`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
253`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_INTERNAL_REG 1
254`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_ZERO_TIME_OMNI 1
255`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_NUM_FIELDS 1
256`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_FID 0
257`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_SLC 63:0
258`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_WIDTH 64
259`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_INT_SLC 63:0
260`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_POSITION 0
261`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
262`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
263`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
264
265
266`endif
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