design/sys/iop/dmu/rtl/dmu_imu_rds_msi_defines.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_imu_rds_msi_defines.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
`ifdef FIRE_DLC_IMU_RDS_MSI_DEFINES
`else
`define FIRE_DLC_IMU_RDS_MSI_DEFINES

`define FIRE_DLC_IMU_RDS_MSI_CSRBUS_EXT_ADDR_WIDTH      8
`define FIRE_DLC_IMU_RDS_MSI_CSRBUS_EXT_ADDR_RANGE      7:0

`define FIRE_DLC_IMU_RDS_MSI_INSTANCE_ID_VALUE_A 1'h0
`define FIRE_DLC_IMU_RDS_MSI_INSTANCE_ID_VALUE_B 1'h1

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_msi_mapping
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_HW_ADDR  27'b000000011000100000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_MAPPING_ADDR     30'b000000011000100000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_MAPPING_HW_ADDR  27'b000000011100100000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_MAPPING_ADDR     30'b000000011100100000000000000000

`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_WIDTH      64
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_DEPTH      256
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_SLC        63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_INT_SLC    63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_POSITION   0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_LOW_ADDR_WIDTH     8
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_SEL_RANGE  7:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_ADDR_RANGE 26:8
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_READ_MASK  64'b1100000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_READ_ONLY_MASK     64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_WRITE_MASK 64'b1000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_RMASK      64'b1100000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_RESERVED_BIT_MASK  64'b0011111111111111111111111111111111111111111111111111111111000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_HW_LD_MASK 64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_INTERNAL_REG       0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EXTERNAL_DECODE_REG        0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_ZERO_TIME_OMNI     0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_NUM_FIELDS 3
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_FID      0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_SLC      63:63
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_WIDTH    1
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_INT_SLC  0:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_POSITION 63
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_FMASK    64'b1000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_V_POR_VALUE        1'b0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_FID 1
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_SLC 62:62
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_WIDTH       1
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_INT_SLC     0:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_POSITION    62
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_FMASK       64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_HW_LD_MASK  64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQWR_N_POR_VALUE   1'b0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_FID  2
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_SLC  5:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_WIDTH        6
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_INT_SLC      5:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_POSITION     0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_FMASK        64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_MAPPING_EQNUM_POR_VALUE    6'b000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_msi_clear_reg_rw1c_alias
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_HW_ADDR     27'b000000011000101000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1C_ALIAS_ADDR        30'b000000011000101000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1C_ALIAS_HW_ADDR     27'b000000011100101000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1C_ALIAS_ADDR        30'b000000011100101000000000000000

`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_WIDTH 64
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_DEPTH 256
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_SLC   63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_INT_SLC       63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_POSITION      0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_LOW_ADDR_WIDTH        8
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_SEL_RANGE     7:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_ADDR_RANGE    26:8
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_READ_MASK     64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_WRITE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_CLEAR_MASK    64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_RMASK 64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_RESERVED_BIT_MASK     64'b1011111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_INTERNAL_REG  0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EXTERNAL_DECODE_REG   0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_ZERO_TIME_OMNI        0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_NUM_FIELDS    1
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_FID    0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_SLC    62:62
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_WIDTH  1
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_INT_SLC        0:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_POSITION       62
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_FMASK  64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1C_ALIAS_EQWR_N_POR_VALUE      1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_msi_clear_reg_rw1s_alias
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_HW_ADDR     27'b000000011000101000100000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_A_MSI_CLEAR_REG_RW1S_ALIAS_ADDR        30'b000000011000101000100000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1S_ALIAS_HW_ADDR     27'b000000011100101000100000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_MSI_CLEAR_REG_RW1S_ALIAS_ADDR        30'b000000011100101000100000000000

`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_WIDTH 64
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_DEPTH 256
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_SLC   63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_INT_SLC       63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_POSITION      0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_LOW_ADDR_WIDTH        8
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_SEL_RANGE     7:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_ADDR_RANGE    26:8
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_READ_MASK     64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_WRITE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_SET_MASK      64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_RMASK 64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_RESERVED_BIT_MASK     64'b1011111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_INTERNAL_REG  0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EXTERNAL_DECODE_REG   0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_ZERO_TIME_OMNI        0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_NUM_FIELDS    1
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_FID    0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_SLC    62:62
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_WIDTH  1
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_INT_SLC        0:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_POSITION       62
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_FMASK  64'b0100000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_MSI_CLEAR_REG_RW1S_ALIAS_EQWR_N_POR_VALUE      1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_int_mondo_data_0_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_HW_ADDR 27'b000000011000101100000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_0_REG_ADDR    30'b000000011000101100000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_0_REG_HW_ADDR 27'b000000011100101100000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_0_REG_ADDR    30'b000000011100101100000000000000

`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WIDTH     64
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DEPTH     1
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_SLC       63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_INT_SLC   63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_POSITION  0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_LOW_ADDR_WIDTH    0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_ADDR_RANGE        26:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WRITE_MASK        64'b1111111111111111111111111111111111111111111111111111111111000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_RMASK     64'b1111111111111111111111111111111111111111111111111111111111000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_INTERNAL_REG      1
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_ZERO_TIME_OMNI    1
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_NUM_FIELDS        1
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_FID  0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_SLC  63:6
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_WIDTH        58
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_INT_SLC      57:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_POSITION     6
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_FMASK        64'b1111111111111111111111111111111111111111111111111111111111000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_0_REG_DATA_POR_VALUE    58'b0000000000000000000000000000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_msi_csr_int_mondo_data_1_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_HW_ADDR 27'b000000011000101100000000001
`define FIRE_DLC_IMU_RDS_MSI_CSR_A_INT_MONDO_DATA_1_REG_ADDR    30'b000000011000101100000000001000
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_1_REG_HW_ADDR 27'b000000011100101100000000001
`define FIRE_DLC_IMU_RDS_MSI_CSR_B_INT_MONDO_DATA_1_REG_ADDR    30'b000000011100101100000000001000

`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WIDTH     64
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DEPTH     1
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_SLC       63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_INT_SLC   63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_POSITION  0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_LOW_ADDR_WIDTH    0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_ADDR_RANGE        26:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WRITE_MASK        64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_RMASK     64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_INTERNAL_REG      1
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_ZERO_TIME_OMNI    1
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_NUM_FIELDS        1
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_FID  0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_SLC  63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_WIDTH        64
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_INT_SLC      63:0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_POSITION     0
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_FMASK        64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_MSI_CSR_INT_MONDO_DATA_1_REG_DATA_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000


`endif