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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu.h
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: dmu_mmu.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`define FIRE_DLC_MMU_PLS_DPTH 3
39
40`define FIRE_DLC_MMU_PAQ_DPTH 4
41`define FIRE_DLC_MMU_RDQ_DPTH 8
42`define FIRE_DLC_MMU_VAQ_DPTH 4
43
44`define FIRE_DLC_MMU_DBG_SEL_BITS 5:0
45`define FILE_DLC_MMU_TTE_CNT_BITS 2:0
46
47`define FIRE_DLC_MMU_TCB_PRF_SIZE 7
48`define FIRE_DLC_MMU_TCB_PRF_BITS `FIRE_DLC_MMU_TCB_PRF_SIZE - 1 : 0
49`define N2_PA_MSB 38
50
51// ****************************************************************************
52// TAG
53// ****************************************************************************
54`define FIRE_DLC_MMU_TAG_SIZE 64
55`define FIRE_DLC_MMU_TAG_BITS `FIRE_DLC_MMU_TAG_SIZE - 1 : 0
56`define FIRE_DLC_MMU_TAG_MEM_BITS 0 : `FIRE_DLC_MMU_TAG_SIZE - 1
57
58`define FIRE_DLC_MMU_TAG_PTR_SIZE 6
59`define FIRE_DLC_MMU_TAG_PTR_BITS `FIRE_DLC_MMU_TAG_PTR_SIZE - 1 : 0
60
61// ****************************************************************************
62// Translation Data Buffer
63// ****************************************************************************
64`define FIRE_DLC_MMU_TDB_PTR_SIZE `FIRE_DLC_MMU_TAG_PTR_SIZE + 3
65`define FIRE_DLC_MMU_TDB_PTR_BITS `FIRE_DLC_MMU_TDB_PTR_SIZE - 1 : 0
66
67// ****************************************************************************
68// Virtual and Physical Address
69// ****************************************************************************
70`define FIRE_DLC_MMU_VA_ADDR_BITS 63:2
71`define FIRE_DLC_MMU_VA_RQID_BITS 15:0
72`define FIRE_DLC_MMU_VA_TYPE_BITS 6:0
73
74`define FIRE_DLC_MMU_PA_ADDR_BITS `FIRE_PA_MSB:2
75`define FIRE_DLC_MMU_PA_TYPE_BITS 6:0
76
77// ****************************************************************************
78// CSR BITS
79// ****************************************************************************
80`define FIRE_DLC_MMU_CSR_CM_BITS 1:0
81`define FIRE_DLC_MMU_CSR_DS_BITS 2:0
82// `define FIRE_DLC_MMU_CSR_TB_BITS `FIRE_PA_MSB:13
83`define FIRE_DLC_MMU_CSR_TB_BITS 38:13
84`define FIRE_DLC_MMU_CSR_TS_BITS 3:0
85
86`define FIRE_DLC_MMU_CSR_ERR_SIZE 21
87`define FIRE_DLC_MMU_CSR_ERR_BITS `FIRE_DLC_MMU_CSR_ERR_SIZE - 1 : 0
88
89// ****************************************************************************
90// ERROR BITS
91// ****************************************************************************
92`define FIRE_DLC_MMU_PAB_ERR_BITS 2:0
93`define FIRE_DLC_MMU_RCB_ERR_BITS 2:0
94`define FIRE_DLC_MMU_TDC_ERR_BITS 2:0
95`define FIRE_DLC_MMU_VAB_ERR_BITS 1:0
96`define FIRE_DLC_MMU_VAB_VLD_BITS 2:0
97
98`define FIRE_DLC_MMU_PRM_ERR_BITS `FIRE_DLC_MMU_CSR_ERR_BITS
99`define FIRE_DLC_MMU_PRM_RSV_BITS 31 : `FIRE_DLC_MMU_CSR_ERR_SIZE
100`define FIRE_DLC_MMU_SCN_ERR_BITS `FIRE_DLC_MMU_CSR_ERR_SIZE + 31 : 32
101`define FIRE_DLC_MMU_SCN_RSV_BITS 63 : 32 + `FIRE_DLC_MMU_CSR_ERR_SIZE
102
103// ****************************************************************************
104// VIRTUAL TAG DATA (VTD)
105// ****************************************************************************
106`define FIRE_DLC_MMU_VTD_VLD_WDTH 1
107`define FIRE_DLC_MMU_VTD_VLD_LSB 0
108`define FIRE_DLC_MMU_VTD_VLD_MSB `FIRE_DLC_MMU_VTD_VLD_LSB + `FIRE_DLC_MMU_VTD_VLD_WDTH - 1
109`define FIRE_DLC_MMU_VTD_VLD_BITS `FIRE_DLC_MMU_VTD_VLD_MSB : `FIRE_DLC_MMU_VTD_VLD_LSB
110
111`define FIRE_DLC_MMU_VTD_VPN_WDTH 24
112`define FIRE_DLC_MMU_VTD_VPN_LSB 16
113`define FIRE_DLC_MMU_VTD_VPN_MSB `FIRE_DLC_MMU_VTD_VPN_LSB + `FIRE_DLC_MMU_VTD_VPN_WDTH - 1
114`define FIRE_DLC_MMU_VTD_VPN_BITS `FIRE_DLC_MMU_VTD_VPN_MSB : `FIRE_DLC_MMU_VTD_VPN_LSB
115
116`define FIRE_DLC_MMU_VTD_CNT_WDTH 17
117`define FIRE_DLC_MMU_VTD_CNT_LSB 40
118`define FIRE_DLC_MMU_VTD_CNT_MSB `FIRE_DLC_MMU_VTD_CNT_LSB + `FIRE_DLC_MMU_VTD_CNT_WDTH - 1
119`define FIRE_DLC_MMU_VTD_CNT_BITS `FIRE_DLC_MMU_VTD_CNT_MSB : `FIRE_DLC_MMU_VTD_CNT_LSB
120
121`define FIRE_DLC_MMU_VTD_IOTSBNO_WDTH 5
122`define FIRE_DLC_MMU_VTD_IOTSBNO_LSB 11
123`define FIRE_DLC_MMU_VTD_IOTSBNO_MSB `FIRE_DLC_MMU_VTD_IOTSBNO_LSB + `FIRE_DLC_MMU_VTD_IOTSBNO_WDTH - 1
124`define FIRE_DLC_MMU_VTD_IOTSBNO_BITS `FIRE_DLC_MMU_VTD_IOTSBNO_MSB : `FIRE_DLC_MMU_VTD_IOTSBNO_LSB
125
126`define FIRE_DLC_MMU_VTD_RZ0_LSB `FIRE_DLC_MMU_VTD_VLD_MSB + 1
127`define FIRE_DLC_MMU_VTD_RZ0_MSB `FIRE_DLC_MMU_VTD_IOTSBNO_LSB - 1
128`define FIRE_DLC_MMU_VTD_RZ0_BITS `FIRE_DLC_MMU_VTD_RZ0_MSB : `FIRE_DLC_MMU_VTD_RZ0_LSB
129
130`define FIRE_DLC_MMU_VTD_RZ1_LSB `FIRE_DLC_MMU_VTD_CNT_MSB + 1
131`define FIRE_DLC_MMU_VTD_RZ1_MSB 63
132`define FIRE_DLC_MMU_VTD_RZ1_BITS `FIRE_DLC_MMU_VTD_RZ1_MSB : `FIRE_DLC_MMU_VTD_RZ1_LSB
133
134// ****************************************************************************
135// VIRTUAL TAG RECORD (VTR)
136// ****************************************************************************
137`define FIRE_DLC_MMU_VTR_LSB 0
138
139`define FIRE_DLC_MMU_VTR_VLD_WDTH `FIRE_DLC_MMU_VTD_VLD_WDTH
140`define FIRE_DLC_MMU_VTR_VLD_LSB `FIRE_DLC_MMU_VTR_LSB
141`define FIRE_DLC_MMU_VTR_VLD_MSB `FIRE_DLC_MMU_VTR_VLD_LSB + `FIRE_DLC_MMU_VTR_VLD_WDTH - 1
142`define FIRE_DLC_MMU_VTR_VLD_BITS `FIRE_DLC_MMU_VTR_VLD_MSB : `FIRE_DLC_MMU_VTR_VLD_LSB
143
144`define FIRE_DLC_MMU_VTR_IOTSBNO_WDTH `FIRE_DLC_MMU_VTD_IOTSBNO_WDTH
145`define FIRE_DLC_MMU_VTR_IOTSBNO_LSB `FIRE_DLC_MMU_VTR_VLD_MSB + 1
146`define FIRE_DLC_MMU_VTR_IOTSBNO_MSB `FIRE_DLC_MMU_VTR_IOTSBNO_LSB + `FIRE_DLC_MMU_VTR_IOTSBNO_WDTH - 1
147`define FIRE_DLC_MMU_VTR_IOTSBNO_BITS `FIRE_DLC_MMU_VTR_IOTSBNO_MSB : `FIRE_DLC_MMU_VTR_IOTSBNO_LSB
148
149`define FIRE_DLC_MMU_VTR_VPN_WDTH `FIRE_DLC_MMU_VTD_VPN_WDTH
150`define FIRE_DLC_MMU_VTR_VPN_LSB `FIRE_DLC_MMU_VTR_IOTSBNO_MSB + 1
151`define FIRE_DLC_MMU_VTR_VPN_MSB `FIRE_DLC_MMU_VTR_VPN_LSB + `FIRE_DLC_MMU_VTR_VPN_WDTH - 1
152`define FIRE_DLC_MMU_VTR_VPN_BITS `FIRE_DLC_MMU_VTR_VPN_MSB : `FIRE_DLC_MMU_VTR_VPN_LSB
153
154`define FIRE_DLC_MMU_VTR_MSB `FIRE_DLC_MMU_VTR_VPN_MSB
155`define FIRE_DLC_MMU_VTR_BITS `FIRE_DLC_MMU_VTR_MSB : `FIRE_DLC_MMU_VTR_LSB
156`define FIRE_DLC_MMU_VTR_WDTH `FIRE_DLC_MMU_VTR_MSB + 1
157
158// ****************************************************************************
159// VIRTUAL TAG COUNT (VTC)
160// ****************************************************************************
161`define FIRE_DLC_MMU_VTC_WDTH `FIRE_DLC_MMU_VTD_CNT_WDTH
162`define FIRE_DLC_MMU_VTC_LSB 0
163`define FIRE_DLC_MMU_VTC_MSB `FIRE_DLC_MMU_VTC_LSB + `FIRE_DLC_MMU_VTC_WDTH - 1
164`define FIRE_DLC_MMU_VTC_BITS `FIRE_DLC_MMU_VTC_MSB : `FIRE_DLC_MMU_VTC_LSB
165
166// ****************************************************************************
167// PHYSICAL TAG DATA (PTD)
168// ****************************************************************************
169`define FIRE_DLC_MMU_PTD_VLD_WDTH 1
170`define FIRE_DLC_MMU_PTD_VLD_LSB 0
171`define FIRE_DLC_MMU_PTD_VLD_MSB `FIRE_DLC_MMU_PTD_VLD_LSB + `FIRE_DLC_MMU_PTD_VLD_WDTH - 1
172`define FIRE_DLC_MMU_PTD_VLD_BITS `FIRE_DLC_MMU_PTD_VLD_MSB : `FIRE_DLC_MMU_PTD_VLD_LSB
173
174`define FIRE_DLC_MMU_PTD_TAG_LSB 6
175`define FIRE_DLC_MMU_PTD_TAG_MSB `N2_PA_MSB
176`define FIRE_DLC_MMU_PTD_TAG_WDTH `FIRE_DLC_MMU_PTD_TAG_MSB - `FIRE_DLC_MMU_PTD_TAG_LSB + 1
177`define FIRE_DLC_MMU_PTD_TAG_BITS `FIRE_DLC_MMU_PTD_TAG_MSB : `FIRE_DLC_MMU_PTD_TAG_LSB
178`define FIRE_DLC_MMU_PTD_TAG_BITS_N2 `FIRE_PA_MSB : `FIRE_DLC_MMU_PTD_TAG_LSB
179
180`define FIRE_DLC_MMU_PTD_RZ0_LSB `FIRE_DLC_MMU_PTD_VLD_MSB + 1
181`define FIRE_DLC_MMU_PTD_RZ0_MSB `FIRE_DLC_MMU_PTD_TAG_LSB - 1
182`define FIRE_DLC_MMU_PTD_RZ0_BITS `FIRE_DLC_MMU_PTD_RZ0_MSB : `FIRE_DLC_MMU_PTD_RZ0_LSB
183
184`define FIRE_DLC_MMU_PTD_RZ1_LSB `FIRE_DLC_MMU_PTD_TAG_MSB + 1
185`define FIRE_DLC_MMU_PTD_RZ1_MSB 63
186`define FIRE_DLC_MMU_PTD_RZ1_BITS `FIRE_DLC_MMU_PTD_RZ1_MSB : `FIRE_DLC_MMU_PTD_RZ1_LSB
187
188// ****************************************************************************
189// TRANSLATION DATA DATA (TDD)
190// ****************************************************************************
191`define FIRE_DLC_MMU_TDD_VLD_WDTH 1
192`define FIRE_DLC_MMU_TDD_VLD_LSB 0
193`define FIRE_DLC_MMU_TDD_VLD_MSB `FIRE_DLC_MMU_TDD_VLD_LSB + `FIRE_DLC_MMU_TDD_VLD_WDTH - 1
194`define FIRE_DLC_MMU_TDD_VLD_BITS `FIRE_DLC_MMU_TDD_VLD_MSB : `FIRE_DLC_MMU_TDD_VLD_LSB
195
196`define FIRE_DLC_MMU_TDD_WRT_WDTH 1
197`define FIRE_DLC_MMU_TDD_WRT_LSB 1
198`define FIRE_DLC_MMU_TDD_WRT_MSB `FIRE_DLC_MMU_TDD_WRT_LSB + `FIRE_DLC_MMU_TDD_WRT_WDTH - 1
199`define FIRE_DLC_MMU_TDD_WRT_BITS `FIRE_DLC_MMU_TDD_WRT_MSB : `FIRE_DLC_MMU_TDD_WRT_LSB
200
201`define FIRE_DLC_MMU_TDD_KEYVLD_WDTH 1
202`define FIRE_DLC_MMU_TDD_KEYVLD_LSB 2
203`define FIRE_DLC_MMU_TDD_KEYVLD_MSB `FIRE_DLC_MMU_TDD_KEYVLD_LSB + `FIRE_DLC_MMU_TDD_KEYVLD_WDTH - 1
204`define FIRE_DLC_MMU_TDD_KEYVLD_BITS `FIRE_DLC_MMU_TDD_KEYVLD_MSB : `FIRE_DLC_MMU_TDD_KEYVLD_LSB
205
206`define FIRE_DLC_MMU_TDD_FNM_WDTH 3
207`define FIRE_DLC_MMU_TDD_FNM_LSB 3
208`define FIRE_DLC_MMU_TDD_FNM_MSB `FIRE_DLC_MMU_TDD_FNM_LSB + `FIRE_DLC_MMU_TDD_FNM_WDTH - 1
209`define FIRE_DLC_MMU_TDD_FNM_BITS `FIRE_DLC_MMU_TDD_FNM_MSB : `FIRE_DLC_MMU_TDD_FNM_LSB
210
211`define FIRE_DLC_MMU_TDD_PPN_WDTH `N2_PA_MSB - 12
212`define FIRE_DLC_MMU_TDD_PPN_LSB 13
213`define FIRE_DLC_MMU_TDD_PPN_MSB `FIRE_DLC_MMU_TDD_PPN_LSB + `FIRE_DLC_MMU_TDD_PPN_WDTH - 1
214`define FIRE_DLC_MMU_TDD_PPN_BITS `FIRE_DLC_MMU_TDD_PPN_MSB : `FIRE_DLC_MMU_TDD_PPN_LSB
215`define FIRE_DLC_MMU_TDD_PPN_BITS_N2 `FIRE_PA_MSB : `FIRE_DLC_MMU_TDD_PPN_LSB
216
217`define FIRE_DLC_MMU_TDD_KEY_WDTH 16
218`define FIRE_DLC_MMU_TDD_KEY_LSB 48
219`define FIRE_DLC_MMU_TDD_KEY_MSB `FIRE_DLC_MMU_TDD_KEY_LSB + `FIRE_DLC_MMU_TDD_KEY_WDTH - 1
220`define FIRE_DLC_MMU_TDD_KEY_BITS `FIRE_DLC_MMU_TDD_KEY_MSB : `FIRE_DLC_MMU_TDD_KEY_LSB
221
222`define FIRE_DLC_MMU_TDD_PAR_WDTH 4
223`define FIRE_DLC_MMU_TDD_PAR_LSB 44
224`define FIRE_DLC_MMU_TDD_PAR_MSB `FIRE_DLC_MMU_TDD_PAR_LSB + `FIRE_DLC_MMU_TDD_PAR_WDTH - 1
225`define FIRE_DLC_MMU_TDD_PAR_BITS `FIRE_DLC_MMU_TDD_PAR_MSB : `FIRE_DLC_MMU_TDD_PAR_LSB
226
227`define FIRE_DLC_MMU_TDD_RZ0_LSB `FIRE_DLC_MMU_TDD_FNM_MSB + 1
228`define FIRE_DLC_MMU_TDD_RZ0_MSB `FIRE_DLC_MMU_TDD_PPN_LSB - 1
229`define FIRE_DLC_MMU_TDD_RZ0_BITS `FIRE_DLC_MMU_TDD_RZ0_MSB : `FIRE_DLC_MMU_TDD_RZ0_LSB
230
231`define FIRE_DLC_MMU_TDD_RZ1_LSB `FIRE_DLC_MMU_TDD_PPN_MSB + 1
232`define FIRE_DLC_MMU_TDD_RZ1_MSB `FIRE_DLC_MMU_TDD_PAR_LSB - 1
233`define FIRE_DLC_MMU_TDD_RZ1_BITS `FIRE_DLC_MMU_TDD_RZ1_MSB : `FIRE_DLC_MMU_TDD_RZ1_LSB
234
235// ****************************************************************************
236// TRANSLATION DATA RECORD (TDR)
237// ****************************************************************************
238`define FIRE_DLC_MMU_TDR_LSB 0
239
240`define FIRE_DLC_MMU_TDR_VLD_WDTH `FIRE_DLC_MMU_TDD_VLD_WDTH
241`define FIRE_DLC_MMU_TDR_VLD_LSB `FIRE_DLC_MMU_TDR_LSB
242`define FIRE_DLC_MMU_TDR_VLD_MSB `FIRE_DLC_MMU_TDR_VLD_LSB + `FIRE_DLC_MMU_TDR_VLD_WDTH - 1
243`define FIRE_DLC_MMU_TDR_VLD_BITS `FIRE_DLC_MMU_TDR_VLD_MSB : `FIRE_DLC_MMU_TDR_VLD_LSB
244
245`define FIRE_DLC_MMU_TDR_WRT_WDTH `FIRE_DLC_MMU_TDD_WRT_WDTH
246`define FIRE_DLC_MMU_TDR_WRT_LSB `FIRE_DLC_MMU_TDR_VLD_MSB + 1
247`define FIRE_DLC_MMU_TDR_WRT_MSB `FIRE_DLC_MMU_TDR_WRT_LSB + `FIRE_DLC_MMU_TDR_WRT_WDTH - 1
248`define FIRE_DLC_MMU_TDR_WRT_BITS `FIRE_DLC_MMU_TDR_WRT_MSB : `FIRE_DLC_MMU_TDR_WRT_LSB
249
250`define FIRE_DLC_MMU_TDR_KEYVLD_WDTH `FIRE_DLC_MMU_TDD_KEYVLD_WDTH
251`define FIRE_DLC_MMU_TDR_KEYVLD_LSB `FIRE_DLC_MMU_TDR_WRT_MSB + 1
252`define FIRE_DLC_MMU_TDR_KEYVLD_MSB `FIRE_DLC_MMU_TDR_KEYVLD_LSB + `FIRE_DLC_MMU_TDR_KEYVLD_WDTH - 1
253`define FIRE_DLC_MMU_TDR_KEYVLD_BITS `FIRE_DLC_MMU_TDR_KEYVLD_MSB : `FIRE_DLC_MMU_TDR_KEYVLD_LSB
254
255`define FIRE_DLC_MMU_TDR_FNM_WDTH `FIRE_DLC_MMU_TDD_FNM_WDTH
256`define FIRE_DLC_MMU_TDR_FNM_LSB `FIRE_DLC_MMU_TDR_KEYVLD_MSB + 1
257`define FIRE_DLC_MMU_TDR_FNM_MSB `FIRE_DLC_MMU_TDR_FNM_LSB + `FIRE_DLC_MMU_TDR_FNM_WDTH - 1
258`define FIRE_DLC_MMU_TDR_FNM_BITS `FIRE_DLC_MMU_TDR_FNM_MSB : `FIRE_DLC_MMU_TDR_FNM_LSB
259
260`define FIRE_DLC_MMU_TDR_PPN_WDTH `FIRE_DLC_MMU_TDD_PPN_WDTH
261`define FIRE_DLC_MMU_TDR_PPN_LSB `FIRE_DLC_MMU_TDR_FNM_MSB + 1
262`define FIRE_DLC_MMU_TDR_PPN_MSB `FIRE_DLC_MMU_TDR_PPN_LSB + `FIRE_DLC_MMU_TDR_PPN_WDTH - 1
263`define FIRE_DLC_MMU_TDR_PPN_BITS `FIRE_DLC_MMU_TDR_PPN_MSB : `FIRE_DLC_MMU_TDR_PPN_LSB
264
265`define FIRE_DLC_MMU_TDR_KEY_WDTH `FIRE_DLC_MMU_TDD_KEY_WDTH
266`define FIRE_DLC_MMU_TDR_KEY_LSB `FIRE_DLC_MMU_TDR_PPN_MSB + 1
267`define FIRE_DLC_MMU_TDR_KEY_MSB `FIRE_DLC_MMU_TDR_KEY_LSB + `FIRE_DLC_MMU_TDR_KEY_WDTH - 1
268`define FIRE_DLC_MMU_TDR_KEY_BITS `FIRE_DLC_MMU_TDR_KEY_MSB : `FIRE_DLC_MMU_TDR_KEY_LSB
269
270`define FIRE_DLC_MMU_TDR_PAR_WDTH `FIRE_DLC_MMU_TDD_PAR_WDTH
271`define FIRE_DLC_MMU_TDR_PAR_LSB `FIRE_DLC_MMU_TDR_KEY_MSB + 1
272`define FIRE_DLC_MMU_TDR_PAR_MSB `FIRE_DLC_MMU_TDR_PAR_LSB + `FIRE_DLC_MMU_TDR_PAR_WDTH - 1
273`define FIRE_DLC_MMU_TDR_PAR_BITS `FIRE_DLC_MMU_TDR_PAR_MSB : `FIRE_DLC_MMU_TDR_PAR_LSB
274
275`define FIRE_DLC_MMU_TDR_DATA_BITS `FIRE_DLC_MMU_TDR_KEY_MSB : `FIRE_DLC_MMU_TDR_LSB
276
277`define FIRE_DLC_MMU_TDR_MSB `FIRE_DLC_MMU_TDR_PAR_MSB
278`define FIRE_DLC_MMU_TDR_BITS `FIRE_DLC_MMU_TDR_MSB : `FIRE_DLC_MMU_TDR_LSB
279`define FIRE_DLC_MMU_TDR_WDTH `FIRE_DLC_MMU_TDR_MSB + 1
280`define FIRE_DLC_MMU_TDR_MINUS_PAR_BITS `FIRE_DLC_MMU_TDR_KEY_MSB : `FIRE_DLC_MMU_TDR_LSB
281
282// ****************************************************************************
283// REMAINING DATA RECORD (RDR)
284// From IRB to RDQ to ORB
285// ****************************************************************************
286`define FIRE_DLC_MMU_RDR_LSB 0
287
288`define FIRE_DLC_MMU_RDR_STAG_WDTH `FIRE_DLC_SRM_SBDTAG_WDTH
289`define FIRE_DLC_MMU_RDR_STAG_LSB `FIRE_DLC_MMU_RDR_LSB
290`define FIRE_DLC_MMU_RDR_STAG_MSB `FIRE_DLC_MMU_RDR_STAG_LSB + `FIRE_DLC_MMU_RDR_STAG_WDTH - 1
291`define FIRE_DLC_MMU_RDR_STAG_BITS `FIRE_DLC_MMU_RDR_STAG_MSB : `FIRE_DLC_MMU_RDR_STAG_LSB
292
293`define FIRE_DLC_MMU_RDR_DPTR_WDTH `FIRE_DLC_SRM_DPTR_WDTH
294`define FIRE_DLC_MMU_RDR_DPTR_LSB `FIRE_DLC_MMU_RDR_STAG_MSB + 1
295`define FIRE_DLC_MMU_RDR_DPTR_MSB `FIRE_DLC_MMU_RDR_DPTR_LSB + `FIRE_DLC_MMU_RDR_DPTR_WDTH - 1
296`define FIRE_DLC_MMU_RDR_DPTR_BITS `FIRE_DLC_MMU_RDR_DPTR_MSB : `FIRE_DLC_MMU_RDR_DPTR_LSB
297
298`define FIRE_DLC_MMU_RDR_DWBE_WDTH `FIRE_DLC_SRM_DWBE_WDTH
299`define FIRE_DLC_MMU_RDR_DWBE_LSB `FIRE_DLC_MMU_RDR_DPTR_MSB + 1
300`define FIRE_DLC_MMU_RDR_DWBE_MSB `FIRE_DLC_MMU_RDR_DWBE_LSB + `FIRE_DLC_MMU_RDR_DWBE_WDTH - 1
301`define FIRE_DLC_MMU_RDR_DWBE_BITS `FIRE_DLC_MMU_RDR_DWBE_MSB : `FIRE_DLC_MMU_RDR_DWBE_LSB
302
303`define FIRE_DLC_MMU_RDR_LGTH_WDTH `FIRE_DLC_SRM_LEN_WDTH
304`define FIRE_DLC_MMU_RDR_LGTH_LSB `FIRE_DLC_MMU_RDR_DWBE_MSB + 1
305`define FIRE_DLC_MMU_RDR_LGTH_MSB `FIRE_DLC_MMU_RDR_LGTH_LSB + `FIRE_DLC_MMU_RDR_LGTH_WDTH - 1
306`define FIRE_DLC_MMU_RDR_LGTH_BITS `FIRE_DLC_MMU_RDR_LGTH_MSB : `FIRE_DLC_MMU_RDR_LGTH_LSB
307
308`define FIRE_DLC_MMU_RDR_MSB `FIRE_DLC_MMU_RDR_LGTH_MSB
309`define FIRE_DLC_MMU_RDR_BITS `FIRE_DLC_MMU_RDR_MSB : `FIRE_DLC_MMU_RDR_LSB
310`define FIRE_DLC_MMU_RDR_WDTH `FIRE_DLC_MMU_RDR_MSB + 1
311
312// ****************************************************************************
313// VIRTUAL ADDRESS RECORD (VAR)
314// From IRB to VAQ to VAB
315// ****************************************************************************
316`define FIRE_DLC_MMU_VAR_LSB 0
317
318`define FIRE_DLC_MMU_VAR_ADDR_WDTH `FIRE_DLC_SRM_ADDR_WDTH
319`define FIRE_DLC_MMU_VAR_ADDR_LSB `FIRE_DLC_MMU_VAR_LSB
320`define FIRE_DLC_MMU_VAR_ADDR_MSB `FIRE_DLC_MMU_VAR_ADDR_LSB + `FIRE_DLC_MMU_VAR_ADDR_WDTH - 1
321`define FIRE_DLC_MMU_VAR_ADDR_BITS `FIRE_DLC_MMU_VAR_ADDR_MSB : `FIRE_DLC_MMU_VAR_ADDR_LSB
322
323`define FIRE_DLC_MMU_VAR_RQID_WDTH `FIRE_DLC_SRM_REQID_WDTH
324`define FIRE_DLC_MMU_VAR_RQID_LSB `FIRE_DLC_MMU_VAR_ADDR_MSB + 1
325`define FIRE_DLC_MMU_VAR_RQID_MSB `FIRE_DLC_MMU_VAR_RQID_LSB + `FIRE_DLC_MMU_VAR_RQID_WDTH - 1
326`define FIRE_DLC_MMU_VAR_RQID_BITS `FIRE_DLC_MMU_VAR_RQID_MSB : `FIRE_DLC_MMU_VAR_RQID_LSB
327
328`define FIRE_DLC_MMU_VAR_TYPE_WDTH `FIRE_DLC_SRM_TYPE_WDTH
329`define FIRE_DLC_MMU_VAR_TYPE_LSB `FIRE_DLC_MMU_VAR_RQID_MSB + 1
330`define FIRE_DLC_MMU_VAR_TYPE_MSB `FIRE_DLC_MMU_VAR_TYPE_LSB + `FIRE_DLC_MMU_VAR_TYPE_WDTH - 1
331`define FIRE_DLC_MMU_VAR_TYPE_BITS `FIRE_DLC_MMU_VAR_TYPE_MSB : `FIRE_DLC_MMU_VAR_TYPE_LSB
332
333`define FIRE_DLC_MMU_VAR_MSB `FIRE_DLC_MMU_VAR_TYPE_MSB
334`define FIRE_DLC_MMU_VAR_BITS `FIRE_DLC_MMU_VAR_MSB : `FIRE_DLC_MMU_VAR_LSB
335`define FIRE_DLC_MMU_VAR_WDTH `FIRE_DLC_MMU_VAR_MSB + 1
336
337`define FIRE_DLC_MMU_VAR_IOTSB_BITS 4 : 0
338`define FIRE_DLC_MMU_IOTSB_BSPA_BITS 25 : 0
339
340// ****************************************************************************
341// PHYSICAL ADDRESS RECORD (PAR)
342// From PAB to PAQ to ORB
343// ****************************************************************************
344`define FIRE_DLC_MMU_PAR_LSB 0
345
346`define FIRE_DLC_MMU_PAR_ADDR_WDTH `FIRE_DLC_ISR_ADDR_WDTH
347`define FIRE_DLC_MMU_PAR_ADDR_LSB `FIRE_DLC_MMU_PAR_LSB
348`define FIRE_DLC_MMU_PAR_ADDR_MSB `FIRE_DLC_MMU_PAR_ADDR_LSB + `FIRE_DLC_MMU_PAR_ADDR_WDTH - 1
349`define FIRE_DLC_MMU_PAR_ADDR_BITS `FIRE_DLC_MMU_PAR_ADDR_MSB : `FIRE_DLC_MMU_PAR_ADDR_LSB
350
351`define FIRE_DLC_MMU_PAR_AERR_WDTH `FIRE_DLC_ISR_ADDRERR_WDTH
352`define FIRE_DLC_MMU_PAR_AERR_LSB `FIRE_DLC_MMU_PAR_ADDR_MSB + 1
353`define FIRE_DLC_MMU_PAR_AERR_MSB `FIRE_DLC_MMU_PAR_AERR_LSB + `FIRE_DLC_MMU_PAR_AERR_WDTH - 1
354`define FIRE_DLC_MMU_PAR_AERR_BITS `FIRE_DLC_MMU_PAR_AERR_MSB : `FIRE_DLC_MMU_PAR_AERR_LSB
355
356`define FIRE_DLC_MMU_PAR_TYPE_WDTH `FIRE_DLC_ISR_TYP_WDTH
357`define FIRE_DLC_MMU_PAR_TYPE_LSB `FIRE_DLC_MMU_PAR_AERR_MSB + 1
358`define FIRE_DLC_MMU_PAR_TYPE_MSB `FIRE_DLC_MMU_PAR_TYPE_LSB + `FIRE_DLC_MMU_PAR_TYPE_WDTH - 1
359`define FIRE_DLC_MMU_PAR_TYPE_BITS `FIRE_DLC_MMU_PAR_TYPE_MSB : `FIRE_DLC_MMU_PAR_TYPE_LSB
360
361`define FIRE_DLC_MMU_PAR_MSB `FIRE_DLC_MMU_PAR_TYPE_MSB
362`define FIRE_DLC_MMU_PAR_BITS `FIRE_DLC_MMU_PAR_MSB : `FIRE_DLC_MMU_PAR_LSB
363`define FIRE_DLC_MMU_PAR_WDTH `FIRE_DLC_MMU_PAR_MSB + 1
Full OpenSPARC design & verification tarball including full HDL.