design/sys/iop/dmu/rtl/dmu_mmu.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_mmu.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
`define FIRE_DLC_MMU_PLS_DPTH           3

`define FIRE_DLC_MMU_PAQ_DPTH           4
`define FIRE_DLC_MMU_RDQ_DPTH           8
`define FIRE_DLC_MMU_VAQ_DPTH           4

`define FIRE_DLC_MMU_DBG_SEL_BITS       5:0
`define FILE_DLC_MMU_TTE_CNT_BITS       2:0

`define FIRE_DLC_MMU_TCB_PRF_SIZE       7
`define FIRE_DLC_MMU_TCB_PRF_BITS       `FIRE_DLC_MMU_TCB_PRF_SIZE - 1 : 0
`define N2_PA_MSB                       38

// ****************************************************************************
// TAG
// ****************************************************************************
`define FIRE_DLC_MMU_TAG_SIZE           64
`define FIRE_DLC_MMU_TAG_BITS           `FIRE_DLC_MMU_TAG_SIZE - 1 : 0
`define FIRE_DLC_MMU_TAG_MEM_BITS       0 : `FIRE_DLC_MMU_TAG_SIZE - 1

`define FIRE_DLC_MMU_TAG_PTR_SIZE       6
`define FIRE_DLC_MMU_TAG_PTR_BITS       `FIRE_DLC_MMU_TAG_PTR_SIZE - 1 : 0

// ****************************************************************************
// Translation Data Buffer
// ****************************************************************************
`define FIRE_DLC_MMU_TDB_PTR_SIZE       `FIRE_DLC_MMU_TAG_PTR_SIZE + 3
`define FIRE_DLC_MMU_TDB_PTR_BITS       `FIRE_DLC_MMU_TDB_PTR_SIZE - 1 : 0

// ****************************************************************************
// Virtual and Physical Address
// ****************************************************************************
`define FIRE_DLC_MMU_VA_ADDR_BITS       63:2
`define FIRE_DLC_MMU_VA_RQID_BITS       15:0
`define FIRE_DLC_MMU_VA_TYPE_BITS       6:0

`define FIRE_DLC_MMU_PA_ADDR_BITS       `FIRE_PA_MSB:2
`define FIRE_DLC_MMU_PA_TYPE_BITS       6:0

// ****************************************************************************
// CSR BITS
// ****************************************************************************
`define FIRE_DLC_MMU_CSR_CM_BITS        1:0
`define FIRE_DLC_MMU_CSR_DS_BITS        2:0
// `define FIRE_DLC_MMU_CSR_TB_BITS     `FIRE_PA_MSB:13
`define FIRE_DLC_MMU_CSR_TB_BITS        38:13
`define FIRE_DLC_MMU_CSR_TS_BITS        3:0

`define FIRE_DLC_MMU_CSR_ERR_SIZE       21
`define FIRE_DLC_MMU_CSR_ERR_BITS       `FIRE_DLC_MMU_CSR_ERR_SIZE - 1 : 0

// ****************************************************************************
// ERROR BITS
// ****************************************************************************
`define FIRE_DLC_MMU_PAB_ERR_BITS       2:0
`define FIRE_DLC_MMU_RCB_ERR_BITS       2:0
`define FIRE_DLC_MMU_TDC_ERR_BITS       2:0
`define FIRE_DLC_MMU_VAB_ERR_BITS       1:0
`define FIRE_DLC_MMU_VAB_VLD_BITS       2:0

`define FIRE_DLC_MMU_PRM_ERR_BITS       `FIRE_DLC_MMU_CSR_ERR_BITS
`define FIRE_DLC_MMU_PRM_RSV_BITS       31 : `FIRE_DLC_MMU_CSR_ERR_SIZE
`define FIRE_DLC_MMU_SCN_ERR_BITS       `FIRE_DLC_MMU_CSR_ERR_SIZE + 31 : 32
`define FIRE_DLC_MMU_SCN_RSV_BITS       63 : 32 + `FIRE_DLC_MMU_CSR_ERR_SIZE

// ****************************************************************************
// VIRTUAL TAG DATA (VTD)
// ****************************************************************************
`define FIRE_DLC_MMU_VTD_VLD_WDTH       1
`define FIRE_DLC_MMU_VTD_VLD_LSB        0
`define FIRE_DLC_MMU_VTD_VLD_MSB        `FIRE_DLC_MMU_VTD_VLD_LSB + `FIRE_DLC_MMU_VTD_VLD_WDTH - 1
`define FIRE_DLC_MMU_VTD_VLD_BITS       `FIRE_DLC_MMU_VTD_VLD_MSB : `FIRE_DLC_MMU_VTD_VLD_LSB

`define FIRE_DLC_MMU_VTD_VPN_WDTH       24
`define FIRE_DLC_MMU_VTD_VPN_LSB        16
`define FIRE_DLC_MMU_VTD_VPN_MSB        `FIRE_DLC_MMU_VTD_VPN_LSB + `FIRE_DLC_MMU_VTD_VPN_WDTH - 1
`define FIRE_DLC_MMU_VTD_VPN_BITS       `FIRE_DLC_MMU_VTD_VPN_MSB : `FIRE_DLC_MMU_VTD_VPN_LSB

`define FIRE_DLC_MMU_VTD_CNT_WDTH       17
`define FIRE_DLC_MMU_VTD_CNT_LSB        40
`define FIRE_DLC_MMU_VTD_CNT_MSB        `FIRE_DLC_MMU_VTD_CNT_LSB + `FIRE_DLC_MMU_VTD_CNT_WDTH - 1
`define FIRE_DLC_MMU_VTD_CNT_BITS       `FIRE_DLC_MMU_VTD_CNT_MSB : `FIRE_DLC_MMU_VTD_CNT_LSB

`define FIRE_DLC_MMU_VTD_IOTSBNO_WDTH   5
`define FIRE_DLC_MMU_VTD_IOTSBNO_LSB    11
`define FIRE_DLC_MMU_VTD_IOTSBNO_MSB    `FIRE_DLC_MMU_VTD_IOTSBNO_LSB + `FIRE_DLC_MMU_VTD_IOTSBNO_WDTH - 1
`define FIRE_DLC_MMU_VTD_IOTSBNO_BITS   `FIRE_DLC_MMU_VTD_IOTSBNO_MSB : `FIRE_DLC_MMU_VTD_IOTSBNO_LSB

`define FIRE_DLC_MMU_VTD_RZ0_LSB        `FIRE_DLC_MMU_VTD_VLD_MSB + 1
`define FIRE_DLC_MMU_VTD_RZ0_MSB        `FIRE_DLC_MMU_VTD_IOTSBNO_LSB - 1
`define FIRE_DLC_MMU_VTD_RZ0_BITS       `FIRE_DLC_MMU_VTD_RZ0_MSB : `FIRE_DLC_MMU_VTD_RZ0_LSB

`define FIRE_DLC_MMU_VTD_RZ1_LSB        `FIRE_DLC_MMU_VTD_CNT_MSB + 1
`define FIRE_DLC_MMU_VTD_RZ1_MSB        63
`define FIRE_DLC_MMU_VTD_RZ1_BITS       `FIRE_DLC_MMU_VTD_RZ1_MSB : `FIRE_DLC_MMU_VTD_RZ1_LSB

// ****************************************************************************
// VIRTUAL TAG RECORD (VTR)
// ****************************************************************************
`define FIRE_DLC_MMU_VTR_LSB            0

`define FIRE_DLC_MMU_VTR_VLD_WDTH       `FIRE_DLC_MMU_VTD_VLD_WDTH
`define FIRE_DLC_MMU_VTR_VLD_LSB        `FIRE_DLC_MMU_VTR_LSB
`define FIRE_DLC_MMU_VTR_VLD_MSB        `FIRE_DLC_MMU_VTR_VLD_LSB + `FIRE_DLC_MMU_VTR_VLD_WDTH - 1
`define FIRE_DLC_MMU_VTR_VLD_BITS       `FIRE_DLC_MMU_VTR_VLD_MSB : `FIRE_DLC_MMU_VTR_VLD_LSB

`define FIRE_DLC_MMU_VTR_IOTSBNO_WDTH   `FIRE_DLC_MMU_VTD_IOTSBNO_WDTH
`define FIRE_DLC_MMU_VTR_IOTSBNO_LSB    `FIRE_DLC_MMU_VTR_VLD_MSB + 1
`define FIRE_DLC_MMU_VTR_IOTSBNO_MSB    `FIRE_DLC_MMU_VTR_IOTSBNO_LSB + `FIRE_DLC_MMU_VTR_IOTSBNO_WDTH - 1
`define FIRE_DLC_MMU_VTR_IOTSBNO_BITS   `FIRE_DLC_MMU_VTR_IOTSBNO_MSB : `FIRE_DLC_MMU_VTR_IOTSBNO_LSB

`define FIRE_DLC_MMU_VTR_VPN_WDTH       `FIRE_DLC_MMU_VTD_VPN_WDTH
`define FIRE_DLC_MMU_VTR_VPN_LSB        `FIRE_DLC_MMU_VTR_IOTSBNO_MSB + 1
`define FIRE_DLC_MMU_VTR_VPN_MSB        `FIRE_DLC_MMU_VTR_VPN_LSB + `FIRE_DLC_MMU_VTR_VPN_WDTH - 1
`define FIRE_DLC_MMU_VTR_VPN_BITS       `FIRE_DLC_MMU_VTR_VPN_MSB : `FIRE_DLC_MMU_VTR_VPN_LSB

`define FIRE_DLC_MMU_VTR_MSB            `FIRE_DLC_MMU_VTR_VPN_MSB
`define FIRE_DLC_MMU_VTR_BITS           `FIRE_DLC_MMU_VTR_MSB : `FIRE_DLC_MMU_VTR_LSB
`define FIRE_DLC_MMU_VTR_WDTH           `FIRE_DLC_MMU_VTR_MSB + 1

// ****************************************************************************
// VIRTUAL TAG COUNT (VTC)
// ****************************************************************************
`define FIRE_DLC_MMU_VTC_WDTH           `FIRE_DLC_MMU_VTD_CNT_WDTH
`define FIRE_DLC_MMU_VTC_LSB            0
`define FIRE_DLC_MMU_VTC_MSB            `FIRE_DLC_MMU_VTC_LSB + `FIRE_DLC_MMU_VTC_WDTH - 1
`define FIRE_DLC_MMU_VTC_BITS           `FIRE_DLC_MMU_VTC_MSB : `FIRE_DLC_MMU_VTC_LSB

// ****************************************************************************
// PHYSICAL TAG DATA (PTD)
// ****************************************************************************
`define FIRE_DLC_MMU_PTD_VLD_WDTH       1
`define FIRE_DLC_MMU_PTD_VLD_LSB        0
`define FIRE_DLC_MMU_PTD_VLD_MSB        `FIRE_DLC_MMU_PTD_VLD_LSB + `FIRE_DLC_MMU_PTD_VLD_WDTH - 1
`define FIRE_DLC_MMU_PTD_VLD_BITS       `FIRE_DLC_MMU_PTD_VLD_MSB : `FIRE_DLC_MMU_PTD_VLD_LSB

`define FIRE_DLC_MMU_PTD_TAG_LSB        6
`define FIRE_DLC_MMU_PTD_TAG_MSB        `N2_PA_MSB
`define FIRE_DLC_MMU_PTD_TAG_WDTH       `FIRE_DLC_MMU_PTD_TAG_MSB - `FIRE_DLC_MMU_PTD_TAG_LSB + 1
`define FIRE_DLC_MMU_PTD_TAG_BITS       `FIRE_DLC_MMU_PTD_TAG_MSB : `FIRE_DLC_MMU_PTD_TAG_LSB
`define FIRE_DLC_MMU_PTD_TAG_BITS_N2    `FIRE_PA_MSB              : `FIRE_DLC_MMU_PTD_TAG_LSB

`define FIRE_DLC_MMU_PTD_RZ0_LSB        `FIRE_DLC_MMU_PTD_VLD_MSB + 1
`define FIRE_DLC_MMU_PTD_RZ0_MSB        `FIRE_DLC_MMU_PTD_TAG_LSB - 1
`define FIRE_DLC_MMU_PTD_RZ0_BITS       `FIRE_DLC_MMU_PTD_RZ0_MSB : `FIRE_DLC_MMU_PTD_RZ0_LSB

`define FIRE_DLC_MMU_PTD_RZ1_LSB        `FIRE_DLC_MMU_PTD_TAG_MSB + 1
`define FIRE_DLC_MMU_PTD_RZ1_MSB        63
`define FIRE_DLC_MMU_PTD_RZ1_BITS       `FIRE_DLC_MMU_PTD_RZ1_MSB : `FIRE_DLC_MMU_PTD_RZ1_LSB

// ****************************************************************************
// TRANSLATION DATA DATA (TDD)
// ****************************************************************************
`define FIRE_DLC_MMU_TDD_VLD_WDTH       1
`define FIRE_DLC_MMU_TDD_VLD_LSB        0
`define FIRE_DLC_MMU_TDD_VLD_MSB        `FIRE_DLC_MMU_TDD_VLD_LSB + `FIRE_DLC_MMU_TDD_VLD_WDTH - 1
`define FIRE_DLC_MMU_TDD_VLD_BITS       `FIRE_DLC_MMU_TDD_VLD_MSB : `FIRE_DLC_MMU_TDD_VLD_LSB

`define FIRE_DLC_MMU_TDD_WRT_WDTH       1
`define FIRE_DLC_MMU_TDD_WRT_LSB        1
`define FIRE_DLC_MMU_TDD_WRT_MSB        `FIRE_DLC_MMU_TDD_WRT_LSB + `FIRE_DLC_MMU_TDD_WRT_WDTH - 1
`define FIRE_DLC_MMU_TDD_WRT_BITS       `FIRE_DLC_MMU_TDD_WRT_MSB : `FIRE_DLC_MMU_TDD_WRT_LSB

`define FIRE_DLC_MMU_TDD_KEYVLD_WDTH    1
`define FIRE_DLC_MMU_TDD_KEYVLD_LSB     2
`define FIRE_DLC_MMU_TDD_KEYVLD_MSB     `FIRE_DLC_MMU_TDD_KEYVLD_LSB + `FIRE_DLC_MMU_TDD_KEYVLD_WDTH - 1
`define FIRE_DLC_MMU_TDD_KEYVLD_BITS    `FIRE_DLC_MMU_TDD_KEYVLD_MSB : `FIRE_DLC_MMU_TDD_KEYVLD_LSB

`define FIRE_DLC_MMU_TDD_FNM_WDTH       3
`define FIRE_DLC_MMU_TDD_FNM_LSB        3
`define FIRE_DLC_MMU_TDD_FNM_MSB        `FIRE_DLC_MMU_TDD_FNM_LSB + `FIRE_DLC_MMU_TDD_FNM_WDTH - 1
`define FIRE_DLC_MMU_TDD_FNM_BITS       `FIRE_DLC_MMU_TDD_FNM_MSB : `FIRE_DLC_MMU_TDD_FNM_LSB

`define FIRE_DLC_MMU_TDD_PPN_WDTH       `N2_PA_MSB - 12
`define FIRE_DLC_MMU_TDD_PPN_LSB        13
`define FIRE_DLC_MMU_TDD_PPN_MSB        `FIRE_DLC_MMU_TDD_PPN_LSB + `FIRE_DLC_MMU_TDD_PPN_WDTH - 1
`define FIRE_DLC_MMU_TDD_PPN_BITS       `FIRE_DLC_MMU_TDD_PPN_MSB : `FIRE_DLC_MMU_TDD_PPN_LSB
`define FIRE_DLC_MMU_TDD_PPN_BITS_N2    `FIRE_PA_MSB : `FIRE_DLC_MMU_TDD_PPN_LSB

`define FIRE_DLC_MMU_TDD_KEY_WDTH       16
`define FIRE_DLC_MMU_TDD_KEY_LSB        48
`define FIRE_DLC_MMU_TDD_KEY_MSB        `FIRE_DLC_MMU_TDD_KEY_LSB + `FIRE_DLC_MMU_TDD_KEY_WDTH - 1
`define FIRE_DLC_MMU_TDD_KEY_BITS       `FIRE_DLC_MMU_TDD_KEY_MSB : `FIRE_DLC_MMU_TDD_KEY_LSB

`define FIRE_DLC_MMU_TDD_PAR_WDTH       4
`define FIRE_DLC_MMU_TDD_PAR_LSB        44
`define FIRE_DLC_MMU_TDD_PAR_MSB        `FIRE_DLC_MMU_TDD_PAR_LSB + `FIRE_DLC_MMU_TDD_PAR_WDTH - 1
`define FIRE_DLC_MMU_TDD_PAR_BITS       `FIRE_DLC_MMU_TDD_PAR_MSB : `FIRE_DLC_MMU_TDD_PAR_LSB

`define FIRE_DLC_MMU_TDD_RZ0_LSB        `FIRE_DLC_MMU_TDD_FNM_MSB + 1
`define FIRE_DLC_MMU_TDD_RZ0_MSB        `FIRE_DLC_MMU_TDD_PPN_LSB - 1
`define FIRE_DLC_MMU_TDD_RZ0_BITS       `FIRE_DLC_MMU_TDD_RZ0_MSB : `FIRE_DLC_MMU_TDD_RZ0_LSB

`define FIRE_DLC_MMU_TDD_RZ1_LSB        `FIRE_DLC_MMU_TDD_PPN_MSB + 1
`define FIRE_DLC_MMU_TDD_RZ1_MSB        `FIRE_DLC_MMU_TDD_PAR_LSB - 1
`define FIRE_DLC_MMU_TDD_RZ1_BITS       `FIRE_DLC_MMU_TDD_RZ1_MSB : `FIRE_DLC_MMU_TDD_RZ1_LSB

// ****************************************************************************
// TRANSLATION DATA RECORD (TDR)
// ****************************************************************************
`define FIRE_DLC_MMU_TDR_LSB            0

`define FIRE_DLC_MMU_TDR_VLD_WDTH       `FIRE_DLC_MMU_TDD_VLD_WDTH
`define FIRE_DLC_MMU_TDR_VLD_LSB        `FIRE_DLC_MMU_TDR_LSB
`define FIRE_DLC_MMU_TDR_VLD_MSB        `FIRE_DLC_MMU_TDR_VLD_LSB + `FIRE_DLC_MMU_TDR_VLD_WDTH - 1
`define FIRE_DLC_MMU_TDR_VLD_BITS       `FIRE_DLC_MMU_TDR_VLD_MSB : `FIRE_DLC_MMU_TDR_VLD_LSB

`define FIRE_DLC_MMU_TDR_WRT_WDTH       `FIRE_DLC_MMU_TDD_WRT_WDTH
`define FIRE_DLC_MMU_TDR_WRT_LSB        `FIRE_DLC_MMU_TDR_VLD_MSB + 1
`define FIRE_DLC_MMU_TDR_WRT_MSB        `FIRE_DLC_MMU_TDR_WRT_LSB + `FIRE_DLC_MMU_TDR_WRT_WDTH - 1
`define FIRE_DLC_MMU_TDR_WRT_BITS       `FIRE_DLC_MMU_TDR_WRT_MSB : `FIRE_DLC_MMU_TDR_WRT_LSB

`define FIRE_DLC_MMU_TDR_KEYVLD_WDTH    `FIRE_DLC_MMU_TDD_KEYVLD_WDTH
`define FIRE_DLC_MMU_TDR_KEYVLD_LSB     `FIRE_DLC_MMU_TDR_WRT_MSB + 1
`define FIRE_DLC_MMU_TDR_KEYVLD_MSB     `FIRE_DLC_MMU_TDR_KEYVLD_LSB + `FIRE_DLC_MMU_TDR_KEYVLD_WDTH - 1
`define FIRE_DLC_MMU_TDR_KEYVLD_BITS    `FIRE_DLC_MMU_TDR_KEYVLD_MSB : `FIRE_DLC_MMU_TDR_KEYVLD_LSB

`define FIRE_DLC_MMU_TDR_FNM_WDTH       `FIRE_DLC_MMU_TDD_FNM_WDTH
`define FIRE_DLC_MMU_TDR_FNM_LSB        `FIRE_DLC_MMU_TDR_KEYVLD_MSB + 1
`define FIRE_DLC_MMU_TDR_FNM_MSB        `FIRE_DLC_MMU_TDR_FNM_LSB + `FIRE_DLC_MMU_TDR_FNM_WDTH - 1
`define FIRE_DLC_MMU_TDR_FNM_BITS       `FIRE_DLC_MMU_TDR_FNM_MSB : `FIRE_DLC_MMU_TDR_FNM_LSB

`define FIRE_DLC_MMU_TDR_PPN_WDTH       `FIRE_DLC_MMU_TDD_PPN_WDTH
`define FIRE_DLC_MMU_TDR_PPN_LSB        `FIRE_DLC_MMU_TDR_FNM_MSB + 1
`define FIRE_DLC_MMU_TDR_PPN_MSB        `FIRE_DLC_MMU_TDR_PPN_LSB + `FIRE_DLC_MMU_TDR_PPN_WDTH - 1
`define FIRE_DLC_MMU_TDR_PPN_BITS       `FIRE_DLC_MMU_TDR_PPN_MSB : `FIRE_DLC_MMU_TDR_PPN_LSB

`define FIRE_DLC_MMU_TDR_KEY_WDTH       `FIRE_DLC_MMU_TDD_KEY_WDTH
`define FIRE_DLC_MMU_TDR_KEY_LSB        `FIRE_DLC_MMU_TDR_PPN_MSB + 1
`define FIRE_DLC_MMU_TDR_KEY_MSB        `FIRE_DLC_MMU_TDR_KEY_LSB + `FIRE_DLC_MMU_TDR_KEY_WDTH - 1
`define FIRE_DLC_MMU_TDR_KEY_BITS       `FIRE_DLC_MMU_TDR_KEY_MSB : `FIRE_DLC_MMU_TDR_KEY_LSB

`define FIRE_DLC_MMU_TDR_PAR_WDTH       `FIRE_DLC_MMU_TDD_PAR_WDTH
`define FIRE_DLC_MMU_TDR_PAR_LSB        `FIRE_DLC_MMU_TDR_KEY_MSB + 1
`define FIRE_DLC_MMU_TDR_PAR_MSB        `FIRE_DLC_MMU_TDR_PAR_LSB + `FIRE_DLC_MMU_TDR_PAR_WDTH - 1
`define FIRE_DLC_MMU_TDR_PAR_BITS       `FIRE_DLC_MMU_TDR_PAR_MSB : `FIRE_DLC_MMU_TDR_PAR_LSB

`define FIRE_DLC_MMU_TDR_DATA_BITS      `FIRE_DLC_MMU_TDR_KEY_MSB : `FIRE_DLC_MMU_TDR_LSB

`define FIRE_DLC_MMU_TDR_MSB            `FIRE_DLC_MMU_TDR_PAR_MSB
`define FIRE_DLC_MMU_TDR_BITS           `FIRE_DLC_MMU_TDR_MSB : `FIRE_DLC_MMU_TDR_LSB
`define FIRE_DLC_MMU_TDR_WDTH           `FIRE_DLC_MMU_TDR_MSB + 1
`define FIRE_DLC_MMU_TDR_MINUS_PAR_BITS `FIRE_DLC_MMU_TDR_KEY_MSB : `FIRE_DLC_MMU_TDR_LSB

// ****************************************************************************
// REMAINING DATA RECORD (RDR)
// From IRB to RDQ to ORB
// ****************************************************************************
`define FIRE_DLC_MMU_RDR_LSB            0

`define FIRE_DLC_MMU_RDR_STAG_WDTH      `FIRE_DLC_SRM_SBDTAG_WDTH
`define FIRE_DLC_MMU_RDR_STAG_LSB       `FIRE_DLC_MMU_RDR_LSB
`define FIRE_DLC_MMU_RDR_STAG_MSB       `FIRE_DLC_MMU_RDR_STAG_LSB + `FIRE_DLC_MMU_RDR_STAG_WDTH - 1
`define FIRE_DLC_MMU_RDR_STAG_BITS      `FIRE_DLC_MMU_RDR_STAG_MSB : `FIRE_DLC_MMU_RDR_STAG_LSB

`define FIRE_DLC_MMU_RDR_DPTR_WDTH      `FIRE_DLC_SRM_DPTR_WDTH
`define FIRE_DLC_MMU_RDR_DPTR_LSB       `FIRE_DLC_MMU_RDR_STAG_MSB + 1
`define FIRE_DLC_MMU_RDR_DPTR_MSB       `FIRE_DLC_MMU_RDR_DPTR_LSB + `FIRE_DLC_MMU_RDR_DPTR_WDTH - 1
`define FIRE_DLC_MMU_RDR_DPTR_BITS      `FIRE_DLC_MMU_RDR_DPTR_MSB : `FIRE_DLC_MMU_RDR_DPTR_LSB

`define FIRE_DLC_MMU_RDR_DWBE_WDTH      `FIRE_DLC_SRM_DWBE_WDTH
`define FIRE_DLC_MMU_RDR_DWBE_LSB       `FIRE_DLC_MMU_RDR_DPTR_MSB + 1
`define FIRE_DLC_MMU_RDR_DWBE_MSB       `FIRE_DLC_MMU_RDR_DWBE_LSB + `FIRE_DLC_MMU_RDR_DWBE_WDTH - 1
`define FIRE_DLC_MMU_RDR_DWBE_BITS      `FIRE_DLC_MMU_RDR_DWBE_MSB : `FIRE_DLC_MMU_RDR_DWBE_LSB

`define FIRE_DLC_MMU_RDR_LGTH_WDTH      `FIRE_DLC_SRM_LEN_WDTH
`define FIRE_DLC_MMU_RDR_LGTH_LSB       `FIRE_DLC_MMU_RDR_DWBE_MSB + 1
`define FIRE_DLC_MMU_RDR_LGTH_MSB       `FIRE_DLC_MMU_RDR_LGTH_LSB + `FIRE_DLC_MMU_RDR_LGTH_WDTH - 1
`define FIRE_DLC_MMU_RDR_LGTH_BITS      `FIRE_DLC_MMU_RDR_LGTH_MSB : `FIRE_DLC_MMU_RDR_LGTH_LSB

`define FIRE_DLC_MMU_RDR_MSB            `FIRE_DLC_MMU_RDR_LGTH_MSB
`define FIRE_DLC_MMU_RDR_BITS           `FIRE_DLC_MMU_RDR_MSB : `FIRE_DLC_MMU_RDR_LSB
`define FIRE_DLC_MMU_RDR_WDTH           `FIRE_DLC_MMU_RDR_MSB + 1

// ****************************************************************************
// VIRTUAL ADDRESS RECORD (VAR)
// From IRB to VAQ to VAB
// ****************************************************************************
`define FIRE_DLC_MMU_VAR_LSB            0

`define FIRE_DLC_MMU_VAR_ADDR_WDTH      `FIRE_DLC_SRM_ADDR_WDTH
`define FIRE_DLC_MMU_VAR_ADDR_LSB       `FIRE_DLC_MMU_VAR_LSB
`define FIRE_DLC_MMU_VAR_ADDR_MSB       `FIRE_DLC_MMU_VAR_ADDR_LSB + `FIRE_DLC_MMU_VAR_ADDR_WDTH - 1
`define FIRE_DLC_MMU_VAR_ADDR_BITS      `FIRE_DLC_MMU_VAR_ADDR_MSB : `FIRE_DLC_MMU_VAR_ADDR_LSB

`define FIRE_DLC_MMU_VAR_RQID_WDTH      `FIRE_DLC_SRM_REQID_WDTH
`define FIRE_DLC_MMU_VAR_RQID_LSB       `FIRE_DLC_MMU_VAR_ADDR_MSB + 1
`define FIRE_DLC_MMU_VAR_RQID_MSB       `FIRE_DLC_MMU_VAR_RQID_LSB + `FIRE_DLC_MMU_VAR_RQID_WDTH - 1
`define FIRE_DLC_MMU_VAR_RQID_BITS      `FIRE_DLC_MMU_VAR_RQID_MSB : `FIRE_DLC_MMU_VAR_RQID_LSB

`define FIRE_DLC_MMU_VAR_TYPE_WDTH      `FIRE_DLC_SRM_TYPE_WDTH
`define FIRE_DLC_MMU_VAR_TYPE_LSB       `FIRE_DLC_MMU_VAR_RQID_MSB + 1
`define FIRE_DLC_MMU_VAR_TYPE_MSB       `FIRE_DLC_MMU_VAR_TYPE_LSB + `FIRE_DLC_MMU_VAR_TYPE_WDTH - 1
`define FIRE_DLC_MMU_VAR_TYPE_BITS      `FIRE_DLC_MMU_VAR_TYPE_MSB : `FIRE_DLC_MMU_VAR_TYPE_LSB

`define FIRE_DLC_MMU_VAR_MSB            `FIRE_DLC_MMU_VAR_TYPE_MSB
`define FIRE_DLC_MMU_VAR_BITS           `FIRE_DLC_MMU_VAR_MSB : `FIRE_DLC_MMU_VAR_LSB
`define FIRE_DLC_MMU_VAR_WDTH           `FIRE_DLC_MMU_VAR_MSB + 1

`define FIRE_DLC_MMU_VAR_IOTSB_BITS     4  : 0
`define FIRE_DLC_MMU_IOTSB_BSPA_BITS    25 : 0

// ****************************************************************************
// PHYSICAL ADDRESS RECORD (PAR)
// From PAB to PAQ to ORB
// ****************************************************************************
`define FIRE_DLC_MMU_PAR_LSB            0

`define FIRE_DLC_MMU_PAR_ADDR_WDTH      `FIRE_DLC_ISR_ADDR_WDTH
`define FIRE_DLC_MMU_PAR_ADDR_LSB       `FIRE_DLC_MMU_PAR_LSB
`define FIRE_DLC_MMU_PAR_ADDR_MSB       `FIRE_DLC_MMU_PAR_ADDR_LSB + `FIRE_DLC_MMU_PAR_ADDR_WDTH - 1
`define FIRE_DLC_MMU_PAR_ADDR_BITS      `FIRE_DLC_MMU_PAR_ADDR_MSB : `FIRE_DLC_MMU_PAR_ADDR_LSB

`define FIRE_DLC_MMU_PAR_AERR_WDTH      `FIRE_DLC_ISR_ADDRERR_WDTH
`define FIRE_DLC_MMU_PAR_AERR_LSB       `FIRE_DLC_MMU_PAR_ADDR_MSB + 1
`define FIRE_DLC_MMU_PAR_AERR_MSB       `FIRE_DLC_MMU_PAR_AERR_LSB + `FIRE_DLC_MMU_PAR_AERR_WDTH - 1
`define FIRE_DLC_MMU_PAR_AERR_BITS      `FIRE_DLC_MMU_PAR_AERR_MSB : `FIRE_DLC_MMU_PAR_AERR_LSB

`define FIRE_DLC_MMU_PAR_TYPE_WDTH      `FIRE_DLC_ISR_TYP_WDTH
`define FIRE_DLC_MMU_PAR_TYPE_LSB       `FIRE_DLC_MMU_PAR_AERR_MSB + 1
`define FIRE_DLC_MMU_PAR_TYPE_MSB       `FIRE_DLC_MMU_PAR_TYPE_LSB + `FIRE_DLC_MMU_PAR_TYPE_WDTH - 1
`define FIRE_DLC_MMU_PAR_TYPE_BITS      `FIRE_DLC_MMU_PAR_TYPE_MSB : `FIRE_DLC_MMU_PAR_TYPE_LSB

`define FIRE_DLC_MMU_PAR_MSB            `FIRE_DLC_MMU_PAR_TYPE_MSB
`define FIRE_DLC_MMU_PAR_BITS           `FIRE_DLC_MMU_PAR_MSB : `FIRE_DLC_MMU_PAR_LSB
`define FIRE_DLC_MMU_PAR_WDTH           `FIRE_DLC_MMU_PAR_MSB + 1