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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / dmu / rtl / dmu_mmu_csr_defines.h
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: dmu_mmu_csr_defines.h
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38`ifdef FIRE_DLC_MMU_CSR_DEFINES
39`else
40`define FIRE_DLC_MMU_CSR_DEFINES
41
42`define FIRE_DLC_MMU_CSR_CSRBUS_EXT_ADDR_WIDTH 9
43`define FIRE_DLC_MMU_CSR_CSRBUS_EXT_ADDR_RANGE 8:0
44
45`define FIRE_DLC_MMU_CSR_INSTANCE_ID_VALUE_A 1'h0
46`define FIRE_DLC_MMU_CSR_INSTANCE_ID_VALUE_B 1'h1
47
48//-------------------------------------------------------
49//----- Variable definitions for register fire_dlc_mmu_csr_ctl
50//-------------------------------------------------------
51
52`define FIRE_DLC_MMU_CSR_A_CTL_HW_ADDR 27'b000000011001000000000000000
53`define FIRE_DLC_MMU_CSR_A_CTL_ADDR 30'b000000011001000000000000000000
54`define FIRE_DLC_MMU_CSR_B_CTL_HW_ADDR 27'b000000011101000000000000000
55`define FIRE_DLC_MMU_CSR_B_CTL_ADDR 30'b000000011101000000000000000000
56
57`define FIRE_DLC_MMU_CSR_CTL_WIDTH 64
58`define FIRE_DLC_MMU_CSR_CTL_DEPTH 1
59`define FIRE_DLC_MMU_CSR_CTL_SLC 63:0
60`define FIRE_DLC_MMU_CSR_CTL_INT_SLC 63:0
61`define FIRE_DLC_MMU_CSR_CTL_POSITION 0
62`define FIRE_DLC_MMU_CSR_CTL_LOW_ADDR_WIDTH 0
63`define FIRE_DLC_MMU_CSR_CTL_ADDR_RANGE 26:0
64`define FIRE_DLC_MMU_CSR_CTL_READ_MASK 64'b0000000000001111001111110000000000000000000011110001011100001111
65`define FIRE_DLC_MMU_CSR_CTL_READ_ONLY_MASK 64'b0000000000001111001111110000000000000000000000000000000000000000
66`define FIRE_DLC_MMU_CSR_CTL_WRITE_MASK 64'b0000000000000000000000000000000000000000000011110001011100001111
67`define FIRE_DLC_MMU_CSR_CTL_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
68`define FIRE_DLC_MMU_CSR_CTL_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
69`define FIRE_DLC_MMU_CSR_CTL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
70`define FIRE_DLC_MMU_CSR_CTL_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
71`define FIRE_DLC_MMU_CSR_CTL_RMASK 64'b0000000000001111001111110000000000000000000011110001011100001111
72`define FIRE_DLC_MMU_CSR_CTL_RESERVED_BIT_MASK 64'b1111111111110000110000001111111111111111111100001110100011110000
73`define FIRE_DLC_MMU_CSR_CTL_HW_LD_MASK 64'b0000000000001111001111110000000000000000000000000000000000000000
74`define FIRE_DLC_MMU_CSR_CTL_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
75`define FIRE_DLC_MMU_CSR_CTL_INTERNAL_REG 1
76`define FIRE_DLC_MMU_CSR_CTL_ZERO_TIME_OMNI 1
77`define FIRE_DLC_MMU_CSR_CTL_NUM_FIELDS 14
78`define FIRE_DLC_MMU_CSR_CTL_SPARES_FID 0
79`define FIRE_DLC_MMU_CSR_CTL_SPARES_SLC 51:48
80`define FIRE_DLC_MMU_CSR_CTL_SPARES_WIDTH 4
81`define FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC 3:0
82`define FIRE_DLC_MMU_CSR_CTL_SPARES_POSITION 48
83`define FIRE_DLC_MMU_CSR_CTL_SPARES_FMASK 64'b0000000000001111000000000000000000000000000000000000000000000000
84`define FIRE_DLC_MMU_CSR_CTL_SPARES_HW_LD_MASK 64'b0000000000001111000000000000000000000000000000000000000000000000
85`define FIRE_DLC_MMU_CSR_CTL_SPARES_POR_VALUE 4'b0000
86`define FIRE_DLC_MMU_CSR_CTL_PAQ_FID 1
87`define FIRE_DLC_MMU_CSR_CTL_PAQ_SLC 45:45
88`define FIRE_DLC_MMU_CSR_CTL_PAQ_WIDTH 1
89`define FIRE_DLC_MMU_CSR_CTL_PAQ_INT_SLC 0:0
90`define FIRE_DLC_MMU_CSR_CTL_PAQ_POSITION 45
91`define FIRE_DLC_MMU_CSR_CTL_PAQ_FMASK 64'b0000000000000000001000000000000000000000000000000000000000000000
92`define FIRE_DLC_MMU_CSR_CTL_PAQ_HW_LD_MASK 64'b0000000000000000001000000000000000000000000000000000000000000000
93`define FIRE_DLC_MMU_CSR_CTL_PAQ_POR_VALUE 1'b0
94`define FIRE_DLC_MMU_CSR_CTL_VAQ_FID 2
95`define FIRE_DLC_MMU_CSR_CTL_VAQ_SLC 44:44
96`define FIRE_DLC_MMU_CSR_CTL_VAQ_WIDTH 1
97`define FIRE_DLC_MMU_CSR_CTL_VAQ_INT_SLC 0:0
98`define FIRE_DLC_MMU_CSR_CTL_VAQ_POSITION 44
99`define FIRE_DLC_MMU_CSR_CTL_VAQ_FMASK 64'b0000000000000000000100000000000000000000000000000000000000000000
100`define FIRE_DLC_MMU_CSR_CTL_VAQ_HW_LD_MASK 64'b0000000000000000000100000000000000000000000000000000000000000000
101`define FIRE_DLC_MMU_CSR_CTL_VAQ_POR_VALUE 1'b0
102`define FIRE_DLC_MMU_CSR_CTL_TPL_FID 3
103`define FIRE_DLC_MMU_CSR_CTL_TPL_SLC 43:43
104`define FIRE_DLC_MMU_CSR_CTL_TPL_WIDTH 1
105`define FIRE_DLC_MMU_CSR_CTL_TPL_INT_SLC 0:0
106`define FIRE_DLC_MMU_CSR_CTL_TPL_POSITION 43
107`define FIRE_DLC_MMU_CSR_CTL_TPL_FMASK 64'b0000000000000000000010000000000000000000000000000000000000000000
108`define FIRE_DLC_MMU_CSR_CTL_TPL_HW_LD_MASK 64'b0000000000000000000010000000000000000000000000000000000000000000
109`define FIRE_DLC_MMU_CSR_CTL_TPL_POR_VALUE 1'b0
110`define FIRE_DLC_MMU_CSR_CTL_TIP_FID 4
111`define FIRE_DLC_MMU_CSR_CTL_TIP_SLC 42:42
112`define FIRE_DLC_MMU_CSR_CTL_TIP_WIDTH 1
113`define FIRE_DLC_MMU_CSR_CTL_TIP_INT_SLC 0:0
114`define FIRE_DLC_MMU_CSR_CTL_TIP_POSITION 42
115`define FIRE_DLC_MMU_CSR_CTL_TIP_FMASK 64'b0000000000000000000001000000000000000000000000000000000000000000
116`define FIRE_DLC_MMU_CSR_CTL_TIP_HW_LD_MASK 64'b0000000000000000000001000000000000000000000000000000000000000000
117`define FIRE_DLC_MMU_CSR_CTL_TIP_POR_VALUE 1'b0
118`define FIRE_DLC_MMU_CSR_CTL_TCM_FID 5
119`define FIRE_DLC_MMU_CSR_CTL_TCM_SLC 41:40
120`define FIRE_DLC_MMU_CSR_CTL_TCM_WIDTH 2
121`define FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC 1:0
122`define FIRE_DLC_MMU_CSR_CTL_TCM_POSITION 40
123`define FIRE_DLC_MMU_CSR_CTL_TCM_FMASK 64'b0000000000000000000000110000000000000000000000000000000000000000
124`define FIRE_DLC_MMU_CSR_CTL_TCM_HW_LD_MASK 64'b0000000000000000000000110000000000000000000000000000000000000000
125`define FIRE_DLC_MMU_CSR_CTL_TCM_POR_VALUE 2'b00
126`define FIRE_DLC_MMU_CSR_CTL_SPAREC_FID 6
127`define FIRE_DLC_MMU_CSR_CTL_SPAREC_SLC 19:16
128`define FIRE_DLC_MMU_CSR_CTL_SPAREC_WIDTH 4
129`define FIRE_DLC_MMU_CSR_CTL_SPAREC_INT_SLC 3:0
130`define FIRE_DLC_MMU_CSR_CTL_SPAREC_POSITION 16
131`define FIRE_DLC_MMU_CSR_CTL_SPAREC_FMASK 64'b0000000000000000000000000000000000000000000011110000000000000000
132`define FIRE_DLC_MMU_CSR_CTL_SPAREC_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
133`define FIRE_DLC_MMU_CSR_CTL_SPAREC_POR_VALUE 4'b0000
134`define FIRE_DLC_MMU_CSR_CTL_PD_FID 7
135`define FIRE_DLC_MMU_CSR_CTL_PD_SLC 12:12
136`define FIRE_DLC_MMU_CSR_CTL_PD_WIDTH 1
137`define FIRE_DLC_MMU_CSR_CTL_PD_INT_SLC 0:0
138`define FIRE_DLC_MMU_CSR_CTL_PD_POSITION 12
139`define FIRE_DLC_MMU_CSR_CTL_PD_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
140`define FIRE_DLC_MMU_CSR_CTL_PD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
141`define FIRE_DLC_MMU_CSR_CTL_PD_POR_VALUE 1'b0
142`define FIRE_DLC_MMU_CSR_CTL_SE_FID 8
143`define FIRE_DLC_MMU_CSR_CTL_SE_SLC 10:10
144`define FIRE_DLC_MMU_CSR_CTL_SE_WIDTH 1
145`define FIRE_DLC_MMU_CSR_CTL_SE_INT_SLC 0:0
146`define FIRE_DLC_MMU_CSR_CTL_SE_POSITION 10
147`define FIRE_DLC_MMU_CSR_CTL_SE_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
148`define FIRE_DLC_MMU_CSR_CTL_SE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
149`define FIRE_DLC_MMU_CSR_CTL_SE_POR_VALUE 1'b0
150`define FIRE_DLC_MMU_CSR_CTL_CM_FID 9
151`define FIRE_DLC_MMU_CSR_CTL_CM_SLC 9:8
152`define FIRE_DLC_MMU_CSR_CTL_CM_WIDTH 2
153`define FIRE_DLC_MMU_CSR_CTL_CM_INT_SLC 1:0
154`define FIRE_DLC_MMU_CSR_CTL_CM_POSITION 8
155`define FIRE_DLC_MMU_CSR_CTL_CM_FMASK 64'b0000000000000000000000000000000000000000000000000000001100000000
156`define FIRE_DLC_MMU_CSR_CTL_CM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
157`define FIRE_DLC_MMU_CSR_CTL_CM_POR_VALUE 2'b00
158`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_FID 10
159`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_SLC 3:3
160`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_WIDTH 1
161`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_INT_SLC 0:0
162`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_POSITION 3
163`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
164`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
165`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_POR_VALUE 1'b0
166`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_FID 11
167`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_SLC 2:2
168`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_WIDTH 1
169`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_INT_SLC 0:0
170`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_POSITION 2
171`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
172`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
173`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_POR_VALUE 1'b0
174`define FIRE_DLC_MMU_CSR_CTL_BE_FID 12
175`define FIRE_DLC_MMU_CSR_CTL_BE_SLC 1:1
176`define FIRE_DLC_MMU_CSR_CTL_BE_WIDTH 1
177`define FIRE_DLC_MMU_CSR_CTL_BE_INT_SLC 0:0
178`define FIRE_DLC_MMU_CSR_CTL_BE_POSITION 1
179`define FIRE_DLC_MMU_CSR_CTL_BE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
180`define FIRE_DLC_MMU_CSR_CTL_BE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
181`define FIRE_DLC_MMU_CSR_CTL_BE_POR_VALUE 1'b0
182`define FIRE_DLC_MMU_CSR_CTL_TE_FID 13
183`define FIRE_DLC_MMU_CSR_CTL_TE_SLC 0:0
184`define FIRE_DLC_MMU_CSR_CTL_TE_WIDTH 1
185`define FIRE_DLC_MMU_CSR_CTL_TE_INT_SLC 0:0
186`define FIRE_DLC_MMU_CSR_CTL_TE_POSITION 0
187`define FIRE_DLC_MMU_CSR_CTL_TE_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
188`define FIRE_DLC_MMU_CSR_CTL_TE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
189`define FIRE_DLC_MMU_CSR_CTL_TE_POR_VALUE 1'b0
190
191//-------------------------------------------------------
192//----- Variable definitions for register fire_dlc_mmu_csr_tsb
193//-------------------------------------------------------
194
195`define FIRE_DLC_MMU_CSR_A_TSB_HW_ADDR 27'b000000011001000000000000001
196`define FIRE_DLC_MMU_CSR_A_TSB_ADDR 30'b000000011001000000000000001000
197`define FIRE_DLC_MMU_CSR_B_TSB_HW_ADDR 27'b000000011101000000000000001
198`define FIRE_DLC_MMU_CSR_B_TSB_ADDR 30'b000000011101000000000000001000
199
200`define FIRE_DLC_MMU_CSR_TSB_WIDTH 64
201`define FIRE_DLC_MMU_CSR_TSB_DEPTH 1
202`define FIRE_DLC_MMU_CSR_TSB_SLC 63:0
203`define FIRE_DLC_MMU_CSR_TSB_INT_SLC 63:0
204`define FIRE_DLC_MMU_CSR_TSB_POSITION 0
205`define FIRE_DLC_MMU_CSR_TSB_LOW_ADDR_WIDTH 0
206`define FIRE_DLC_MMU_CSR_TSB_ADDR_RANGE 26:0
207`define FIRE_DLC_MMU_CSR_TSB_READ_MASK 64'b0000000000000000000000000111111111111111111111111110000100001111
208`define FIRE_DLC_MMU_CSR_TSB_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
209`define FIRE_DLC_MMU_CSR_TSB_WRITE_MASK 64'b0000000000000000000000000111111111111111111111111110000100001111
210`define FIRE_DLC_MMU_CSR_TSB_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
211`define FIRE_DLC_MMU_CSR_TSB_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
212`define FIRE_DLC_MMU_CSR_TSB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
213`define FIRE_DLC_MMU_CSR_TSB_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
214`define FIRE_DLC_MMU_CSR_TSB_RMASK 64'b0000000000000000000000000111111111111111111111111110000100001111
215`define FIRE_DLC_MMU_CSR_TSB_RESERVED_BIT_MASK 64'b1111111111111111111111111000000000000000000000000001111011110000
216`define FIRE_DLC_MMU_CSR_TSB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
217`define FIRE_DLC_MMU_CSR_TSB_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
218`define FIRE_DLC_MMU_CSR_TSB_INTERNAL_REG 1
219`define FIRE_DLC_MMU_CSR_TSB_ZERO_TIME_OMNI 1
220`define FIRE_DLC_MMU_CSR_TSB_NUM_FIELDS 3
221`define FIRE_DLC_MMU_CSR_TSB_TB_FID 0
222`define FIRE_DLC_MMU_CSR_TSB_TB_SLC 38:13
223`define FIRE_DLC_MMU_CSR_TSB_TB_WIDTH 26
224`define FIRE_DLC_MMU_CSR_TSB_TB_INT_SLC 25:0
225`define FIRE_DLC_MMU_CSR_TSB_TB_POSITION 13
226`define FIRE_DLC_MMU_CSR_TSB_TB_FMASK 64'b0000000000000000000000000111111111111111111111111110000000000000
227`define FIRE_DLC_MMU_CSR_TSB_TB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
228`define FIRE_DLC_MMU_CSR_TSB_TB_POR_VALUE 26'b00000000000000000000000000
229`define FIRE_DLC_MMU_CSR_TSB_PS_FID 1
230`define FIRE_DLC_MMU_CSR_TSB_PS_SLC 8:8
231`define FIRE_DLC_MMU_CSR_TSB_PS_WIDTH 1
232`define FIRE_DLC_MMU_CSR_TSB_PS_INT_SLC 0:0
233`define FIRE_DLC_MMU_CSR_TSB_PS_POSITION 8
234`define FIRE_DLC_MMU_CSR_TSB_PS_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
235`define FIRE_DLC_MMU_CSR_TSB_PS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
236`define FIRE_DLC_MMU_CSR_TSB_PS_POR_VALUE 1'b0
237`define FIRE_DLC_MMU_CSR_TSB_TS_FID 2
238`define FIRE_DLC_MMU_CSR_TSB_TS_SLC 3:0
239`define FIRE_DLC_MMU_CSR_TSB_TS_WIDTH 4
240`define FIRE_DLC_MMU_CSR_TSB_TS_INT_SLC 3:0
241`define FIRE_DLC_MMU_CSR_TSB_TS_POSITION 0
242`define FIRE_DLC_MMU_CSR_TSB_TS_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001111
243`define FIRE_DLC_MMU_CSR_TSB_TS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
244`define FIRE_DLC_MMU_CSR_TSB_TS_POR_VALUE 4'b0000
245
246//-------------------------------------------------------
247//----- Variable definitions for register fire_dlc_mmu_csr_fsh
248//-------------------------------------------------------
249
250`define FIRE_DLC_MMU_CSR_A_FSH_HW_ADDR 27'b000000011001000000000100000
251`define FIRE_DLC_MMU_CSR_A_FSH_ADDR 30'b000000011001000000000100000000
252`define FIRE_DLC_MMU_CSR_B_FSH_HW_ADDR 27'b000000011101000000000100000
253`define FIRE_DLC_MMU_CSR_B_FSH_ADDR 30'b000000011101000000000100000000
254
255`define FIRE_DLC_MMU_CSR_FSH_WIDTH 64
256`define FIRE_DLC_MMU_CSR_FSH_DEPTH 1
257`define FIRE_DLC_MMU_CSR_FSH_SLC 63:0
258`define FIRE_DLC_MMU_CSR_FSH_INT_SLC 63:0
259`define FIRE_DLC_MMU_CSR_FSH_POSITION 0
260`define FIRE_DLC_MMU_CSR_FSH_LOW_ADDR_WIDTH 0
261`define FIRE_DLC_MMU_CSR_FSH_ADDR_RANGE 26:0
262`define FIRE_DLC_MMU_CSR_FSH_READ_MASK 64'b0000000000000000000000000111111111111111111111111111111111000000
263`define FIRE_DLC_MMU_CSR_FSH_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
264`define FIRE_DLC_MMU_CSR_FSH_WRITE_MASK 64'b0000000000000000000000000111111111111111111111111111111111000000
265`define FIRE_DLC_MMU_CSR_FSH_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
266`define FIRE_DLC_MMU_CSR_FSH_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
267`define FIRE_DLC_MMU_CSR_FSH_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
268`define FIRE_DLC_MMU_CSR_FSH_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
269`define FIRE_DLC_MMU_CSR_FSH_RMASK 64'b0000000000000000000000000111111111111111111111111111111111000000
270`define FIRE_DLC_MMU_CSR_FSH_RESERVED_BIT_MASK 64'b1111111111111111111111111000000000000000000000000000000000111111
271`define FIRE_DLC_MMU_CSR_FSH_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
272`define FIRE_DLC_MMU_CSR_FSH_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
273`define FIRE_DLC_MMU_CSR_FSH_INTERNAL_REG 1
274`define FIRE_DLC_MMU_CSR_FSH_ZERO_TIME_OMNI 1
275`define FIRE_DLC_MMU_CSR_FSH_NUM_FIELDS 1
276`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_FID 0
277`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_SLC 38:6
278`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_WIDTH 33
279`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_INT_SLC 32:0
280`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_POSITION 6
281`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_FMASK 64'b0000000000000000000000000111111111111111111111111111111111000000
282`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
283`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_POR_VALUE 33'b000000000000000000000000000000000
284
285//-------------------------------------------------------
286//----- Variable definitions for register fire_dlc_mmu_csr_inv
287//-------------------------------------------------------
288
289`define FIRE_DLC_MMU_CSR_A_INV_HW_ADDR 27'b000000011001000000000100001
290`define FIRE_DLC_MMU_CSR_A_INV_ADDR 30'b000000011001000000000100001000
291`define FIRE_DLC_MMU_CSR_B_INV_HW_ADDR 27'b000000011101000000000100001
292`define FIRE_DLC_MMU_CSR_B_INV_ADDR 30'b000000011101000000000100001000
293
294`define FIRE_DLC_MMU_CSR_INV_WIDTH 64
295`define FIRE_DLC_MMU_CSR_INV_DEPTH 1
296`define FIRE_DLC_MMU_CSR_INV_SLC 63:0
297`define FIRE_DLC_MMU_CSR_INV_INT_SLC 63:0
298`define FIRE_DLC_MMU_CSR_INV_POSITION 0
299`define FIRE_DLC_MMU_CSR_INV_LOW_ADDR_WIDTH 0
300`define FIRE_DLC_MMU_CSR_INV_ADDR_RANGE 26:0
301`define FIRE_DLC_MMU_CSR_INV_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
302`define FIRE_DLC_MMU_CSR_INV_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
303`define FIRE_DLC_MMU_CSR_INV_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
304`define FIRE_DLC_MMU_CSR_INV_WRITE_ONLY_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
305`define FIRE_DLC_MMU_CSR_INV_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
306`define FIRE_DLC_MMU_CSR_INV_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
307`define FIRE_DLC_MMU_CSR_INV_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
308`define FIRE_DLC_MMU_CSR_INV_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
309`define FIRE_DLC_MMU_CSR_INV_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
310`define FIRE_DLC_MMU_CSR_INV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
311`define FIRE_DLC_MMU_CSR_INV_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
312`define FIRE_DLC_MMU_CSR_INV_INTERNAL_REG 0
313`define FIRE_DLC_MMU_CSR_INV_EXTERNAL_DECODE_REG 1
314`define FIRE_DLC_MMU_CSR_INV_ZERO_TIME_OMNI 0
315`define FIRE_DLC_MMU_CSR_INV_NUM_FIELDS 1
316`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_FID 0
317`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_SLC 63:0
318`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_WIDTH 64
319`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_INT_SLC 63:0
320`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_POSITION 0
321`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
322`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
323`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
324
325//-------------------------------------------------------
326//----- Variable definitions for register fire_dlc_mmu_csr_log
327//-------------------------------------------------------
328
329`define FIRE_DLC_MMU_CSR_A_LOG_HW_ADDR 27'b000000011001000001000000000
330`define FIRE_DLC_MMU_CSR_A_LOG_ADDR 30'b000000011001000001000000000000
331`define FIRE_DLC_MMU_CSR_B_LOG_HW_ADDR 27'b000000011101000001000000000
332`define FIRE_DLC_MMU_CSR_B_LOG_ADDR 30'b000000011101000001000000000000
333
334`define FIRE_DLC_MMU_CSR_LOG_WIDTH 64
335`define FIRE_DLC_MMU_CSR_LOG_DEPTH 1
336`define FIRE_DLC_MMU_CSR_LOG_SLC 63:0
337`define FIRE_DLC_MMU_CSR_LOG_INT_SLC 63:0
338`define FIRE_DLC_MMU_CSR_LOG_POSITION 0
339`define FIRE_DLC_MMU_CSR_LOG_LOW_ADDR_WIDTH 0
340`define FIRE_DLC_MMU_CSR_LOG_ADDR_RANGE 26:0
341`define FIRE_DLC_MMU_CSR_LOG_READ_MASK 64'b0000000000000000000000000000000000000000000111111111111111111111
342`define FIRE_DLC_MMU_CSR_LOG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
343`define FIRE_DLC_MMU_CSR_LOG_WRITE_MASK 64'b0000000000000000000000000000000000000000000111111111111111111111
344`define FIRE_DLC_MMU_CSR_LOG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
345`define FIRE_DLC_MMU_CSR_LOG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
346`define FIRE_DLC_MMU_CSR_LOG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
347`define FIRE_DLC_MMU_CSR_LOG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
348`define FIRE_DLC_MMU_CSR_LOG_RMASK 64'b0000000000000000000000000000000000000000000111111111111111111111
349`define FIRE_DLC_MMU_CSR_LOG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111000000000000000000000
350`define FIRE_DLC_MMU_CSR_LOG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
351`define FIRE_DLC_MMU_CSR_LOG_POR_VALUE 64'b0000000000000000000000000000000000000000000111111111111111111111
352`define FIRE_DLC_MMU_CSR_LOG_INTERNAL_REG 1
353`define FIRE_DLC_MMU_CSR_LOG_ZERO_TIME_OMNI 1
354`define FIRE_DLC_MMU_CSR_LOG_NUM_FIELDS 1
355`define FIRE_DLC_MMU_CSR_LOG_EN_FID 0
356`define FIRE_DLC_MMU_CSR_LOG_EN_SLC 20:0
357`define FIRE_DLC_MMU_CSR_LOG_EN_WIDTH 21
358`define FIRE_DLC_MMU_CSR_LOG_EN_INT_SLC 20:0
359`define FIRE_DLC_MMU_CSR_LOG_EN_POSITION 0
360`define FIRE_DLC_MMU_CSR_LOG_EN_FMASK 64'b0000000000000000000000000000000000000000000111111111111111111111
361`define FIRE_DLC_MMU_CSR_LOG_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
362`define FIRE_DLC_MMU_CSR_LOG_EN_POR_VALUE 21'b111111111111111111111
363
364//-------------------------------------------------------
365//----- Variable definitions for register fire_dlc_mmu_csr_int_en
366//-------------------------------------------------------
367
368`define FIRE_DLC_MMU_CSR_A_INT_EN_HW_ADDR 27'b000000011001000001000000001
369`define FIRE_DLC_MMU_CSR_A_INT_EN_ADDR 30'b000000011001000001000000001000
370`define FIRE_DLC_MMU_CSR_B_INT_EN_HW_ADDR 27'b000000011101000001000000001
371`define FIRE_DLC_MMU_CSR_B_INT_EN_ADDR 30'b000000011101000001000000001000
372
373`define FIRE_DLC_MMU_CSR_INT_EN_WIDTH 64
374`define FIRE_DLC_MMU_CSR_INT_EN_DEPTH 1
375`define FIRE_DLC_MMU_CSR_INT_EN_SLC 63:0
376`define FIRE_DLC_MMU_CSR_INT_EN_INT_SLC 63:0
377`define FIRE_DLC_MMU_CSR_INT_EN_POSITION 0
378`define FIRE_DLC_MMU_CSR_INT_EN_LOW_ADDR_WIDTH 0
379`define FIRE_DLC_MMU_CSR_INT_EN_ADDR_RANGE 26:0
380`define FIRE_DLC_MMU_CSR_INT_EN_READ_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
381`define FIRE_DLC_MMU_CSR_INT_EN_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
382`define FIRE_DLC_MMU_CSR_INT_EN_WRITE_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
383`define FIRE_DLC_MMU_CSR_INT_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
384`define FIRE_DLC_MMU_CSR_INT_EN_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
385`define FIRE_DLC_MMU_CSR_INT_EN_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
386`define FIRE_DLC_MMU_CSR_INT_EN_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
387`define FIRE_DLC_MMU_CSR_INT_EN_RMASK 64'b0000000000011111111111111111111100000000000111111111111111111111
388`define FIRE_DLC_MMU_CSR_INT_EN_RESERVED_BIT_MASK 64'b1111111111100000000000000000000011111111111000000000000000000000
389`define FIRE_DLC_MMU_CSR_INT_EN_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
390`define FIRE_DLC_MMU_CSR_INT_EN_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
391`define FIRE_DLC_MMU_CSR_INT_EN_INTERNAL_REG 1
392`define FIRE_DLC_MMU_CSR_INT_EN_ZERO_TIME_OMNI 1
393`define FIRE_DLC_MMU_CSR_INT_EN_NUM_FIELDS 2
394`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_FID 0
395`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_SLC 52:32
396`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_WIDTH 21
397`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_INT_SLC 20:0
398`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_POSITION 32
399`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_FMASK 64'b0000000000011111111111111111111100000000000000000000000000000000
400`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
401`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_POR_VALUE 21'b000000000000000000000
402`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_FID 1
403`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_SLC 20:0
404`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_WIDTH 21
405`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_INT_SLC 20:0
406`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_POSITION 0
407`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_FMASK 64'b0000000000000000000000000000000000000000000111111111111111111111
408`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
409`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_POR_VALUE 21'b000000000000000000000
410
411//-------------------------------------------------------
412//----- Variable definitions for register fire_dlc_mmu_csr_en_err
413//-------------------------------------------------------
414
415`define FIRE_DLC_MMU_CSR_A_EN_ERR_HW_ADDR 27'b000000011001000001000000010
416`define FIRE_DLC_MMU_CSR_A_EN_ERR_ADDR 30'b000000011001000001000000010000
417`define FIRE_DLC_MMU_CSR_B_EN_ERR_HW_ADDR 27'b000000011101000001000000010
418`define FIRE_DLC_MMU_CSR_B_EN_ERR_ADDR 30'b000000011101000001000000010000
419
420`define FIRE_DLC_MMU_CSR_EN_ERR_WIDTH 64
421`define FIRE_DLC_MMU_CSR_EN_ERR_DEPTH 1
422`define FIRE_DLC_MMU_CSR_EN_ERR_SLC 63:0
423`define FIRE_DLC_MMU_CSR_EN_ERR_INT_SLC 63:0
424`define FIRE_DLC_MMU_CSR_EN_ERR_POSITION 0
425`define FIRE_DLC_MMU_CSR_EN_ERR_LOW_ADDR_WIDTH 0
426`define FIRE_DLC_MMU_CSR_EN_ERR_ADDR_RANGE 26:0
427`define FIRE_DLC_MMU_CSR_EN_ERR_READ_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
428`define FIRE_DLC_MMU_CSR_EN_ERR_READ_ONLY_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
429`define FIRE_DLC_MMU_CSR_EN_ERR_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
430`define FIRE_DLC_MMU_CSR_EN_ERR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
431`define FIRE_DLC_MMU_CSR_EN_ERR_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
432`define FIRE_DLC_MMU_CSR_EN_ERR_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
433`define FIRE_DLC_MMU_CSR_EN_ERR_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
434`define FIRE_DLC_MMU_CSR_EN_ERR_RMASK 64'b0000000000011111111111111111111100000000000111111111111111111111
435`define FIRE_DLC_MMU_CSR_EN_ERR_RESERVED_BIT_MASK 64'b1111111111100000000000000000000011111111111000000000000000000000
436`define FIRE_DLC_MMU_CSR_EN_ERR_HW_LD_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
437`define FIRE_DLC_MMU_CSR_EN_ERR_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
438`define FIRE_DLC_MMU_CSR_EN_ERR_INTERNAL_REG 0
439`define FIRE_DLC_MMU_CSR_EN_ERR_EXTERNAL_DECODE_REG 1
440`define FIRE_DLC_MMU_CSR_EN_ERR_ZERO_TIME_OMNI 0
441`define FIRE_DLC_MMU_CSR_EN_ERR_NUM_FIELDS 2
442`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_FID 0
443`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_SLC 52:32
444`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_WIDTH 21
445`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_INT_SLC 20:0
446`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_POSITION 32
447`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_FMASK 64'b0000000000011111111111111111111100000000000000000000000000000000
448`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_HW_LD_MASK 64'b0000000000011111111111111111111100000000000000000000000000000000
449`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_POR_VALUE 21'b000000000000000000000
450`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_FID 1
451`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_SLC 20:0
452`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_WIDTH 21
453`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_INT_SLC 20:0
454`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_POSITION 0
455`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000111111111111111111111
456`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000111111111111111111111
457`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_POR_VALUE 21'b000000000000000000000
458
459//-------------------------------------------------------
460//----- Variable definitions for register fire_dlc_mmu_csr_err_rw1c_alias
461//-------------------------------------------------------
462
463`define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_HW_ADDR 27'b000000011001000001000000011
464`define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_ADDR 30'b000000011001000001000000011000
465`define FIRE_DLC_MMU_CSR_B_ERR_RW1C_ALIAS_HW_ADDR 27'b000000011101000001000000011
466`define FIRE_DLC_MMU_CSR_B_ERR_RW1C_ALIAS_ADDR 30'b000000011101000001000000011000
467
468`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH 64
469`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_DEPTH 1
470`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SLC 63:0
471`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_INT_SLC 63:0
472`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_POSITION 0
473`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_LOW_ADDR_WIDTH 0
474`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_ADDR_RANGE 26:0
475`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_READ_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
476`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
477`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
478`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
479`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
480`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_CLEAR_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
481`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
482`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_RMASK 64'b0000000000011111111111111111111100000000000111111111111111111111
483`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_RESERVED_BIT_MASK 64'b1111111111100000000000000000000011111111111000000000000000000000
484`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_HW_LD_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
485`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
486`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_INTERNAL_REG 1
487`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_ZERO_TIME_OMNI 1
488`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_NUM_FIELDS 42
489`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_FID 0
490`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_SLC 52:52
491`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_WIDTH 1
492`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_INT_SLC 0:0
493`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_POSITION 52
494`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_FMASK 64'b0000000000010000000000000000000000000000000000000000000000000000
495`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_HW_LD_MASK 64'b0000000000010000000000000000000000000000000000000000000000000000
496`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_POR_VALUE 1'b0
497`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_FID 1
498`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_SLC 51:51
499`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_WIDTH 1
500`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_INT_SLC 0:0
501`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_POSITION 51
502`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_FMASK 64'b0000000000001000000000000000000000000000000000000000000000000000
503`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_HW_LD_MASK 64'b0000000000001000000000000000000000000000000000000000000000000000
504`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_POR_VALUE 1'b0
505`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_FID 2
506`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_SLC 50:50
507`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_WIDTH 1
508`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_INT_SLC 0:0
509`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_POSITION 50
510`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_FMASK 64'b0000000000000100000000000000000000000000000000000000000000000000
511`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_HW_LD_MASK 64'b0000000000000100000000000000000000000000000000000000000000000000
512`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_POR_VALUE 1'b0
513`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_FID 3
514`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_SLC 49:49
515`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_WIDTH 1
516`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_INT_SLC 0:0
517`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_POSITION 49
518`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_FMASK 64'b0000000000000010000000000000000000000000000000000000000000000000
519`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_HW_LD_MASK 64'b0000000000000010000000000000000000000000000000000000000000000000
520`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_POR_VALUE 1'b0
521`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_FID 4
522`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_SLC 48:48
523`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_WIDTH 1
524`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_INT_SLC 0:0
525`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_POSITION 48
526`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_FMASK 64'b0000000000000001000000000000000000000000000000000000000000000000
527`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_HW_LD_MASK 64'b0000000000000001000000000000000000000000000000000000000000000000
528`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_POR_VALUE 1'b0
529`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_FID 5
530`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_SLC 47:47
531`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_WIDTH 1
532`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_INT_SLC 0:0
533`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_POSITION 47
534`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_FMASK 64'b0000000000000000100000000000000000000000000000000000000000000000
535`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_HW_LD_MASK 64'b0000000000000000100000000000000000000000000000000000000000000000
536`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_POR_VALUE 1'b0
537`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_FID 6
538`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_SLC 46:46
539`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_WIDTH 1
540`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_INT_SLC 0:0
541`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_POSITION 46
542`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_FMASK 64'b0000000000000000010000000000000000000000000000000000000000000000
543`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_HW_LD_MASK 64'b0000000000000000010000000000000000000000000000000000000000000000
544`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_POR_VALUE 1'b0
545`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_FID 7
546`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_SLC 45:45
547`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_WIDTH 1
548`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_INT_SLC 0:0
549`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_POSITION 45
550`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_FMASK 64'b0000000000000000001000000000000000000000000000000000000000000000
551`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_HW_LD_MASK 64'b0000000000000000001000000000000000000000000000000000000000000000
552`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_POR_VALUE 1'b0
553`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_FID 8
554`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_SLC 44:44
555`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_WIDTH 1
556`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_INT_SLC 0:0
557`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_POSITION 44
558`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_FMASK 64'b0000000000000000000100000000000000000000000000000000000000000000
559`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_HW_LD_MASK 64'b0000000000000000000100000000000000000000000000000000000000000000
560`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_POR_VALUE 1'b0
561`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_FID 9
562`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_SLC 43:43
563`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_WIDTH 1
564`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_INT_SLC 0:0
565`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_POSITION 43
566`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_FMASK 64'b0000000000000000000010000000000000000000000000000000000000000000
567`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_HW_LD_MASK 64'b0000000000000000000010000000000000000000000000000000000000000000
568`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_POR_VALUE 1'b0
569`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_FID 10
570`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_SLC 42:42
571`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_WIDTH 1
572`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_INT_SLC 0:0
573`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_POSITION 42
574`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_FMASK 64'b0000000000000000000001000000000000000000000000000000000000000000
575`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_HW_LD_MASK 64'b0000000000000000000001000000000000000000000000000000000000000000
576`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_POR_VALUE 1'b0
577`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_FID 11
578`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_SLC 41:41
579`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_WIDTH 1
580`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_INT_SLC 0:0
581`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_POSITION 41
582`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_FMASK 64'b0000000000000000000000100000000000000000000000000000000000000000
583`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_HW_LD_MASK 64'b0000000000000000000000100000000000000000000000000000000000000000
584`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_POR_VALUE 1'b0
585`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_FID 12
586`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_SLC 40:40
587`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_WIDTH 1
588`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_INT_SLC 0:0
589`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_POSITION 40
590`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_FMASK 64'b0000000000000000000000010000000000000000000000000000000000000000
591`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_HW_LD_MASK 64'b0000000000000000000000010000000000000000000000000000000000000000
592`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_POR_VALUE 1'b0
593`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_FID 13
594`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_SLC 39:39
595`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_WIDTH 1
596`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_INT_SLC 0:0
597`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_POSITION 39
598`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
599`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
600`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_POR_VALUE 1'b0
601`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_FID 14
602`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_SLC 38:38
603`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_WIDTH 1
604`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_INT_SLC 0:0
605`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_POSITION 38
606`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
607`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
608`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_POR_VALUE 1'b0
609`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_FID 15
610`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_SLC 37:37
611`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_WIDTH 1
612`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_INT_SLC 0:0
613`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_POSITION 37
614`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
615`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
616`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_POR_VALUE 1'b0
617`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_FID 16
618`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_SLC 36:36
619`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_WIDTH 1
620`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_INT_SLC 0:0
621`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_POSITION 36
622`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
623`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
624`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_POR_VALUE 1'b0
625`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_FID 17
626`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_SLC 35:35
627`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_WIDTH 1
628`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_INT_SLC 0:0
629`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_POSITION 35
630`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_FMASK 64'b0000000000000000000000000000100000000000000000000000000000000000
631`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000000100000000000000000000000000000000000
632`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_POR_VALUE 1'b0
633`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_FID 18
634`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_SLC 34:34
635`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_WIDTH 1
636`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_INT_SLC 0:0
637`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_POSITION 34
638`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_FMASK 64'b0000000000000000000000000000010000000000000000000000000000000000
639`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_HW_LD_MASK 64'b0000000000000000000000000000010000000000000000000000000000000000
640`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_POR_VALUE 1'b0
641`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_FID 19
642`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_SLC 33:33
643`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_WIDTH 1
644`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_INT_SLC 0:0
645`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_POSITION 33
646`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
647`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_HW_LD_MASK 64'b0000000000000000000000000000001000000000000000000000000000000000
648`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_POR_VALUE 1'b0
649`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_FID 20
650`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_SLC 32:32
651`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_WIDTH 1
652`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_INT_SLC 0:0
653`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_POSITION 32
654`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
655`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_HW_LD_MASK 64'b0000000000000000000000000000000100000000000000000000000000000000
656`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_POR_VALUE 1'b0
657`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_FID 21
658`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_SLC 20:20
659`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_WIDTH 1
660`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_INT_SLC 0:0
661`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_POSITION 20
662`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000100000000000000000000
663`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000100000000000000000000
664`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_POR_VALUE 1'b0
665`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_FID 22
666`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_SLC 19:19
667`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_WIDTH 1
668`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_INT_SLC 0:0
669`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_POSITION 19
670`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_FMASK 64'b0000000000000000000000000000000000000000000010000000000000000000
671`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000010000000000000000000
672`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_POR_VALUE 1'b0
673`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_FID 23
674`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_SLC 18:18
675`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_WIDTH 1
676`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_INT_SLC 0:0
677`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_POSITION 18
678`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000001000000000000000000
679`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000001000000000000000000
680`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_POR_VALUE 1'b0
681`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_FID 24
682`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_SLC 17:17
683`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_WIDTH 1
684`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_INT_SLC 0:0
685`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_POSITION 17
686`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000100000000000000000
687`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000100000000000000000
688`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_POR_VALUE 1'b0
689`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_FID 25
690`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_SLC 16:16
691`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_WIDTH 1
692`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_INT_SLC 0:0
693`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_POSITION 16
694`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
695`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000010000000000000000
696`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_POR_VALUE 1'b0
697`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_FID 26
698`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_SLC 15:15
699`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_WIDTH 1
700`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_INT_SLC 0:0
701`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_POSITION 15
702`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
703`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001000000000000000
704`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_POR_VALUE 1'b0
705`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_FID 27
706`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_SLC 14:14
707`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_WIDTH 1
708`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_INT_SLC 0:0
709`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_POSITION 14
710`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000100000000000000
711`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000100000000000000
712`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_POR_VALUE 1'b0
713`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_FID 28
714`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_SLC 13:13
715`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_WIDTH 1
716`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_INT_SLC 0:0
717`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_POSITION 13
718`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
719`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000010000000000000
720`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_POR_VALUE 1'b0
721`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_FID 29
722`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_SLC 12:12
723`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_WIDTH 1
724`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_INT_SLC 0:0
725`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_POSITION 12
726`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
727`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
728`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_POR_VALUE 1'b0
729`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_FID 30
730`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_SLC 11:11
731`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_WIDTH 1
732`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_INT_SLC 0:0
733`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_POSITION 11
734`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
735`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
736`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_POR_VALUE 1'b0
737`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_FID 31
738`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_SLC 10:10
739`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_WIDTH 1
740`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_INT_SLC 0:0
741`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_POSITION 10
742`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
743`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
744`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_POR_VALUE 1'b0
745`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_FID 32
746`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_SLC 9:9
747`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_WIDTH 1
748`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_INT_SLC 0:0
749`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_POSITION 9
750`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
751`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
752`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_POR_VALUE 1'b0
753`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_FID 33
754`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_SLC 8:8
755`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_WIDTH 1
756`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_INT_SLC 0:0
757`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_POSITION 8
758`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
759`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
760`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_POR_VALUE 1'b0
761`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_FID 34
762`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_SLC 7:7
763`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_WIDTH 1
764`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_INT_SLC 0:0
765`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_POSITION 7
766`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
767`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
768`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_POR_VALUE 1'b0
769`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_FID 35
770`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_SLC 6:6
771`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_WIDTH 1
772`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_INT_SLC 0:0
773`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_POSITION 6
774`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
775`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
776`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_POR_VALUE 1'b0
777`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_FID 36
778`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_SLC 5:5
779`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_WIDTH 1
780`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_INT_SLC 0:0
781`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_POSITION 5
782`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
783`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
784`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_POR_VALUE 1'b0
785`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_FID 37
786`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_SLC 4:4
787`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_WIDTH 1
788`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_INT_SLC 0:0
789`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_POSITION 4
790`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
791`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
792`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_POR_VALUE 1'b0
793`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_FID 38
794`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_SLC 3:3
795`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_WIDTH 1
796`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_INT_SLC 0:0
797`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_POSITION 3
798`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
799`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
800`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_POR_VALUE 1'b0
801`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_FID 39
802`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_SLC 2:2
803`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_WIDTH 1
804`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_INT_SLC 0:0
805`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_POSITION 2
806`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
807`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
808`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_POR_VALUE 1'b0
809`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_FID 40
810`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_SLC 1:1
811`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_WIDTH 1
812`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_INT_SLC 0:0
813`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_POSITION 1
814`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
815`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
816`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_POR_VALUE 1'b0
817`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_FID 41
818`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_SLC 0:0
819`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_WIDTH 1
820`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_INT_SLC 0:0
821`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_POSITION 0
822`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
823`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
824`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_POR_VALUE 1'b0
825
826//-------------------------------------------------------
827//----- Variable definitions for register fire_dlc_mmu_csr_err_rw1s_alias
828//-------------------------------------------------------
829
830`define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_HW_ADDR 27'b000000011001000001000000100
831`define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_ADDR 30'b000000011001000001000000100000
832`define FIRE_DLC_MMU_CSR_B_ERR_RW1S_ALIAS_HW_ADDR 27'b000000011101000001000000100
833`define FIRE_DLC_MMU_CSR_B_ERR_RW1S_ALIAS_ADDR 30'b000000011101000001000000100000
834
835`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_WIDTH 64
836`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_DEPTH 1
837`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SLC 63:0
838`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_INT_SLC 63:0
839`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_POSITION 0
840`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_LOW_ADDR_WIDTH 0
841`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_ADDR_RANGE 26:0
842`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_READ_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
843`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
844`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
845`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
846`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SET_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
847`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
848`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
849`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_RMASK 64'b0000000000011111111111111111111100000000000111111111111111111111
850`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_RESERVED_BIT_MASK 64'b1111111111100000000000000000000011111111111000000000000000000000
851`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_HW_LD_MASK 64'b0000000000011111111111111111111100000000000111111111111111111111
852`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
853`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_INTERNAL_REG 1
854`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_ZERO_TIME_OMNI 1
855`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_NUM_FIELDS 42
856`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_FID 0
857`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_SLC 52:52
858`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_WIDTH 1
859`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_INT_SLC 0:0
860`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_POSITION 52
861`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_FMASK 64'b0000000000010000000000000000000000000000000000000000000000000000
862`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_HW_LD_MASK 64'b0000000000010000000000000000000000000000000000000000000000000000
863`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_POR_VALUE 1'b0
864`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_FID 1
865`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_SLC 51:51
866`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_WIDTH 1
867`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_INT_SLC 0:0
868`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_POSITION 51
869`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_FMASK 64'b0000000000001000000000000000000000000000000000000000000000000000
870`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_HW_LD_MASK 64'b0000000000001000000000000000000000000000000000000000000000000000
871`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_POR_VALUE 1'b0
872`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_FID 2
873`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_SLC 50:50
874`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_WIDTH 1
875`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_INT_SLC 0:0
876`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_POSITION 50
877`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_FMASK 64'b0000000000000100000000000000000000000000000000000000000000000000
878`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_HW_LD_MASK 64'b0000000000000100000000000000000000000000000000000000000000000000
879`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_POR_VALUE 1'b0
880`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_FID 3
881`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_SLC 49:49
882`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_WIDTH 1
883`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_INT_SLC 0:0
884`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_POSITION 49
885`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_FMASK 64'b0000000000000010000000000000000000000000000000000000000000000000
886`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_HW_LD_MASK 64'b0000000000000010000000000000000000000000000000000000000000000000
887`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_POR_VALUE 1'b0
888`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_FID 4
889`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_SLC 48:48
890`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_WIDTH 1
891`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_INT_SLC 0:0
892`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_POSITION 48
893`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_FMASK 64'b0000000000000001000000000000000000000000000000000000000000000000
894`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_HW_LD_MASK 64'b0000000000000001000000000000000000000000000000000000000000000000
895`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_POR_VALUE 1'b0
896`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_FID 5
897`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_SLC 47:47
898`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_WIDTH 1
899`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_INT_SLC 0:0
900`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_POSITION 47
901`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_FMASK 64'b0000000000000000100000000000000000000000000000000000000000000000
902`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_HW_LD_MASK 64'b0000000000000000100000000000000000000000000000000000000000000000
903`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_POR_VALUE 1'b0
904`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_FID 6
905`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_SLC 46:46
906`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_WIDTH 1
907`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_INT_SLC 0:0
908`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_POSITION 46
909`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_FMASK 64'b0000000000000000010000000000000000000000000000000000000000000000
910`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_HW_LD_MASK 64'b0000000000000000010000000000000000000000000000000000000000000000
911`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_POR_VALUE 1'b0
912`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_FID 7
913`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_SLC 45:45
914`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_WIDTH 1
915`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_INT_SLC 0:0
916`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_POSITION 45
917`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_FMASK 64'b0000000000000000001000000000000000000000000000000000000000000000
918`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_HW_LD_MASK 64'b0000000000000000001000000000000000000000000000000000000000000000
919`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_POR_VALUE 1'b0
920`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_FID 8
921`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_SLC 44:44
922`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_WIDTH 1
923`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_INT_SLC 0:0
924`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_POSITION 44
925`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_FMASK 64'b0000000000000000000100000000000000000000000000000000000000000000
926`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_HW_LD_MASK 64'b0000000000000000000100000000000000000000000000000000000000000000
927`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_POR_VALUE 1'b0
928`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_FID 9
929`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_SLC 43:43
930`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_WIDTH 1
931`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_INT_SLC 0:0
932`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_POSITION 43
933`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_FMASK 64'b0000000000000000000010000000000000000000000000000000000000000000
934`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_HW_LD_MASK 64'b0000000000000000000010000000000000000000000000000000000000000000
935`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_POR_VALUE 1'b0
936`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_FID 10
937`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_SLC 42:42
938`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_WIDTH 1
939`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_INT_SLC 0:0
940`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_POSITION 42
941`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_FMASK 64'b0000000000000000000001000000000000000000000000000000000000000000
942`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_HW_LD_MASK 64'b0000000000000000000001000000000000000000000000000000000000000000
943`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_POR_VALUE 1'b0
944`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_FID 11
945`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_SLC 41:41
946`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_WIDTH 1
947`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_INT_SLC 0:0
948`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_POSITION 41
949`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_FMASK 64'b0000000000000000000000100000000000000000000000000000000000000000
950`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_HW_LD_MASK 64'b0000000000000000000000100000000000000000000000000000000000000000
951`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_POR_VALUE 1'b0
952`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_FID 12
953`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_SLC 40:40
954`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_WIDTH 1
955`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_INT_SLC 0:0
956`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_POSITION 40
957`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_FMASK 64'b0000000000000000000000010000000000000000000000000000000000000000
958`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_HW_LD_MASK 64'b0000000000000000000000010000000000000000000000000000000000000000
959`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_POR_VALUE 1'b0
960`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_FID 13
961`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_SLC 39:39
962`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_WIDTH 1
963`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_INT_SLC 0:0
964`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_POSITION 39
965`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
966`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_HW_LD_MASK 64'b0000000000000000000000001000000000000000000000000000000000000000
967`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_POR_VALUE 1'b0
968`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_FID 14
969`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_SLC 38:38
970`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_WIDTH 1
971`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_INT_SLC 0:0
972`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_POSITION 38
973`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
974`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_HW_LD_MASK 64'b0000000000000000000000000100000000000000000000000000000000000000
975`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_POR_VALUE 1'b0
976`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_FID 15
977`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_SLC 37:37
978`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_WIDTH 1
979`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_INT_SLC 0:0
980`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_POSITION 37
981`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
982`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_HW_LD_MASK 64'b0000000000000000000000000010000000000000000000000000000000000000
983`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_POR_VALUE 1'b0
984`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_FID 16
985`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_SLC 36:36
986`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_WIDTH 1
987`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_INT_SLC 0:0
988`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_POSITION 36
989`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
990`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_HW_LD_MASK 64'b0000000000000000000000000001000000000000000000000000000000000000
991`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_POR_VALUE 1'b0
992`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_FID 17
993`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_SLC 35:35
994`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_WIDTH 1
995`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_INT_SLC 0:0
996`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_POSITION 35
997`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_FMASK 64'b0000000000000000000000000000100000000000000000000000000000000000
998`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_HW_LD_MASK 64'b0000000000000000000000000000100000000000000000000000000000000000
999`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_POR_VALUE 1'b0
1000`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_FID 18
1001`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_SLC 34:34
1002`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_WIDTH 1
1003`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_INT_SLC 0:0
1004`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_POSITION 34
1005`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_FMASK 64'b0000000000000000000000000000010000000000000000000000000000000000
1006`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_HW_LD_MASK 64'b0000000000000000000000000000010000000000000000000000000000000000
1007`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_POR_VALUE 1'b0
1008`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_FID 19
1009`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_SLC 33:33
1010`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_WIDTH 1
1011`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_INT_SLC 0:0
1012`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_POSITION 33
1013`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
1014`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_HW_LD_MASK 64'b0000000000000000000000000000001000000000000000000000000000000000
1015`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_POR_VALUE 1'b0
1016`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_FID 20
1017`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_SLC 32:32
1018`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_WIDTH 1
1019`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_INT_SLC 0:0
1020`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_POSITION 32
1021`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
1022`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_HW_LD_MASK 64'b0000000000000000000000000000000100000000000000000000000000000000
1023`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_POR_VALUE 1'b0
1024`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_FID 21
1025`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_SLC 20:20
1026`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_WIDTH 1
1027`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_INT_SLC 0:0
1028`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_POSITION 20
1029`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000100000000000000000000
1030`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000100000000000000000000
1031`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_POR_VALUE 1'b0
1032`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_FID 22
1033`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_SLC 19:19
1034`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_WIDTH 1
1035`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_INT_SLC 0:0
1036`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_POSITION 19
1037`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_FMASK 64'b0000000000000000000000000000000000000000000010000000000000000000
1038`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000010000000000000000000
1039`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_POR_VALUE 1'b0
1040`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_FID 23
1041`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_SLC 18:18
1042`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_WIDTH 1
1043`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_INT_SLC 0:0
1044`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_POSITION 18
1045`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000001000000000000000000
1046`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000001000000000000000000
1047`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_POR_VALUE 1'b0
1048`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_FID 24
1049`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_SLC 17:17
1050`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_WIDTH 1
1051`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_INT_SLC 0:0
1052`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_POSITION 17
1053`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000100000000000000000
1054`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000100000000000000000
1055`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_POR_VALUE 1'b0
1056`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_FID 25
1057`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_SLC 16:16
1058`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_WIDTH 1
1059`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_INT_SLC 0:0
1060`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_POSITION 16
1061`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_FMASK 64'b0000000000000000000000000000000000000000000000010000000000000000
1062`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000010000000000000000
1063`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_POR_VALUE 1'b0
1064`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_FID 26
1065`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_SLC 15:15
1066`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_WIDTH 1
1067`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_INT_SLC 0:0
1068`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_POSITION 15
1069`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
1070`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001000000000000000
1071`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_POR_VALUE 1'b0
1072`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_FID 27
1073`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_SLC 14:14
1074`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_WIDTH 1
1075`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_INT_SLC 0:0
1076`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_POSITION 14
1077`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000100000000000000
1078`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000100000000000000
1079`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_POR_VALUE 1'b0
1080`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_FID 28
1081`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_SLC 13:13
1082`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_WIDTH 1
1083`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_INT_SLC 0:0
1084`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_POSITION 13
1085`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
1086`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000010000000000000
1087`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_POR_VALUE 1'b0
1088`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_FID 29
1089`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_SLC 12:12
1090`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_WIDTH 1
1091`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_INT_SLC 0:0
1092`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_POSITION 12
1093`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
1094`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000001000000000000
1095`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_POR_VALUE 1'b0
1096`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_FID 30
1097`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_SLC 11:11
1098`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_WIDTH 1
1099`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_INT_SLC 0:0
1100`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_POSITION 11
1101`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_FMASK 64'b0000000000000000000000000000000000000000000000000000100000000000
1102`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000100000000000
1103`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_POR_VALUE 1'b0
1104`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_FID 31
1105`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_SLC 10:10
1106`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_WIDTH 1
1107`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_INT_SLC 0:0
1108`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_POSITION 10
1109`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_FMASK 64'b0000000000000000000000000000000000000000000000000000010000000000
1110`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000010000000000
1111`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_POR_VALUE 1'b0
1112`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_FID 32
1113`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_SLC 9:9
1114`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_WIDTH 1
1115`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_INT_SLC 0:0
1116`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_POSITION 9
1117`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
1118`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000001000000000
1119`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_POR_VALUE 1'b0
1120`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_FID 33
1121`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_SLC 8:8
1122`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_WIDTH 1
1123`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_INT_SLC 0:0
1124`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_POSITION 8
1125`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1126`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000100000000
1127`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_POR_VALUE 1'b0
1128`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_FID 34
1129`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_SLC 7:7
1130`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_WIDTH 1
1131`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_INT_SLC 0:0
1132`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_POSITION 7
1133`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
1134`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000
1135`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_POR_VALUE 1'b0
1136`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_FID 35
1137`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_SLC 6:6
1138`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_WIDTH 1
1139`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_INT_SLC 0:0
1140`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_POSITION 6
1141`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
1142`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001000000
1143`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_POR_VALUE 1'b0
1144`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_FID 36
1145`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_SLC 5:5
1146`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_WIDTH 1
1147`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_INT_SLC 0:0
1148`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_POSITION 5
1149`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
1150`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000100000
1151`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_POR_VALUE 1'b0
1152`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_FID 37
1153`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_SLC 4:4
1154`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_WIDTH 1
1155`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_INT_SLC 0:0
1156`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_POSITION 4
1157`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
1158`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000010000
1159`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_POR_VALUE 1'b0
1160`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_FID 38
1161`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_SLC 3:3
1162`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_WIDTH 1
1163`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_INT_SLC 0:0
1164`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_POSITION 3
1165`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000
1166`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000001000
1167`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_POR_VALUE 1'b0
1168`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_FID 39
1169`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_SLC 2:2
1170`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_WIDTH 1
1171`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_INT_SLC 0:0
1172`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_POSITION 2
1173`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1174`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1175`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_POR_VALUE 1'b0
1176`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_FID 40
1177`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_SLC 1:1
1178`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_WIDTH 1
1179`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_INT_SLC 0:0
1180`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_POSITION 1
1181`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1182`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1183`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_POR_VALUE 1'b0
1184`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_FID 41
1185`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_SLC 0:0
1186`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_WIDTH 1
1187`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_INT_SLC 0:0
1188`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_POSITION 0
1189`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1190`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1191`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_POR_VALUE 1'b0
1192
1193//-------------------------------------------------------
1194//----- Variable definitions for register fire_dlc_mmu_csr_flta
1195//-------------------------------------------------------
1196
1197`define FIRE_DLC_MMU_CSR_A_FLTA_HW_ADDR 27'b000000011001000001000000101
1198`define FIRE_DLC_MMU_CSR_A_FLTA_ADDR 30'b000000011001000001000000101000
1199`define FIRE_DLC_MMU_CSR_B_FLTA_HW_ADDR 27'b000000011101000001000000101
1200`define FIRE_DLC_MMU_CSR_B_FLTA_ADDR 30'b000000011101000001000000101000
1201
1202`define FIRE_DLC_MMU_CSR_FLTA_WIDTH 64
1203`define FIRE_DLC_MMU_CSR_FLTA_DEPTH 1
1204`define FIRE_DLC_MMU_CSR_FLTA_SLC 63:0
1205`define FIRE_DLC_MMU_CSR_FLTA_INT_SLC 63:0
1206`define FIRE_DLC_MMU_CSR_FLTA_POSITION 0
1207`define FIRE_DLC_MMU_CSR_FLTA_LOW_ADDR_WIDTH 0
1208`define FIRE_DLC_MMU_CSR_FLTA_ADDR_RANGE 26:0
1209`define FIRE_DLC_MMU_CSR_FLTA_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100
1210`define FIRE_DLC_MMU_CSR_FLTA_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1211`define FIRE_DLC_MMU_CSR_FLTA_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100
1212`define FIRE_DLC_MMU_CSR_FLTA_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1213`define FIRE_DLC_MMU_CSR_FLTA_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1214`define FIRE_DLC_MMU_CSR_FLTA_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1215`define FIRE_DLC_MMU_CSR_FLTA_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1216`define FIRE_DLC_MMU_CSR_FLTA_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111100
1217`define FIRE_DLC_MMU_CSR_FLTA_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
1218`define FIRE_DLC_MMU_CSR_FLTA_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100
1219`define FIRE_DLC_MMU_CSR_FLTA_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1220`define FIRE_DLC_MMU_CSR_FLTA_INTERNAL_REG 1
1221`define FIRE_DLC_MMU_CSR_FLTA_ZERO_TIME_OMNI 1
1222`define FIRE_DLC_MMU_CSR_FLTA_NUM_FIELDS 1
1223`define FIRE_DLC_MMU_CSR_FLTA_VA_FID 0
1224`define FIRE_DLC_MMU_CSR_FLTA_VA_SLC 63:2
1225`define FIRE_DLC_MMU_CSR_FLTA_VA_WIDTH 62
1226`define FIRE_DLC_MMU_CSR_FLTA_VA_INT_SLC 61:0
1227`define FIRE_DLC_MMU_CSR_FLTA_VA_POSITION 2
1228`define FIRE_DLC_MMU_CSR_FLTA_VA_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111100
1229`define FIRE_DLC_MMU_CSR_FLTA_VA_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100
1230`define FIRE_DLC_MMU_CSR_FLTA_VA_POR_VALUE 62'b00000000000000000000000000000000000000000000000000000000000000
1231
1232//-------------------------------------------------------
1233//----- Variable definitions for register fire_dlc_mmu_csr_flts
1234//-------------------------------------------------------
1235
1236`define FIRE_DLC_MMU_CSR_A_FLTS_HW_ADDR 27'b000000011001000001000000110
1237`define FIRE_DLC_MMU_CSR_A_FLTS_ADDR 30'b000000011001000001000000110000
1238`define FIRE_DLC_MMU_CSR_B_FLTS_HW_ADDR 27'b000000011101000001000000110
1239`define FIRE_DLC_MMU_CSR_B_FLTS_ADDR 30'b000000011101000001000000110000
1240
1241`define FIRE_DLC_MMU_CSR_FLTS_WIDTH 64
1242`define FIRE_DLC_MMU_CSR_FLTS_DEPTH 1
1243`define FIRE_DLC_MMU_CSR_FLTS_SLC 63:0
1244`define FIRE_DLC_MMU_CSR_FLTS_INT_SLC 63:0
1245`define FIRE_DLC_MMU_CSR_FLTS_POSITION 0
1246`define FIRE_DLC_MMU_CSR_FLTS_LOW_ADDR_WIDTH 0
1247`define FIRE_DLC_MMU_CSR_FLTS_ADDR_RANGE 26:0
1248`define FIRE_DLC_MMU_CSR_FLTS_READ_MASK 64'b0000000000000000000000011111111100000000011111111111111111111111
1249`define FIRE_DLC_MMU_CSR_FLTS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1250`define FIRE_DLC_MMU_CSR_FLTS_WRITE_MASK 64'b0000000000000000000000011111111100000000011111111111111111111111
1251`define FIRE_DLC_MMU_CSR_FLTS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1252`define FIRE_DLC_MMU_CSR_FLTS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1253`define FIRE_DLC_MMU_CSR_FLTS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1254`define FIRE_DLC_MMU_CSR_FLTS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1255`define FIRE_DLC_MMU_CSR_FLTS_RMASK 64'b0000000000000000000000011111111100000000011111111111111111111111
1256`define FIRE_DLC_MMU_CSR_FLTS_RESERVED_BIT_MASK 64'b1111111111111111111111100000000011111111100000000000000000000000
1257`define FIRE_DLC_MMU_CSR_FLTS_HW_LD_MASK 64'b0000000000000000000000011111111100000000011111111111111111111111
1258`define FIRE_DLC_MMU_CSR_FLTS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1259`define FIRE_DLC_MMU_CSR_FLTS_INTERNAL_REG 1
1260`define FIRE_DLC_MMU_CSR_FLTS_ZERO_TIME_OMNI 1
1261`define FIRE_DLC_MMU_CSR_FLTS_NUM_FIELDS 3
1262`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_FID 0
1263`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_SLC 40:32
1264`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_WIDTH 9
1265`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC 8:0
1266`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_POSITION 32
1267`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_FMASK 64'b0000000000000000000000011111111100000000000000000000000000000000
1268`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_HW_LD_MASK 64'b0000000000000000000000011111111100000000000000000000000000000000
1269`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_POR_VALUE 9'b000000000
1270`define FIRE_DLC_MMU_CSR_FLTS_TYPE_FID 1
1271`define FIRE_DLC_MMU_CSR_FLTS_TYPE_SLC 22:16
1272`define FIRE_DLC_MMU_CSR_FLTS_TYPE_WIDTH 7
1273`define FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC 6:0
1274`define FIRE_DLC_MMU_CSR_FLTS_TYPE_POSITION 16
1275`define FIRE_DLC_MMU_CSR_FLTS_TYPE_FMASK 64'b0000000000000000000000000000000000000000011111110000000000000000
1276`define FIRE_DLC_MMU_CSR_FLTS_TYPE_HW_LD_MASK 64'b0000000000000000000000000000000000000000011111110000000000000000
1277`define FIRE_DLC_MMU_CSR_FLTS_TYPE_POR_VALUE 7'b0000000
1278`define FIRE_DLC_MMU_CSR_FLTS_ID_FID 2
1279`define FIRE_DLC_MMU_CSR_FLTS_ID_SLC 15:0
1280`define FIRE_DLC_MMU_CSR_FLTS_ID_WIDTH 16
1281`define FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC 15:0
1282`define FIRE_DLC_MMU_CSR_FLTS_ID_POSITION 0
1283`define FIRE_DLC_MMU_CSR_FLTS_ID_FMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1284`define FIRE_DLC_MMU_CSR_FLTS_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1285`define FIRE_DLC_MMU_CSR_FLTS_ID_POR_VALUE 16'b0000000000000000
1286
1287//-------------------------------------------------------
1288//----- Variable definitions for register fire_dlc_mmu_csr_prfc
1289//-------------------------------------------------------
1290
1291`define FIRE_DLC_MMU_CSR_A_PRFC_HW_ADDR 27'b000000011001000010000000000
1292`define FIRE_DLC_MMU_CSR_A_PRFC_ADDR 30'b000000011001000010000000000000
1293`define FIRE_DLC_MMU_CSR_B_PRFC_HW_ADDR 27'b000000011101000010000000000
1294`define FIRE_DLC_MMU_CSR_B_PRFC_ADDR 30'b000000011101000010000000000000
1295
1296`define FIRE_DLC_MMU_CSR_PRFC_WIDTH 64
1297`define FIRE_DLC_MMU_CSR_PRFC_DEPTH 1
1298`define FIRE_DLC_MMU_CSR_PRFC_SLC 63:0
1299`define FIRE_DLC_MMU_CSR_PRFC_INT_SLC 63:0
1300`define FIRE_DLC_MMU_CSR_PRFC_POSITION 0
1301`define FIRE_DLC_MMU_CSR_PRFC_LOW_ADDR_WIDTH 0
1302`define FIRE_DLC_MMU_CSR_PRFC_ADDR_RANGE 26:0
1303`define FIRE_DLC_MMU_CSR_PRFC_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1304`define FIRE_DLC_MMU_CSR_PRFC_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1305`define FIRE_DLC_MMU_CSR_PRFC_WRITE_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1306`define FIRE_DLC_MMU_CSR_PRFC_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1307`define FIRE_DLC_MMU_CSR_PRFC_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1308`define FIRE_DLC_MMU_CSR_PRFC_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1309`define FIRE_DLC_MMU_CSR_PRFC_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1310`define FIRE_DLC_MMU_CSR_PRFC_RMASK 64'b0000000000000000000000000000000000000000000000001111111111111111
1311`define FIRE_DLC_MMU_CSR_PRFC_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
1312`define FIRE_DLC_MMU_CSR_PRFC_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1313`define FIRE_DLC_MMU_CSR_PRFC_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1314`define FIRE_DLC_MMU_CSR_PRFC_INTERNAL_REG 1
1315`define FIRE_DLC_MMU_CSR_PRFC_ZERO_TIME_OMNI 1
1316`define FIRE_DLC_MMU_CSR_PRFC_NUM_FIELDS 2
1317`define FIRE_DLC_MMU_CSR_PRFC_SEL1_FID 0
1318`define FIRE_DLC_MMU_CSR_PRFC_SEL1_SLC 15:8
1319`define FIRE_DLC_MMU_CSR_PRFC_SEL1_WIDTH 8
1320`define FIRE_DLC_MMU_CSR_PRFC_SEL1_INT_SLC 7:0
1321`define FIRE_DLC_MMU_CSR_PRFC_SEL1_POSITION 8
1322`define FIRE_DLC_MMU_CSR_PRFC_SEL1_FMASK 64'b0000000000000000000000000000000000000000000000001111111100000000
1323`define FIRE_DLC_MMU_CSR_PRFC_SEL1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1324`define FIRE_DLC_MMU_CSR_PRFC_SEL1_POR_VALUE 8'b00000000
1325`define FIRE_DLC_MMU_CSR_PRFC_SEL0_FID 1
1326`define FIRE_DLC_MMU_CSR_PRFC_SEL0_SLC 7:0
1327`define FIRE_DLC_MMU_CSR_PRFC_SEL0_WIDTH 8
1328`define FIRE_DLC_MMU_CSR_PRFC_SEL0_INT_SLC 7:0
1329`define FIRE_DLC_MMU_CSR_PRFC_SEL0_POSITION 0
1330`define FIRE_DLC_MMU_CSR_PRFC_SEL0_FMASK 64'b0000000000000000000000000000000000000000000000000000000011111111
1331`define FIRE_DLC_MMU_CSR_PRFC_SEL0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1332`define FIRE_DLC_MMU_CSR_PRFC_SEL0_POR_VALUE 8'b00000000
1333
1334//-------------------------------------------------------
1335//----- Variable definitions for register fire_dlc_mmu_csr_prf0
1336//-------------------------------------------------------
1337
1338`define FIRE_DLC_MMU_CSR_A_PRF0_HW_ADDR 27'b000000011001000010000000001
1339`define FIRE_DLC_MMU_CSR_A_PRF0_ADDR 30'b000000011001000010000000001000
1340`define FIRE_DLC_MMU_CSR_B_PRF0_HW_ADDR 27'b000000011101000010000000001
1341`define FIRE_DLC_MMU_CSR_B_PRF0_ADDR 30'b000000011101000010000000001000
1342
1343`define FIRE_DLC_MMU_CSR_PRF0_WIDTH 64
1344`define FIRE_DLC_MMU_CSR_PRF0_DEPTH 1
1345`define FIRE_DLC_MMU_CSR_PRF0_SLC 63:0
1346`define FIRE_DLC_MMU_CSR_PRF0_INT_SLC 63:0
1347`define FIRE_DLC_MMU_CSR_PRF0_POSITION 0
1348`define FIRE_DLC_MMU_CSR_PRF0_LOW_ADDR_WIDTH 0
1349`define FIRE_DLC_MMU_CSR_PRF0_ADDR_RANGE 26:0
1350`define FIRE_DLC_MMU_CSR_PRF0_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1351`define FIRE_DLC_MMU_CSR_PRF0_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1352`define FIRE_DLC_MMU_CSR_PRF0_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1353`define FIRE_DLC_MMU_CSR_PRF0_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1354`define FIRE_DLC_MMU_CSR_PRF0_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1355`define FIRE_DLC_MMU_CSR_PRF0_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1356`define FIRE_DLC_MMU_CSR_PRF0_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1357`define FIRE_DLC_MMU_CSR_PRF0_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1358`define FIRE_DLC_MMU_CSR_PRF0_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1359`define FIRE_DLC_MMU_CSR_PRF0_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1360`define FIRE_DLC_MMU_CSR_PRF0_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1361`define FIRE_DLC_MMU_CSR_PRF0_INTERNAL_REG 1
1362`define FIRE_DLC_MMU_CSR_PRF0_ZERO_TIME_OMNI 1
1363`define FIRE_DLC_MMU_CSR_PRF0_NUM_FIELDS 1
1364`define FIRE_DLC_MMU_CSR_PRF0_CNT_FID 0
1365`define FIRE_DLC_MMU_CSR_PRF0_CNT_SLC 63:0
1366`define FIRE_DLC_MMU_CSR_PRF0_CNT_WIDTH 64
1367`define FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC 63:0
1368`define FIRE_DLC_MMU_CSR_PRF0_CNT_POSITION 0
1369`define FIRE_DLC_MMU_CSR_PRF0_CNT_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1370`define FIRE_DLC_MMU_CSR_PRF0_CNT_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1371`define FIRE_DLC_MMU_CSR_PRF0_CNT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1372
1373//-------------------------------------------------------
1374//----- Variable definitions for register fire_dlc_mmu_csr_prf1
1375//-------------------------------------------------------
1376
1377`define FIRE_DLC_MMU_CSR_A_PRF1_HW_ADDR 27'b000000011001000010000000010
1378`define FIRE_DLC_MMU_CSR_A_PRF1_ADDR 30'b000000011001000010000000010000
1379`define FIRE_DLC_MMU_CSR_B_PRF1_HW_ADDR 27'b000000011101000010000000010
1380`define FIRE_DLC_MMU_CSR_B_PRF1_ADDR 30'b000000011101000010000000010000
1381
1382`define FIRE_DLC_MMU_CSR_PRF1_WIDTH 64
1383`define FIRE_DLC_MMU_CSR_PRF1_DEPTH 1
1384`define FIRE_DLC_MMU_CSR_PRF1_SLC 63:0
1385`define FIRE_DLC_MMU_CSR_PRF1_INT_SLC 63:0
1386`define FIRE_DLC_MMU_CSR_PRF1_POSITION 0
1387`define FIRE_DLC_MMU_CSR_PRF1_LOW_ADDR_WIDTH 0
1388`define FIRE_DLC_MMU_CSR_PRF1_ADDR_RANGE 26:0
1389`define FIRE_DLC_MMU_CSR_PRF1_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1390`define FIRE_DLC_MMU_CSR_PRF1_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1391`define FIRE_DLC_MMU_CSR_PRF1_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1392`define FIRE_DLC_MMU_CSR_PRF1_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1393`define FIRE_DLC_MMU_CSR_PRF1_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1394`define FIRE_DLC_MMU_CSR_PRF1_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1395`define FIRE_DLC_MMU_CSR_PRF1_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1396`define FIRE_DLC_MMU_CSR_PRF1_RMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1397`define FIRE_DLC_MMU_CSR_PRF1_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1398`define FIRE_DLC_MMU_CSR_PRF1_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1399`define FIRE_DLC_MMU_CSR_PRF1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1400`define FIRE_DLC_MMU_CSR_PRF1_INTERNAL_REG 1
1401`define FIRE_DLC_MMU_CSR_PRF1_ZERO_TIME_OMNI 1
1402`define FIRE_DLC_MMU_CSR_PRF1_NUM_FIELDS 1
1403`define FIRE_DLC_MMU_CSR_PRF1_CNT_FID 0
1404`define FIRE_DLC_MMU_CSR_PRF1_CNT_SLC 63:0
1405`define FIRE_DLC_MMU_CSR_PRF1_CNT_WIDTH 64
1406`define FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC 63:0
1407`define FIRE_DLC_MMU_CSR_PRF1_CNT_POSITION 0
1408`define FIRE_DLC_MMU_CSR_PRF1_CNT_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1409`define FIRE_DLC_MMU_CSR_PRF1_CNT_HW_LD_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
1410`define FIRE_DLC_MMU_CSR_PRF1_CNT_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1411
1412//-------------------------------------------------------
1413//----- Variable definitions for register fire_dlc_mmu_csr_vtb
1414//-------------------------------------------------------
1415
1416`define FIRE_DLC_MMU_CSR_A_VTB_HW_ADDR 27'b000000011001000110000000000
1417`define FIRE_DLC_MMU_CSR_A_VTB_ADDR 30'b000000011001000110000000000000
1418`define FIRE_DLC_MMU_CSR_B_VTB_HW_ADDR 27'b000000011101000110000000000
1419`define FIRE_DLC_MMU_CSR_B_VTB_ADDR 30'b000000011101000110000000000000
1420
1421`define FIRE_DLC_MMU_CSR_VTB_WIDTH 64
1422`define FIRE_DLC_MMU_CSR_VTB_DEPTH 64
1423`define FIRE_DLC_MMU_CSR_VTB_SLC 63:0
1424`define FIRE_DLC_MMU_CSR_VTB_INT_SLC 63:0
1425`define FIRE_DLC_MMU_CSR_VTB_POSITION 0
1426`define FIRE_DLC_MMU_CSR_VTB_LOW_ADDR_WIDTH 6
1427`define FIRE_DLC_MMU_CSR_VTB_SEL_RANGE 5:0
1428`define FIRE_DLC_MMU_CSR_VTB_ADDR_RANGE 26:6
1429`define FIRE_DLC_MMU_CSR_VTB_READ_MASK 64'b0000000111111111111111111111111111111111111111111111100000000001
1430`define FIRE_DLC_MMU_CSR_VTB_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1431`define FIRE_DLC_MMU_CSR_VTB_WRITE_MASK 64'b0000000111111111111111111111111111111111111111111111100000000001
1432`define FIRE_DLC_MMU_CSR_VTB_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1433`define FIRE_DLC_MMU_CSR_VTB_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1434`define FIRE_DLC_MMU_CSR_VTB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1435`define FIRE_DLC_MMU_CSR_VTB_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1436`define FIRE_DLC_MMU_CSR_VTB_RMASK 64'b0000000111111111111111111111111111111111111111111111100000000001
1437`define FIRE_DLC_MMU_CSR_VTB_RESERVED_BIT_MASK 64'b1111111000000000000000000000000000000000000000000000011111111110
1438`define FIRE_DLC_MMU_CSR_VTB_HW_LD_MASK 64'b0000000111111111111111111111111111111111111111111111100000000001
1439`define FIRE_DLC_MMU_CSR_VTB_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1440`define FIRE_DLC_MMU_CSR_VTB_INTERNAL_REG 0
1441`define FIRE_DLC_MMU_CSR_VTB_EXTERNAL_DECODE_REG 0
1442`define FIRE_DLC_MMU_CSR_VTB_ZERO_TIME_OMNI 0
1443`define FIRE_DLC_MMU_CSR_VTB_NUM_FIELDS 4
1444`define FIRE_DLC_MMU_CSR_VTB_CNT_FID 0
1445`define FIRE_DLC_MMU_CSR_VTB_CNT_SLC 56:40
1446`define FIRE_DLC_MMU_CSR_VTB_CNT_WIDTH 17
1447`define FIRE_DLC_MMU_CSR_VTB_CNT_INT_SLC 16:0
1448`define FIRE_DLC_MMU_CSR_VTB_CNT_POSITION 40
1449`define FIRE_DLC_MMU_CSR_VTB_CNT_FMASK 64'b0000000111111111111111110000000000000000000000000000000000000000
1450`define FIRE_DLC_MMU_CSR_VTB_CNT_HW_LD_MASK 64'b0000000111111111111111110000000000000000000000000000000000000000
1451`define FIRE_DLC_MMU_CSR_VTB_CNT_POR_VALUE 17'b00000000000000000
1452`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_FID 1
1453`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_SLC 39:16
1454`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_WIDTH 24
1455`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_INT_SLC 23:0
1456`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_POSITION 16
1457`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_FMASK 64'b0000000000000000000000001111111111111111111111110000000000000000
1458`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_HW_LD_MASK 64'b0000000000000000000000001111111111111111111111110000000000000000
1459`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_POR_VALUE 24'b000000000000000000000000
1460`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_FID 2
1461`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_SLC 15:11
1462`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_WIDTH 5
1463`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_INT_SLC 4:0
1464`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_POSITION 11
1465`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_FMASK 64'b0000000000000000000000000000000000000000000000001111100000000000
1466`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000001111100000000000
1467`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_POR_VALUE 5'b00000
1468`define FIRE_DLC_MMU_CSR_VTB_VLD_FID 3
1469`define FIRE_DLC_MMU_CSR_VTB_VLD_SLC 0:0
1470`define FIRE_DLC_MMU_CSR_VTB_VLD_WIDTH 1
1471`define FIRE_DLC_MMU_CSR_VTB_VLD_INT_SLC 0:0
1472`define FIRE_DLC_MMU_CSR_VTB_VLD_POSITION 0
1473`define FIRE_DLC_MMU_CSR_VTB_VLD_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1474`define FIRE_DLC_MMU_CSR_VTB_VLD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1475`define FIRE_DLC_MMU_CSR_VTB_VLD_POR_VALUE 1'b0
1476
1477//-------------------------------------------------------
1478//----- Variable definitions for register fire_dlc_mmu_csr_ptb
1479//-------------------------------------------------------
1480
1481`define FIRE_DLC_MMU_CSR_A_PTB_HW_ADDR 27'b000000011001000111000000000
1482`define FIRE_DLC_MMU_CSR_A_PTB_ADDR 30'b000000011001000111000000000000
1483`define FIRE_DLC_MMU_CSR_B_PTB_HW_ADDR 27'b000000011101000111000000000
1484`define FIRE_DLC_MMU_CSR_B_PTB_ADDR 30'b000000011101000111000000000000
1485
1486`define FIRE_DLC_MMU_CSR_PTB_WIDTH 64
1487`define FIRE_DLC_MMU_CSR_PTB_DEPTH 64
1488`define FIRE_DLC_MMU_CSR_PTB_SLC 63:0
1489`define FIRE_DLC_MMU_CSR_PTB_INT_SLC 63:0
1490`define FIRE_DLC_MMU_CSR_PTB_POSITION 0
1491`define FIRE_DLC_MMU_CSR_PTB_LOW_ADDR_WIDTH 6
1492`define FIRE_DLC_MMU_CSR_PTB_SEL_RANGE 5:0
1493`define FIRE_DLC_MMU_CSR_PTB_ADDR_RANGE 26:6
1494`define FIRE_DLC_MMU_CSR_PTB_READ_MASK 64'b0000000000000000000000000111111111111111111111111111111111000001
1495`define FIRE_DLC_MMU_CSR_PTB_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1496`define FIRE_DLC_MMU_CSR_PTB_WRITE_MASK 64'b0000000000000000000000000111111111111111111111111111111111000001
1497`define FIRE_DLC_MMU_CSR_PTB_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1498`define FIRE_DLC_MMU_CSR_PTB_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1499`define FIRE_DLC_MMU_CSR_PTB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1500`define FIRE_DLC_MMU_CSR_PTB_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1501`define FIRE_DLC_MMU_CSR_PTB_RMASK 64'b0000000000000000000000000111111111111111111111111111111111000001
1502`define FIRE_DLC_MMU_CSR_PTB_RESERVED_BIT_MASK 64'b1111111111111111111111111000000000000000000000000000000000111110
1503`define FIRE_DLC_MMU_CSR_PTB_HW_LD_MASK 64'b0000000000000000000000000111111111111111111111111111111111000001
1504`define FIRE_DLC_MMU_CSR_PTB_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1505`define FIRE_DLC_MMU_CSR_PTB_INTERNAL_REG 0
1506`define FIRE_DLC_MMU_CSR_PTB_EXTERNAL_DECODE_REG 0
1507`define FIRE_DLC_MMU_CSR_PTB_ZERO_TIME_OMNI 0
1508`define FIRE_DLC_MMU_CSR_PTB_NUM_FIELDS 2
1509`define FIRE_DLC_MMU_CSR_PTB_TAG_FID 0
1510`define FIRE_DLC_MMU_CSR_PTB_TAG_SLC 38:6
1511`define FIRE_DLC_MMU_CSR_PTB_TAG_WIDTH 33
1512`define FIRE_DLC_MMU_CSR_PTB_TAG_INT_SLC 32:0
1513`define FIRE_DLC_MMU_CSR_PTB_TAG_POSITION 6
1514`define FIRE_DLC_MMU_CSR_PTB_TAG_FMASK 64'b0000000000000000000000000111111111111111111111111111111111000000
1515`define FIRE_DLC_MMU_CSR_PTB_TAG_HW_LD_MASK 64'b0000000000000000000000000111111111111111111111111111111111000000
1516`define FIRE_DLC_MMU_CSR_PTB_TAG_POR_VALUE 33'b000000000000000000000000000000000
1517`define FIRE_DLC_MMU_CSR_PTB_VLD_FID 1
1518`define FIRE_DLC_MMU_CSR_PTB_VLD_SLC 0:0
1519`define FIRE_DLC_MMU_CSR_PTB_VLD_WIDTH 1
1520`define FIRE_DLC_MMU_CSR_PTB_VLD_INT_SLC 0:0
1521`define FIRE_DLC_MMU_CSR_PTB_VLD_POSITION 0
1522`define FIRE_DLC_MMU_CSR_PTB_VLD_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1523`define FIRE_DLC_MMU_CSR_PTB_VLD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1524`define FIRE_DLC_MMU_CSR_PTB_VLD_POR_VALUE 1'b0
1525
1526//-------------------------------------------------------
1527//----- Variable definitions for register fire_dlc_mmu_csr_tdb
1528//-------------------------------------------------------
1529
1530`define FIRE_DLC_MMU_CSR_A_TDB_HW_ADDR 27'b000000011001001000000000000
1531`define FIRE_DLC_MMU_CSR_A_TDB_ADDR 30'b000000011001001000000000000000
1532`define FIRE_DLC_MMU_CSR_B_TDB_HW_ADDR 27'b000000011101001000000000000
1533`define FIRE_DLC_MMU_CSR_B_TDB_ADDR 30'b000000011101001000000000000000
1534
1535`define FIRE_DLC_MMU_CSR_TDB_WIDTH 64
1536`define FIRE_DLC_MMU_CSR_TDB_DEPTH 512
1537`define FIRE_DLC_MMU_CSR_TDB_SLC 63:0
1538`define FIRE_DLC_MMU_CSR_TDB_INT_SLC 63:0
1539`define FIRE_DLC_MMU_CSR_TDB_POSITION 0
1540`define FIRE_DLC_MMU_CSR_TDB_LOW_ADDR_WIDTH 9
1541`define FIRE_DLC_MMU_CSR_TDB_SEL_RANGE 8:0
1542`define FIRE_DLC_MMU_CSR_TDB_ADDR_RANGE 26:9
1543`define FIRE_DLC_MMU_CSR_TDB_READ_MASK 64'b1111111111111111111100000111111111111111111111111110000000111111
1544`define FIRE_DLC_MMU_CSR_TDB_READ_ONLY_MASK 64'b0000000000000000111100000000000000000000000000000000000000000000
1545`define FIRE_DLC_MMU_CSR_TDB_WRITE_MASK 64'b1111111111111111000000000111111111111111111111111110000000111111
1546`define FIRE_DLC_MMU_CSR_TDB_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1547`define FIRE_DLC_MMU_CSR_TDB_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1548`define FIRE_DLC_MMU_CSR_TDB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1549`define FIRE_DLC_MMU_CSR_TDB_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1550`define FIRE_DLC_MMU_CSR_TDB_RMASK 64'b1111111111111111111100000111111111111111111111111110000000111111
1551`define FIRE_DLC_MMU_CSR_TDB_RESERVED_BIT_MASK 64'b0000000000000000000011111000000000000000000000000001111111000000
1552`define FIRE_DLC_MMU_CSR_TDB_HW_LD_MASK 64'b1111111111111111111100000111111111111111111111111110000000111111
1553`define FIRE_DLC_MMU_CSR_TDB_POR_VALUE 64'bxxxxxxxxxxxxxxxxxxxx00000xxxxxxxxxxxxxxxxxxxxxxxxxx0000000xxxxxx
1554`define FIRE_DLC_MMU_CSR_TDB_INTERNAL_REG 0
1555`define FIRE_DLC_MMU_CSR_TDB_EXTERNAL_DECODE_REG 0
1556`define FIRE_DLC_MMU_CSR_TDB_ZERO_TIME_OMNI 0
1557`define FIRE_DLC_MMU_CSR_TDB_NUM_FIELDS 7
1558`define FIRE_DLC_MMU_CSR_TDB_KEY_FID 0
1559`define FIRE_DLC_MMU_CSR_TDB_KEY_SLC 63:48
1560`define FIRE_DLC_MMU_CSR_TDB_KEY_WIDTH 16
1561`define FIRE_DLC_MMU_CSR_TDB_KEY_INT_SLC 15:0
1562`define FIRE_DLC_MMU_CSR_TDB_KEY_POSITION 48
1563`define FIRE_DLC_MMU_CSR_TDB_KEY_FMASK 64'b1111111111111111000000000000000000000000000000000000000000000000
1564`define FIRE_DLC_MMU_CSR_TDB_KEY_HW_LD_MASK 64'b1111111111111111000000000000000000000000000000000000000000000000
1565`define FIRE_DLC_MMU_CSR_TDB_KEY_POR_VALUE 16'bxxxxxxxxxxxxxxxx
1566`define FIRE_DLC_MMU_CSR_TDB_PAR_FID 1
1567`define FIRE_DLC_MMU_CSR_TDB_PAR_SLC 47:44
1568`define FIRE_DLC_MMU_CSR_TDB_PAR_WIDTH 4
1569`define FIRE_DLC_MMU_CSR_TDB_PAR_INT_SLC 3:0
1570`define FIRE_DLC_MMU_CSR_TDB_PAR_POSITION 44
1571`define FIRE_DLC_MMU_CSR_TDB_PAR_FMASK 64'b0000000000000000111100000000000000000000000000000000000000000000
1572`define FIRE_DLC_MMU_CSR_TDB_PAR_HW_LD_MASK 64'b0000000000000000111100000000000000000000000000000000000000000000
1573`define FIRE_DLC_MMU_CSR_TDB_PAR_POR_VALUE 4'bxxxx
1574`define FIRE_DLC_MMU_CSR_TDB_PPN_FID 2
1575`define FIRE_DLC_MMU_CSR_TDB_PPN_SLC 38:13
1576`define FIRE_DLC_MMU_CSR_TDB_PPN_WIDTH 26
1577`define FIRE_DLC_MMU_CSR_TDB_PPN_INT_SLC 25:0
1578`define FIRE_DLC_MMU_CSR_TDB_PPN_POSITION 13
1579`define FIRE_DLC_MMU_CSR_TDB_PPN_FMASK 64'b0000000000000000000000000111111111111111111111111110000000000000
1580`define FIRE_DLC_MMU_CSR_TDB_PPN_HW_LD_MASK 64'b0000000000000000000000000111111111111111111111111110000000000000
1581`define FIRE_DLC_MMU_CSR_TDB_PPN_POR_VALUE 26'bxxxxxxxxxxxxxxxxxxxxxxxxxx
1582`define FIRE_DLC_MMU_CSR_TDB_FNM_FID 3
1583`define FIRE_DLC_MMU_CSR_TDB_FNM_SLC 5:3
1584`define FIRE_DLC_MMU_CSR_TDB_FNM_WIDTH 3
1585`define FIRE_DLC_MMU_CSR_TDB_FNM_INT_SLC 2:0
1586`define FIRE_DLC_MMU_CSR_TDB_FNM_POSITION 3
1587`define FIRE_DLC_MMU_CSR_TDB_FNM_FMASK 64'b0000000000000000000000000000000000000000000000000000000000111000
1588`define FIRE_DLC_MMU_CSR_TDB_FNM_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000111000
1589`define FIRE_DLC_MMU_CSR_TDB_FNM_POR_VALUE 3'bxxx
1590`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_FID 4
1591`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_SLC 2:2
1592`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_WIDTH 1
1593`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_INT_SLC 0:0
1594`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_POSITION 2
1595`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1596`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
1597`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_POR_VALUE 1'bx
1598`define FIRE_DLC_MMU_CSR_TDB_WRT_FID 5
1599`define FIRE_DLC_MMU_CSR_TDB_WRT_SLC 1:1
1600`define FIRE_DLC_MMU_CSR_TDB_WRT_WIDTH 1
1601`define FIRE_DLC_MMU_CSR_TDB_WRT_INT_SLC 0:0
1602`define FIRE_DLC_MMU_CSR_TDB_WRT_POSITION 1
1603`define FIRE_DLC_MMU_CSR_TDB_WRT_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1604`define FIRE_DLC_MMU_CSR_TDB_WRT_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000010
1605`define FIRE_DLC_MMU_CSR_TDB_WRT_POR_VALUE 1'bx
1606`define FIRE_DLC_MMU_CSR_TDB_VLD_FID 6
1607`define FIRE_DLC_MMU_CSR_TDB_VLD_SLC 0:0
1608`define FIRE_DLC_MMU_CSR_TDB_VLD_WIDTH 1
1609`define FIRE_DLC_MMU_CSR_TDB_VLD_INT_SLC 0:0
1610`define FIRE_DLC_MMU_CSR_TDB_VLD_POSITION 0
1611`define FIRE_DLC_MMU_CSR_TDB_VLD_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1612`define FIRE_DLC_MMU_CSR_TDB_VLD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001
1613`define FIRE_DLC_MMU_CSR_TDB_VLD_POR_VALUE 1'bx
1614
1615//-------------------------------------------------------
1616//----- Variable definitions for register fire_dlc_mmu_csr_dev2iotsb
1617//-------------------------------------------------------
1618
1619`define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_HW_ADDR 27'b000000011001001001000000000
1620`define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR 30'b000000011001001001000000000000
1621`define FIRE_DLC_MMU_CSR_B_DEV2IOTSB_HW_ADDR 27'b000000011101001001000000000
1622`define FIRE_DLC_MMU_CSR_B_DEV2IOTSB_ADDR 30'b000000011101001001000000000000
1623
1624`define FIRE_DLC_MMU_CSR_DEV2IOTSB_WIDTH 64
1625`define FIRE_DLC_MMU_CSR_DEV2IOTSB_DEPTH 16
1626`define FIRE_DLC_MMU_CSR_DEV2IOTSB_SLC 63:0
1627`define FIRE_DLC_MMU_CSR_DEV2IOTSB_INT_SLC 63:0
1628`define FIRE_DLC_MMU_CSR_DEV2IOTSB_POSITION 0
1629`define FIRE_DLC_MMU_CSR_DEV2IOTSB_LOW_ADDR_WIDTH 4
1630`define FIRE_DLC_MMU_CSR_DEV2IOTSB_SEL_RANGE 3:0
1631`define FIRE_DLC_MMU_CSR_DEV2IOTSB_ADDR_RANGE 26:4
1632`define FIRE_DLC_MMU_CSR_DEV2IOTSB_READ_MASK 64'b0001111100011111000111110001111100011111000111110001111100011111
1633`define FIRE_DLC_MMU_CSR_DEV2IOTSB_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1634`define FIRE_DLC_MMU_CSR_DEV2IOTSB_WRITE_MASK 64'b0001111100011111000111110001111100011111000111110001111100011111
1635`define FIRE_DLC_MMU_CSR_DEV2IOTSB_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1636`define FIRE_DLC_MMU_CSR_DEV2IOTSB_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1637`define FIRE_DLC_MMU_CSR_DEV2IOTSB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1638`define FIRE_DLC_MMU_CSR_DEV2IOTSB_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1639`define FIRE_DLC_MMU_CSR_DEV2IOTSB_RMASK 64'b0001111100011111000111110001111100011111000111110001111100011111
1640`define FIRE_DLC_MMU_CSR_DEV2IOTSB_RESERVED_BIT_MASK 64'b1110000011100000111000001110000011100000111000001110000011100000
1641`define FIRE_DLC_MMU_CSR_DEV2IOTSB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1642`define FIRE_DLC_MMU_CSR_DEV2IOTSB_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1643`define FIRE_DLC_MMU_CSR_DEV2IOTSB_INTERNAL_REG 0
1644`define FIRE_DLC_MMU_CSR_DEV2IOTSB_EXTERNAL_DECODE_REG 0
1645`define FIRE_DLC_MMU_CSR_DEV2IOTSB_ZERO_TIME_OMNI 0
1646`define FIRE_DLC_MMU_CSR_DEV2IOTSB_NUM_FIELDS 8
1647`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_FID 0
1648`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_SLC 60:56
1649`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_WIDTH 5
1650`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_INT_SLC 4:0
1651`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_POSITION 56
1652`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_FMASK 64'b0001111100000000000000000000000000000000000000000000000000000000
1653`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1654`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_POR_VALUE 5'b00000
1655`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_FID 1
1656`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_SLC 52:48
1657`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_WIDTH 5
1658`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_INT_SLC 4:0
1659`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_POSITION 48
1660`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_FMASK 64'b0000000000011111000000000000000000000000000000000000000000000000
1661`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1662`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_POR_VALUE 5'b00000
1663`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_FID 2
1664`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_SLC 44:40
1665`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_WIDTH 5
1666`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_INT_SLC 4:0
1667`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_POSITION 40
1668`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_FMASK 64'b0000000000000000000111110000000000000000000000000000000000000000
1669`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1670`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_POR_VALUE 5'b00000
1671`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_FID 3
1672`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_SLC 36:32
1673`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_WIDTH 5
1674`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_INT_SLC 4:0
1675`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_POSITION 32
1676`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_FMASK 64'b0000000000000000000000000001111100000000000000000000000000000000
1677`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1678`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_POR_VALUE 5'b00000
1679`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_FID 4
1680`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_SLC 28:24
1681`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_WIDTH 5
1682`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_INT_SLC 4:0
1683`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_POSITION 24
1684`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_FMASK 64'b0000000000000000000000000000000000011111000000000000000000000000
1685`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1686`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_POR_VALUE 5'b00000
1687`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_FID 5
1688`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_SLC 20:16
1689`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_WIDTH 5
1690`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_INT_SLC 4:0
1691`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_POSITION 16
1692`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_FMASK 64'b0000000000000000000000000000000000000000000111110000000000000000
1693`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1694`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_POR_VALUE 5'b00000
1695`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_FID 6
1696`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_SLC 12:8
1697`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_WIDTH 5
1698`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_INT_SLC 4:0
1699`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_POSITION 8
1700`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_FMASK 64'b0000000000000000000000000000000000000000000000000001111100000000
1701`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1702`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_POR_VALUE 5'b00000
1703`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_FID 7
1704`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_SLC 4:0
1705`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_WIDTH 5
1706`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_INT_SLC 4:0
1707`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_POSITION 0
1708`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_FMASK 64'b0000000000000000000000000000000000000000000000000000000000011111
1709`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1710`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_POR_VALUE 5'b00000
1711
1712//-------------------------------------------------------
1713//----- Variable definitions for register fire_dlc_mmu_csr_IotsbDesc
1714//-------------------------------------------------------
1715
1716`define FIRE_DLC_MMU_CSR_A_IOTSBDESC_HW_ADDR 27'b000000011001001001000100000
1717`define FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR 30'b000000011001001001000100000000
1718`define FIRE_DLC_MMU_CSR_B_IOTSBDESC_HW_ADDR 27'b000000011101001001000100000
1719`define FIRE_DLC_MMU_CSR_B_IOTSBDESC_ADDR 30'b000000011101001001000100000000
1720
1721`define FIRE_DLC_MMU_CSR_IOTSBDESC_WIDTH 64
1722`define FIRE_DLC_MMU_CSR_IOTSBDESC_DEPTH 32
1723`define FIRE_DLC_MMU_CSR_IOTSBDESC_SLC 63:0
1724`define FIRE_DLC_MMU_CSR_IOTSBDESC_INT_SLC 63:0
1725`define FIRE_DLC_MMU_CSR_IOTSBDESC_POSITION 0
1726`define FIRE_DLC_MMU_CSR_IOTSBDESC_LOW_ADDR_WIDTH 5
1727`define FIRE_DLC_MMU_CSR_IOTSBDESC_SEL_RANGE 4:0
1728`define FIRE_DLC_MMU_CSR_IOTSBDESC_ADDR_RANGE 26:5
1729`define FIRE_DLC_MMU_CSR_IOTSBDESC_READ_MASK 64'b1110111111111111111111111111111111111111111111111111111111111111
1730`define FIRE_DLC_MMU_CSR_IOTSBDESC_READ_ONLY_MASK 64'b0110000000000000000000000000000000000000000000000000000000000000
1731`define FIRE_DLC_MMU_CSR_IOTSBDESC_WRITE_MASK 64'b1000111111111111111111111111111111111111111111111111111111111111
1732`define FIRE_DLC_MMU_CSR_IOTSBDESC_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1733`define FIRE_DLC_MMU_CSR_IOTSBDESC_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1734`define FIRE_DLC_MMU_CSR_IOTSBDESC_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1735`define FIRE_DLC_MMU_CSR_IOTSBDESC_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1736`define FIRE_DLC_MMU_CSR_IOTSBDESC_RMASK 64'b1110111111111111111111111111111111111111111111111111111111111111
1737`define FIRE_DLC_MMU_CSR_IOTSBDESC_RESERVED_BIT_MASK 64'b0001000000000000000000000000000000000000000000000000000000000000
1738`define FIRE_DLC_MMU_CSR_IOTSBDESC_HW_LD_MASK 64'b0110000000000000000000000000000000000000000000000000000000000000
1739`define FIRE_DLC_MMU_CSR_IOTSBDESC_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
1740`define FIRE_DLC_MMU_CSR_IOTSBDESC_INTERNAL_REG 0
1741`define FIRE_DLC_MMU_CSR_IOTSBDESC_EXTERNAL_DECODE_REG 0
1742`define FIRE_DLC_MMU_CSR_IOTSBDESC_ZERO_TIME_OMNI 0
1743`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_FIELDS 6
1744`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_FID 0
1745`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_SLC 63:63
1746`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_WIDTH 1
1747`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_INT_SLC 0:0
1748`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_POSITION 63
1749`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_FMASK 64'b1000000000000000000000000000000000000000000000000000000000000000
1750`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1751`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_POR_VALUE 1'b0
1752`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_FID 1
1753`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_SLC 62:61
1754`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_WIDTH 2
1755`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_INT_SLC 1:0
1756`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_POSITION 61
1757`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_FMASK 64'b0110000000000000000000000000000000000000000000000000000000000000
1758`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_HW_LD_MASK 64'b0110000000000000000000000000000000000000000000000000000000000000
1759`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_POR_VALUE 2'b00
1760`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_FID 2
1761`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_SLC 59:34
1762`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_WIDTH 26
1763`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_INT_SLC 25:0
1764`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_POSITION 34
1765`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_FMASK 64'b0000111111111111111111111111110000000000000000000000000000000000
1766`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1767`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_POR_VALUE 26'b00000000000000000000000000
1768`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_FID 3
1769`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_SLC 33:7
1770`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_WIDTH 27
1771`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_INT_SLC 26:0
1772`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_POSITION 7
1773`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_FMASK 64'b0000000000000000000000000000001111111111111111111111111110000000
1774`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1775`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_POR_VALUE 27'b000000000000000000000000000
1776`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_FID 4
1777`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_SLC 6:4
1778`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_WIDTH 3
1779`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_INT_SLC 2:0
1780`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_POSITION 4
1781`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_FMASK 64'b0000000000000000000000000000000000000000000000000000000001110000
1782`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1783`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_POR_VALUE 3'b000
1784`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_FID 5
1785`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_SLC 3:0
1786`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_WIDTH 4
1787`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_INT_SLC 3:0
1788`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_POSITION 0
1789`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001111
1790`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
1791`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_POR_VALUE 4'b0000
1792
1793
1794`endif
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