design/sys/iop/dmu/rtl/dmu_mmu_csr_defines.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_mmu_csr_defines.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
`ifdef FIRE_DLC_MMU_CSR_DEFINES
`else
`define FIRE_DLC_MMU_CSR_DEFINES

`define FIRE_DLC_MMU_CSR_CSRBUS_EXT_ADDR_WIDTH  9
`define FIRE_DLC_MMU_CSR_CSRBUS_EXT_ADDR_RANGE  8:0

`define FIRE_DLC_MMU_CSR_INSTANCE_ID_VALUE_A 1'h0
`define FIRE_DLC_MMU_CSR_INSTANCE_ID_VALUE_B 1'h1

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_ctl
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_CTL_HW_ADDR  27'b000000011001000000000000000
`define FIRE_DLC_MMU_CSR_A_CTL_ADDR     30'b000000011001000000000000000000
`define FIRE_DLC_MMU_CSR_B_CTL_HW_ADDR  27'b000000011101000000000000000
`define FIRE_DLC_MMU_CSR_B_CTL_ADDR     30'b000000011101000000000000000000

`define FIRE_DLC_MMU_CSR_CTL_WIDTH      64
`define FIRE_DLC_MMU_CSR_CTL_DEPTH      1
`define FIRE_DLC_MMU_CSR_CTL_SLC        63:0
`define FIRE_DLC_MMU_CSR_CTL_INT_SLC    63:0
`define FIRE_DLC_MMU_CSR_CTL_POSITION   0
`define FIRE_DLC_MMU_CSR_CTL_LOW_ADDR_WIDTH     0
`define FIRE_DLC_MMU_CSR_CTL_ADDR_RANGE 26:0
`define FIRE_DLC_MMU_CSR_CTL_READ_MASK  64'b0000000000001111001111110000000000000000000011110001011100001111
`define FIRE_DLC_MMU_CSR_CTL_READ_ONLY_MASK     64'b0000000000001111001111110000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_WRITE_MASK 64'b0000000000000000000000000000000000000000000011110001011100001111
`define FIRE_DLC_MMU_CSR_CTL_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_RMASK      64'b0000000000001111001111110000000000000000000011110001011100001111
`define FIRE_DLC_MMU_CSR_CTL_RESERVED_BIT_MASK  64'b1111111111110000110000001111111111111111111100001110100011110000
`define FIRE_DLC_MMU_CSR_CTL_HW_LD_MASK 64'b0000000000001111001111110000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_INTERNAL_REG       1
`define FIRE_DLC_MMU_CSR_CTL_ZERO_TIME_OMNI     1
`define FIRE_DLC_MMU_CSR_CTL_NUM_FIELDS 14
`define FIRE_DLC_MMU_CSR_CTL_SPARES_FID 0
`define FIRE_DLC_MMU_CSR_CTL_SPARES_SLC 51:48
`define FIRE_DLC_MMU_CSR_CTL_SPARES_WIDTH       4
`define FIRE_DLC_MMU_CSR_CTL_SPARES_INT_SLC     3:0
`define FIRE_DLC_MMU_CSR_CTL_SPARES_POSITION    48
`define FIRE_DLC_MMU_CSR_CTL_SPARES_FMASK       64'b0000000000001111000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_SPARES_HW_LD_MASK  64'b0000000000001111000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_SPARES_POR_VALUE   4'b0000
`define FIRE_DLC_MMU_CSR_CTL_PAQ_FID    1
`define FIRE_DLC_MMU_CSR_CTL_PAQ_SLC    45:45
`define FIRE_DLC_MMU_CSR_CTL_PAQ_WIDTH  1
`define FIRE_DLC_MMU_CSR_CTL_PAQ_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_CTL_PAQ_POSITION       45
`define FIRE_DLC_MMU_CSR_CTL_PAQ_FMASK  64'b0000000000000000001000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_PAQ_HW_LD_MASK     64'b0000000000000000001000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_PAQ_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_CTL_VAQ_FID    2
`define FIRE_DLC_MMU_CSR_CTL_VAQ_SLC    44:44
`define FIRE_DLC_MMU_CSR_CTL_VAQ_WIDTH  1
`define FIRE_DLC_MMU_CSR_CTL_VAQ_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_CTL_VAQ_POSITION       44
`define FIRE_DLC_MMU_CSR_CTL_VAQ_FMASK  64'b0000000000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_VAQ_HW_LD_MASK     64'b0000000000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_VAQ_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_CTL_TPL_FID    3
`define FIRE_DLC_MMU_CSR_CTL_TPL_SLC    43:43
`define FIRE_DLC_MMU_CSR_CTL_TPL_WIDTH  1
`define FIRE_DLC_MMU_CSR_CTL_TPL_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_CTL_TPL_POSITION       43
`define FIRE_DLC_MMU_CSR_CTL_TPL_FMASK  64'b0000000000000000000010000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_TPL_HW_LD_MASK     64'b0000000000000000000010000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_TPL_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_CTL_TIP_FID    4
`define FIRE_DLC_MMU_CSR_CTL_TIP_SLC    42:42
`define FIRE_DLC_MMU_CSR_CTL_TIP_WIDTH  1
`define FIRE_DLC_MMU_CSR_CTL_TIP_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_CTL_TIP_POSITION       42
`define FIRE_DLC_MMU_CSR_CTL_TIP_FMASK  64'b0000000000000000000001000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_TIP_HW_LD_MASK     64'b0000000000000000000001000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_TIP_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_CTL_TCM_FID    5
`define FIRE_DLC_MMU_CSR_CTL_TCM_SLC    41:40
`define FIRE_DLC_MMU_CSR_CTL_TCM_WIDTH  2
`define FIRE_DLC_MMU_CSR_CTL_TCM_INT_SLC        1:0
`define FIRE_DLC_MMU_CSR_CTL_TCM_POSITION       40
`define FIRE_DLC_MMU_CSR_CTL_TCM_FMASK  64'b0000000000000000000000110000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_TCM_HW_LD_MASK     64'b0000000000000000000000110000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_TCM_POR_VALUE      2'b00
`define FIRE_DLC_MMU_CSR_CTL_SPAREC_FID 6
`define FIRE_DLC_MMU_CSR_CTL_SPAREC_SLC 19:16
`define FIRE_DLC_MMU_CSR_CTL_SPAREC_WIDTH       4
`define FIRE_DLC_MMU_CSR_CTL_SPAREC_INT_SLC     3:0
`define FIRE_DLC_MMU_CSR_CTL_SPAREC_POSITION    16
`define FIRE_DLC_MMU_CSR_CTL_SPAREC_FMASK       64'b0000000000000000000000000000000000000000000011110000000000000000
`define FIRE_DLC_MMU_CSR_CTL_SPAREC_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_SPAREC_POR_VALUE   4'b0000
`define FIRE_DLC_MMU_CSR_CTL_PD_FID     7
`define FIRE_DLC_MMU_CSR_CTL_PD_SLC     12:12
`define FIRE_DLC_MMU_CSR_CTL_PD_WIDTH   1
`define FIRE_DLC_MMU_CSR_CTL_PD_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_CTL_PD_POSITION        12
`define FIRE_DLC_MMU_CSR_CTL_PD_FMASK   64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_DLC_MMU_CSR_CTL_PD_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_PD_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_CTL_SE_FID     8
`define FIRE_DLC_MMU_CSR_CTL_SE_SLC     10:10
`define FIRE_DLC_MMU_CSR_CTL_SE_WIDTH   1
`define FIRE_DLC_MMU_CSR_CTL_SE_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_CTL_SE_POSITION        10
`define FIRE_DLC_MMU_CSR_CTL_SE_FMASK   64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_DLC_MMU_CSR_CTL_SE_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_SE_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_CTL_CM_FID     9
`define FIRE_DLC_MMU_CSR_CTL_CM_SLC     9:8
`define FIRE_DLC_MMU_CSR_CTL_CM_WIDTH   2
`define FIRE_DLC_MMU_CSR_CTL_CM_INT_SLC 1:0
`define FIRE_DLC_MMU_CSR_CTL_CM_POSITION        8
`define FIRE_DLC_MMU_CSR_CTL_CM_FMASK   64'b0000000000000000000000000000000000000000000000000000001100000000
`define FIRE_DLC_MMU_CSR_CTL_CM_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_CM_POR_VALUE       2'b00
`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_FID      10
`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_SLC      3:3
`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_WIDTH    1
`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_INT_SLC  0:0
`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_POSITION 3
`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_FMASK    64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_BUSID_SEL_POR_VALUE        1'b0
`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_FID       11
`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_SLC       2:2
`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_WIDTH     1
`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_INT_SLC   0:0
`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_POSITION  2
`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_SUN4V_EN_POR_VALUE 1'b0
`define FIRE_DLC_MMU_CSR_CTL_BE_FID     12
`define FIRE_DLC_MMU_CSR_CTL_BE_SLC     1:1
`define FIRE_DLC_MMU_CSR_CTL_BE_WIDTH   1
`define FIRE_DLC_MMU_CSR_CTL_BE_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_CTL_BE_POSITION        1
`define FIRE_DLC_MMU_CSR_CTL_BE_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_MMU_CSR_CTL_BE_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_BE_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_CTL_TE_FID     13
`define FIRE_DLC_MMU_CSR_CTL_TE_SLC     0:0
`define FIRE_DLC_MMU_CSR_CTL_TE_WIDTH   1
`define FIRE_DLC_MMU_CSR_CTL_TE_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_CTL_TE_POSITION        0
`define FIRE_DLC_MMU_CSR_CTL_TE_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_CTL_TE_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_CTL_TE_POR_VALUE       1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_tsb
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_TSB_HW_ADDR  27'b000000011001000000000000001
`define FIRE_DLC_MMU_CSR_A_TSB_ADDR     30'b000000011001000000000000001000
`define FIRE_DLC_MMU_CSR_B_TSB_HW_ADDR  27'b000000011101000000000000001
`define FIRE_DLC_MMU_CSR_B_TSB_ADDR     30'b000000011101000000000000001000

`define FIRE_DLC_MMU_CSR_TSB_WIDTH      64
`define FIRE_DLC_MMU_CSR_TSB_DEPTH      1
`define FIRE_DLC_MMU_CSR_TSB_SLC        63:0
`define FIRE_DLC_MMU_CSR_TSB_INT_SLC    63:0
`define FIRE_DLC_MMU_CSR_TSB_POSITION   0
`define FIRE_DLC_MMU_CSR_TSB_LOW_ADDR_WIDTH     0
`define FIRE_DLC_MMU_CSR_TSB_ADDR_RANGE 26:0
`define FIRE_DLC_MMU_CSR_TSB_READ_MASK  64'b0000000000000000000000000111111111111111111111111110000100001111
`define FIRE_DLC_MMU_CSR_TSB_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_WRITE_MASK 64'b0000000000000000000000000111111111111111111111111110000100001111
`define FIRE_DLC_MMU_CSR_TSB_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_RMASK      64'b0000000000000000000000000111111111111111111111111110000100001111
`define FIRE_DLC_MMU_CSR_TSB_RESERVED_BIT_MASK  64'b1111111111111111111111111000000000000000000000000001111011110000
`define FIRE_DLC_MMU_CSR_TSB_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_INTERNAL_REG       1
`define FIRE_DLC_MMU_CSR_TSB_ZERO_TIME_OMNI     1
`define FIRE_DLC_MMU_CSR_TSB_NUM_FIELDS 3
`define FIRE_DLC_MMU_CSR_TSB_TB_FID     0
`define FIRE_DLC_MMU_CSR_TSB_TB_SLC     38:13
`define FIRE_DLC_MMU_CSR_TSB_TB_WIDTH   26
`define FIRE_DLC_MMU_CSR_TSB_TB_INT_SLC 25:0
`define FIRE_DLC_MMU_CSR_TSB_TB_POSITION        13
`define FIRE_DLC_MMU_CSR_TSB_TB_FMASK   64'b0000000000000000000000000111111111111111111111111110000000000000
`define FIRE_DLC_MMU_CSR_TSB_TB_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_TB_POR_VALUE       26'b00000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_PS_FID     1
`define FIRE_DLC_MMU_CSR_TSB_PS_SLC     8:8
`define FIRE_DLC_MMU_CSR_TSB_PS_WIDTH   1
`define FIRE_DLC_MMU_CSR_TSB_PS_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_TSB_PS_POSITION        8
`define FIRE_DLC_MMU_CSR_TSB_PS_FMASK   64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_MMU_CSR_TSB_PS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_PS_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_TSB_TS_FID     2
`define FIRE_DLC_MMU_CSR_TSB_TS_SLC     3:0
`define FIRE_DLC_MMU_CSR_TSB_TS_WIDTH   4
`define FIRE_DLC_MMU_CSR_TSB_TS_INT_SLC 3:0
`define FIRE_DLC_MMU_CSR_TSB_TS_POSITION        0
`define FIRE_DLC_MMU_CSR_TSB_TS_FMASK   64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_MMU_CSR_TSB_TS_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TSB_TS_POR_VALUE       4'b0000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_fsh
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_FSH_HW_ADDR  27'b000000011001000000000100000
`define FIRE_DLC_MMU_CSR_A_FSH_ADDR     30'b000000011001000000000100000000
`define FIRE_DLC_MMU_CSR_B_FSH_HW_ADDR  27'b000000011101000000000100000
`define FIRE_DLC_MMU_CSR_B_FSH_ADDR     30'b000000011101000000000100000000

`define FIRE_DLC_MMU_CSR_FSH_WIDTH      64
`define FIRE_DLC_MMU_CSR_FSH_DEPTH      1
`define FIRE_DLC_MMU_CSR_FSH_SLC        63:0
`define FIRE_DLC_MMU_CSR_FSH_INT_SLC    63:0
`define FIRE_DLC_MMU_CSR_FSH_POSITION   0
`define FIRE_DLC_MMU_CSR_FSH_LOW_ADDR_WIDTH     0
`define FIRE_DLC_MMU_CSR_FSH_ADDR_RANGE 26:0
`define FIRE_DLC_MMU_CSR_FSH_READ_MASK  64'b0000000000000000000000000111111111111111111111111111111111000000
`define FIRE_DLC_MMU_CSR_FSH_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FSH_WRITE_MASK 64'b0000000000000000000000000111111111111111111111111111111111000000
`define FIRE_DLC_MMU_CSR_FSH_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FSH_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FSH_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FSH_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FSH_RMASK      64'b0000000000000000000000000111111111111111111111111111111111000000
`define FIRE_DLC_MMU_CSR_FSH_RESERVED_BIT_MASK  64'b1111111111111111111111111000000000000000000000000000000000111111
`define FIRE_DLC_MMU_CSR_FSH_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FSH_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FSH_INTERNAL_REG       1
`define FIRE_DLC_MMU_CSR_FSH_ZERO_TIME_OMNI     1
`define FIRE_DLC_MMU_CSR_FSH_NUM_FIELDS 1
`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_FID      0
`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_SLC      38:6
`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_WIDTH    33
`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_INT_SLC  32:0
`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_POSITION 6
`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_FMASK    64'b0000000000000000000000000111111111111111111111111111111111000000
`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FSH_FLSH_ADDR_POR_VALUE        33'b000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_inv
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_INV_HW_ADDR  27'b000000011001000000000100001
`define FIRE_DLC_MMU_CSR_A_INV_ADDR     30'b000000011001000000000100001000
`define FIRE_DLC_MMU_CSR_B_INV_HW_ADDR  27'b000000011101000000000100001
`define FIRE_DLC_MMU_CSR_B_INV_ADDR     30'b000000011101000000000100001000

`define FIRE_DLC_MMU_CSR_INV_WIDTH      64
`define FIRE_DLC_MMU_CSR_INV_DEPTH      1
`define FIRE_DLC_MMU_CSR_INV_SLC        63:0
`define FIRE_DLC_MMU_CSR_INV_INT_SLC    63:0
`define FIRE_DLC_MMU_CSR_INV_POSITION   0
`define FIRE_DLC_MMU_CSR_INV_LOW_ADDR_WIDTH     0
`define FIRE_DLC_MMU_CSR_INV_ADDR_RANGE 26:0
`define FIRE_DLC_MMU_CSR_INV_READ_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INV_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INV_WRITE_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_INV_WRITE_ONLY_MASK    64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_INV_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INV_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INV_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INV_RMASK      64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_INV_RESERVED_BIT_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INV_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INV_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INV_INTERNAL_REG       0
`define FIRE_DLC_MMU_CSR_INV_EXTERNAL_DECODE_REG        1
`define FIRE_DLC_MMU_CSR_INV_ZERO_TIME_OMNI     0
`define FIRE_DLC_MMU_CSR_INV_NUM_FIELDS 1
`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_FID       0
`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_SLC       63:0
`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_WIDTH     64
`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_INT_SLC   63:0
`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_POSITION  0
`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_FMASK     64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INV_FLSH_TTE_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_log
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_LOG_HW_ADDR  27'b000000011001000001000000000
`define FIRE_DLC_MMU_CSR_A_LOG_ADDR     30'b000000011001000001000000000000
`define FIRE_DLC_MMU_CSR_B_LOG_HW_ADDR  27'b000000011101000001000000000
`define FIRE_DLC_MMU_CSR_B_LOG_ADDR     30'b000000011101000001000000000000

`define FIRE_DLC_MMU_CSR_LOG_WIDTH      64
`define FIRE_DLC_MMU_CSR_LOG_DEPTH      1
`define FIRE_DLC_MMU_CSR_LOG_SLC        63:0
`define FIRE_DLC_MMU_CSR_LOG_INT_SLC    63:0
`define FIRE_DLC_MMU_CSR_LOG_POSITION   0
`define FIRE_DLC_MMU_CSR_LOG_LOW_ADDR_WIDTH     0
`define FIRE_DLC_MMU_CSR_LOG_ADDR_RANGE 26:0
`define FIRE_DLC_MMU_CSR_LOG_READ_MASK  64'b0000000000000000000000000000000000000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_LOG_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_LOG_WRITE_MASK 64'b0000000000000000000000000000000000000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_LOG_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_LOG_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_LOG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_LOG_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_LOG_RMASK      64'b0000000000000000000000000000000000000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_LOG_RESERVED_BIT_MASK  64'b1111111111111111111111111111111111111111111000000000000000000000
`define FIRE_DLC_MMU_CSR_LOG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_LOG_POR_VALUE  64'b0000000000000000000000000000000000000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_LOG_INTERNAL_REG       1
`define FIRE_DLC_MMU_CSR_LOG_ZERO_TIME_OMNI     1
`define FIRE_DLC_MMU_CSR_LOG_NUM_FIELDS 1
`define FIRE_DLC_MMU_CSR_LOG_EN_FID     0
`define FIRE_DLC_MMU_CSR_LOG_EN_SLC     20:0
`define FIRE_DLC_MMU_CSR_LOG_EN_WIDTH   21
`define FIRE_DLC_MMU_CSR_LOG_EN_INT_SLC 20:0
`define FIRE_DLC_MMU_CSR_LOG_EN_POSITION        0
`define FIRE_DLC_MMU_CSR_LOG_EN_FMASK   64'b0000000000000000000000000000000000000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_LOG_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_LOG_EN_POR_VALUE       21'b111111111111111111111

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_int_en
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_INT_EN_HW_ADDR       27'b000000011001000001000000001
`define FIRE_DLC_MMU_CSR_A_INT_EN_ADDR  30'b000000011001000001000000001000
`define FIRE_DLC_MMU_CSR_B_INT_EN_HW_ADDR       27'b000000011101000001000000001
`define FIRE_DLC_MMU_CSR_B_INT_EN_ADDR  30'b000000011101000001000000001000

`define FIRE_DLC_MMU_CSR_INT_EN_WIDTH   64
`define FIRE_DLC_MMU_CSR_INT_EN_DEPTH   1
`define FIRE_DLC_MMU_CSR_INT_EN_SLC     63:0
`define FIRE_DLC_MMU_CSR_INT_EN_INT_SLC 63:0
`define FIRE_DLC_MMU_CSR_INT_EN_POSITION        0
`define FIRE_DLC_MMU_CSR_INT_EN_LOW_ADDR_WIDTH  0
`define FIRE_DLC_MMU_CSR_INT_EN_ADDR_RANGE      26:0
`define FIRE_DLC_MMU_CSR_INT_EN_READ_MASK       64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_INT_EN_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_WRITE_MASK      64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_INT_EN_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_RMASK   64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_INT_EN_RESERVED_BIT_MASK       64'b1111111111100000000000000000000011111111111000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_INTERNAL_REG    1
`define FIRE_DLC_MMU_CSR_INT_EN_ZERO_TIME_OMNI  1
`define FIRE_DLC_MMU_CSR_INT_EN_NUM_FIELDS      2
`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_FID        0
`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_SLC        52:32
`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_WIDTH      21
`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_INT_SLC    20:0
`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_POSITION   32
`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_FMASK      64'b0000000000011111111111111111111100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_EN_S_POR_VALUE  21'b000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_FID        1
`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_SLC        20:0
`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_WIDTH      21
`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_INT_SLC    20:0
`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_POSITION   0
`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_FMASK      64'b0000000000000000000000000000000000000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_INT_EN_EN_P_POR_VALUE  21'b000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_en_err
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_EN_ERR_HW_ADDR       27'b000000011001000001000000010
`define FIRE_DLC_MMU_CSR_A_EN_ERR_ADDR  30'b000000011001000001000000010000
`define FIRE_DLC_MMU_CSR_B_EN_ERR_HW_ADDR       27'b000000011101000001000000010
`define FIRE_DLC_MMU_CSR_B_EN_ERR_ADDR  30'b000000011101000001000000010000

`define FIRE_DLC_MMU_CSR_EN_ERR_WIDTH   64
`define FIRE_DLC_MMU_CSR_EN_ERR_DEPTH   1
`define FIRE_DLC_MMU_CSR_EN_ERR_SLC     63:0
`define FIRE_DLC_MMU_CSR_EN_ERR_INT_SLC 63:0
`define FIRE_DLC_MMU_CSR_EN_ERR_POSITION        0
`define FIRE_DLC_MMU_CSR_EN_ERR_LOW_ADDR_WIDTH  0
`define FIRE_DLC_MMU_CSR_EN_ERR_ADDR_RANGE      26:0
`define FIRE_DLC_MMU_CSR_EN_ERR_READ_MASK       64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_EN_ERR_READ_ONLY_MASK  64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_EN_ERR_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_RMASK   64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_EN_ERR_RESERVED_BIT_MASK       64'b1111111111100000000000000000000011111111111000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_HW_LD_MASK      64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_EN_ERR_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_INTERNAL_REG    0
`define FIRE_DLC_MMU_CSR_EN_ERR_EXTERNAL_DECODE_REG     1
`define FIRE_DLC_MMU_CSR_EN_ERR_ZERO_TIME_OMNI  0
`define FIRE_DLC_MMU_CSR_EN_ERR_NUM_FIELDS      2
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_FID       0
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_SLC       52:32
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_WIDTH     21
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_INT_SLC   20:0
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_POSITION  32
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_FMASK     64'b0000000000011111111111111111111100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_HW_LD_MASK        64'b0000000000011111111111111111111100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_S_POR_VALUE 21'b000000000000000000000
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_FID       1
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_SLC       20:0
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_WIDTH     21
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_INT_SLC   20:0
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_POSITION  0
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_FMASK     64'b0000000000000000000000000000000000000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_HW_LD_MASK        64'b0000000000000000000000000000000000000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_EN_ERR_ERR_P_POR_VALUE 21'b000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_err_rw1c_alias
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_HW_ADDR       27'b000000011001000001000000011
`define FIRE_DLC_MMU_CSR_A_ERR_RW1C_ALIAS_ADDR  30'b000000011001000001000000011000
`define FIRE_DLC_MMU_CSR_B_ERR_RW1C_ALIAS_HW_ADDR       27'b000000011101000001000000011
`define FIRE_DLC_MMU_CSR_B_ERR_RW1C_ALIAS_ADDR  30'b000000011101000001000000011000

`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WIDTH   64
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_DEPTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SLC     63:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_INT_SLC 63:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_POSITION        0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_LOW_ADDR_WIDTH  0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_ADDR_RANGE      26:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_READ_MASK       64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SET_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_CLEAR_MASK      64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_RMASK   64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_RESERVED_BIT_MASK       64'b1111111111100000000000000000000011111111111000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_HW_LD_MASK      64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_INTERNAL_REG    1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_ZERO_TIME_OMNI  1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_NUM_FIELDS      42
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_FID     0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_SLC     52:52
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_POSITION        52
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_FMASK   64'b0000000000010000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_HW_LD_MASK      64'b0000000000010000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_S_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_FID   1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_SLC   51:51
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_POSITION      51
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_FMASK 64'b0000000000001000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_HW_LD_MASK    64'b0000000000001000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_FID      2
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_SLC      50:50
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_WIDTH    1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_INT_SLC  0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_POSITION 50
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_FMASK    64'b0000000000000100000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_HW_LD_MASK       64'b0000000000000100000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_S_POR_VALUE        1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_FID     3
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_SLC     49:49
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_POSITION        49
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_FMASK   64'b0000000000000010000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_HW_LD_MASK      64'b0000000000000010000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_S_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_FID     4
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_SLC     48:48
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_POSITION        48
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_FMASK   64'b0000000000000001000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_HW_LD_MASK      64'b0000000000000001000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_S_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_FID   5
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_SLC   47:47
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_POSITION      47
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_FMASK 64'b0000000000000000100000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_HW_LD_MASK    64'b0000000000000000100000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_FID   6
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_SLC   46:46
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_POSITION      46
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_FMASK 64'b0000000000000000010000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_HW_LD_MASK    64'b0000000000000000010000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_FID   7
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_SLC   45:45
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_POSITION      45
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_FMASK 64'b0000000000000000001000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_HW_LD_MASK    64'b0000000000000000001000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_FID   8
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_SLC   44:44
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_POSITION      44
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_FMASK 64'b0000000000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_HW_LD_MASK    64'b0000000000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_FID    9
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_SLC    43:43
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_POSITION       43
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_FMASK  64'b0000000000000000000010000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_HW_LD_MASK     64'b0000000000000000000010000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_S_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_FID    10
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_SLC    42:42
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_POSITION       42
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_FMASK  64'b0000000000000000000001000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_HW_LD_MASK     64'b0000000000000000000001000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_S_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_FID   11
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_SLC   41:41
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_POSITION      41
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_FMASK 64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_HW_LD_MASK    64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_FID   12
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_SLC   40:40
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_POSITION      40
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_FMASK 64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_HW_LD_MASK    64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_FID   13
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_SLC   39:39
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_POSITION      39
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_HW_LD_MASK    64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_FID   14
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_SLC   38:38
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_POSITION      38
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_HW_LD_MASK    64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_FID   15
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_SLC   37:37
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_POSITION      37
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_HW_LD_MASK    64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_FID   16
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_SLC   36:36
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_POSITION      36
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_HW_LD_MASK    64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_FID    17
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_SLC    35:35
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_POSITION       35
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_FMASK  64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_HW_LD_MASK     64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_S_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_FID    18
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_SLC    34:34
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_POSITION       34
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_FMASK  64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_HW_LD_MASK     64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_S_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_FID   19
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_SLC   33:33
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_POSITION      33
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_HW_LD_MASK    64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_FID   20
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_SLC   32:32
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_POSITION      32
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_HW_LD_MASK    64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_FID     21
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_SLC     20:20
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_POSITION        20
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_FMASK   64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_KEY_ERR_P_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_FID   22
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_SLC   19:19
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_POSITION      19
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_FMASK 64'b0000000000000000000000000000000000000000000010000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000010000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_ADJ_UF_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_FID      23
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_SLC      18:18
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_WIDTH    1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_INT_SLC  0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_POSITION 18
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_FMASK    64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_HW_LD_MASK       64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SUN4V_VA_OOR_P_POR_VALUE        1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_FID     24
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_SLC     17:17
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_POSITION        17
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_FMASK   64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_DPE_P_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_FID     25
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_SLC     16:16
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_POSITION        16
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_FMASK   64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_IOTSBDESC_INV_P_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_FID   26
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_SLC   15:15
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_POSITION      15
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DPE_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_FID   27
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_SLC   14:14
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_POSITION      14
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_ERR_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_FID   28
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_SLC   13:13
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_POSITION      13
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_UDE_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_FID   29
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_SLC   12:12
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_POSITION      12
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TBW_DME_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_FID    30
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_SLC    11:11
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_POSITION       11
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_FMASK  64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE3_P_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_FID    31
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_SLC    10:10
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_POSITION       10
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_FMASK  64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE2_P_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_FID   32
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_SLC   9:9
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_POSITION      9
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_CAE_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_FID   33
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_SLC   8:8
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_POSITION      8
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTC_DPE_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_FID   34
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_SLC   7:7
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_POSITION      7
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_PRT_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_FID   35
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_SLC   6:6
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_POSITION      6
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TTE_INV_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_FID   36
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_SLC   5:5
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_POSITION      5
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_OOR_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_FID   37
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_SLC   4:4
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_POSITION      4
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_TRN_ERR_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_FID    38
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_SLC    3:3
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_POSITION       3
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE1_P_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_FID    39
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_SLC    2:2
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_POSITION       2
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_SPARE0_P_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_FID   40
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_SLC   1:1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_POSITION      1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_OOR_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_FID   41
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_SLC   0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_POSITION      0
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_ERR_RW1C_ALIAS_BYP_ERR_P_POR_VALUE     1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_err_rw1s_alias
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_HW_ADDR       27'b000000011001000001000000100
`define FIRE_DLC_MMU_CSR_A_ERR_RW1S_ALIAS_ADDR  30'b000000011001000001000000100000
`define FIRE_DLC_MMU_CSR_B_ERR_RW1S_ALIAS_HW_ADDR       27'b000000011101000001000000100
`define FIRE_DLC_MMU_CSR_B_ERR_RW1S_ALIAS_ADDR  30'b000000011101000001000000100000

`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_WIDTH   64
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_DEPTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SLC     63:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_INT_SLC 63:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_POSITION        0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_LOW_ADDR_WIDTH  0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_ADDR_RANGE      26:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_READ_MASK       64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_READ_ONLY_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_WRITE_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SET_MASK        64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_CLEAR_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TOGGLE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_RMASK   64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_RESERVED_BIT_MASK       64'b1111111111100000000000000000000011111111111000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_HW_LD_MASK      64'b0000000000011111111111111111111100000000000111111111111111111111
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_POR_VALUE       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_INTERNAL_REG    1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_ZERO_TIME_OMNI  1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_NUM_FIELDS      42
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_FID     0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_SLC     52:52
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_POSITION        52
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_FMASK   64'b0000000000010000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_HW_LD_MASK      64'b0000000000010000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_S_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_FID   1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_SLC   51:51
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_POSITION      51
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_FMASK 64'b0000000000001000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_HW_LD_MASK    64'b0000000000001000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_FID      2
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_SLC      50:50
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_WIDTH    1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_INT_SLC  0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_POSITION 50
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_FMASK    64'b0000000000000100000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_HW_LD_MASK       64'b0000000000000100000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_S_POR_VALUE        1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_FID     3
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_SLC     49:49
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_POSITION        49
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_FMASK   64'b0000000000000010000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_HW_LD_MASK      64'b0000000000000010000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_S_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_FID     4
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_SLC     48:48
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_POSITION        48
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_FMASK   64'b0000000000000001000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_HW_LD_MASK      64'b0000000000000001000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_S_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_FID   5
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_SLC   47:47
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_POSITION      47
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_FMASK 64'b0000000000000000100000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_HW_LD_MASK    64'b0000000000000000100000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_FID   6
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_SLC   46:46
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_POSITION      46
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_FMASK 64'b0000000000000000010000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_HW_LD_MASK    64'b0000000000000000010000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_FID   7
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_SLC   45:45
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_POSITION      45
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_FMASK 64'b0000000000000000001000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_HW_LD_MASK    64'b0000000000000000001000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_FID   8
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_SLC   44:44
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_POSITION      44
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_FMASK 64'b0000000000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_HW_LD_MASK    64'b0000000000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_FID    9
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_SLC    43:43
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_POSITION       43
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_FMASK  64'b0000000000000000000010000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_HW_LD_MASK     64'b0000000000000000000010000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_S_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_FID    10
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_SLC    42:42
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_POSITION       42
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_FMASK  64'b0000000000000000000001000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_HW_LD_MASK     64'b0000000000000000000001000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_S_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_FID   11
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_SLC   41:41
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_POSITION      41
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_FMASK 64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_HW_LD_MASK    64'b0000000000000000000000100000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_FID   12
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_SLC   40:40
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_POSITION      40
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_FMASK 64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_HW_LD_MASK    64'b0000000000000000000000010000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_FID   13
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_SLC   39:39
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_POSITION      39
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_FMASK 64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_HW_LD_MASK    64'b0000000000000000000000001000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_FID   14
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_SLC   38:38
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_POSITION      38
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_FMASK 64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_HW_LD_MASK    64'b0000000000000000000000000100000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_FID   15
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_SLC   37:37
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_POSITION      37
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_FMASK 64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_HW_LD_MASK    64'b0000000000000000000000000010000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_FID   16
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_SLC   36:36
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_POSITION      36
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_FMASK 64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_HW_LD_MASK    64'b0000000000000000000000000001000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_FID    17
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_SLC    35:35
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_POSITION       35
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_FMASK  64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_HW_LD_MASK     64'b0000000000000000000000000000100000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_S_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_FID    18
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_SLC    34:34
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_POSITION       34
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_FMASK  64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_HW_LD_MASK     64'b0000000000000000000000000000010000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_S_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_FID   19
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_SLC   33:33
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_POSITION      33
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_FMASK 64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_HW_LD_MASK    64'b0000000000000000000000000000001000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_FID   20
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_SLC   32:32
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_POSITION      32
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_FMASK 64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_HW_LD_MASK    64'b0000000000000000000000000000000100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_S_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_FID     21
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_SLC     20:20
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_POSITION        20
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_FMASK   64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000100000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_KEY_ERR_P_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_FID   22
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_SLC   19:19
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_POSITION      19
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_FMASK 64'b0000000000000000000000000000000000000000000010000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000010000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_ADJ_UF_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_FID      23
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_SLC      18:18
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_WIDTH    1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_INT_SLC  0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_POSITION 18
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_FMASK    64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_HW_LD_MASK       64'b0000000000000000000000000000000000000000000001000000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SUN4V_VA_OOR_P_POR_VALUE        1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_FID     24
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_SLC     17:17
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_POSITION        17
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_FMASK   64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000100000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_DPE_P_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_FID     25
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_SLC     16:16
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_WIDTH   1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_INT_SLC 0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_POSITION        16
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_FMASK   64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000010000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_IOTSBDESC_INV_P_POR_VALUE       1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_FID   26
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_SLC   15:15
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_POSITION      15
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000001000000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DPE_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_FID   27
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_SLC   14:14
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_POSITION      14
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000100000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_ERR_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_FID   28
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_SLC   13:13
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_POSITION      13
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_FMASK 64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000010000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_UDE_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_FID   29
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_SLC   12:12
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_POSITION      12
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_FMASK 64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000001000000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TBW_DME_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_FID    30
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_SLC    11:11
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_POSITION       11
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_FMASK  64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000100000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE3_P_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_FID    31
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_SLC    10:10
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_POSITION       10
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_FMASK  64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000010000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE2_P_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_FID   32
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_SLC   9:9
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_POSITION      9
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000001000000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_CAE_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_FID   33
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_SLC   8:8
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_POSITION      8
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000100000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTC_DPE_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_FID   34
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_SLC   7:7
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_POSITION      7
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_PRT_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_FID   35
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_SLC   6:6
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_POSITION      6
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000001000000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TTE_INV_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_FID   36
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_SLC   5:5
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_POSITION      5
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000100000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_OOR_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_FID   37
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_SLC   4:4
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_POSITION      4
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000010000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_TRN_ERR_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_FID    38
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_SLC    3:3
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_POSITION       3
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE1_P_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_FID    39
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_SLC    2:2
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_WIDTH  1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_POSITION       2
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_SPARE0_P_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_FID   40
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_SLC   1:1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_POSITION      1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_OOR_P_POR_VALUE     1'b0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_FID   41
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_SLC   0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_WIDTH 1
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_INT_SLC       0:0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_POSITION      0
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_ERR_RW1S_ALIAS_BYP_ERR_P_POR_VALUE     1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_flta
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_FLTA_HW_ADDR 27'b000000011001000001000000101
`define FIRE_DLC_MMU_CSR_A_FLTA_ADDR    30'b000000011001000001000000101000
`define FIRE_DLC_MMU_CSR_B_FLTA_HW_ADDR 27'b000000011101000001000000101
`define FIRE_DLC_MMU_CSR_B_FLTA_ADDR    30'b000000011101000001000000101000

`define FIRE_DLC_MMU_CSR_FLTA_WIDTH     64
`define FIRE_DLC_MMU_CSR_FLTA_DEPTH     1
`define FIRE_DLC_MMU_CSR_FLTA_SLC       63:0
`define FIRE_DLC_MMU_CSR_FLTA_INT_SLC   63:0
`define FIRE_DLC_MMU_CSR_FLTA_POSITION  0
`define FIRE_DLC_MMU_CSR_FLTA_LOW_ADDR_WIDTH    0
`define FIRE_DLC_MMU_CSR_FLTA_ADDR_RANGE        26:0
`define FIRE_DLC_MMU_CSR_FLTA_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111100
`define FIRE_DLC_MMU_CSR_FLTA_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTA_WRITE_MASK        64'b1111111111111111111111111111111111111111111111111111111111111100
`define FIRE_DLC_MMU_CSR_FLTA_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTA_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTA_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTA_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTA_RMASK     64'b1111111111111111111111111111111111111111111111111111111111111100
`define FIRE_DLC_MMU_CSR_FLTA_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000011
`define FIRE_DLC_MMU_CSR_FLTA_HW_LD_MASK        64'b1111111111111111111111111111111111111111111111111111111111111100
`define FIRE_DLC_MMU_CSR_FLTA_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTA_INTERNAL_REG      1
`define FIRE_DLC_MMU_CSR_FLTA_ZERO_TIME_OMNI    1
`define FIRE_DLC_MMU_CSR_FLTA_NUM_FIELDS        1
`define FIRE_DLC_MMU_CSR_FLTA_VA_FID    0
`define FIRE_DLC_MMU_CSR_FLTA_VA_SLC    63:2
`define FIRE_DLC_MMU_CSR_FLTA_VA_WIDTH  62
`define FIRE_DLC_MMU_CSR_FLTA_VA_INT_SLC        61:0
`define FIRE_DLC_MMU_CSR_FLTA_VA_POSITION       2
`define FIRE_DLC_MMU_CSR_FLTA_VA_FMASK  64'b1111111111111111111111111111111111111111111111111111111111111100
`define FIRE_DLC_MMU_CSR_FLTA_VA_HW_LD_MASK     64'b1111111111111111111111111111111111111111111111111111111111111100
`define FIRE_DLC_MMU_CSR_FLTA_VA_POR_VALUE      62'b00000000000000000000000000000000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_flts
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_FLTS_HW_ADDR 27'b000000011001000001000000110
`define FIRE_DLC_MMU_CSR_A_FLTS_ADDR    30'b000000011001000001000000110000
`define FIRE_DLC_MMU_CSR_B_FLTS_HW_ADDR 27'b000000011101000001000000110
`define FIRE_DLC_MMU_CSR_B_FLTS_ADDR    30'b000000011101000001000000110000

`define FIRE_DLC_MMU_CSR_FLTS_WIDTH     64
`define FIRE_DLC_MMU_CSR_FLTS_DEPTH     1
`define FIRE_DLC_MMU_CSR_FLTS_SLC       63:0
`define FIRE_DLC_MMU_CSR_FLTS_INT_SLC   63:0
`define FIRE_DLC_MMU_CSR_FLTS_POSITION  0
`define FIRE_DLC_MMU_CSR_FLTS_LOW_ADDR_WIDTH    0
`define FIRE_DLC_MMU_CSR_FLTS_ADDR_RANGE        26:0
`define FIRE_DLC_MMU_CSR_FLTS_READ_MASK 64'b0000000000000000000000011111111100000000011111111111111111111111
`define FIRE_DLC_MMU_CSR_FLTS_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_WRITE_MASK        64'b0000000000000000000000011111111100000000011111111111111111111111
`define FIRE_DLC_MMU_CSR_FLTS_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_RMASK     64'b0000000000000000000000011111111100000000011111111111111111111111
`define FIRE_DLC_MMU_CSR_FLTS_RESERVED_BIT_MASK 64'b1111111111111111111111100000000011111111100000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_HW_LD_MASK        64'b0000000000000000000000011111111100000000011111111111111111111111
`define FIRE_DLC_MMU_CSR_FLTS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_INTERNAL_REG      1
`define FIRE_DLC_MMU_CSR_FLTS_ZERO_TIME_OMNI    1
`define FIRE_DLC_MMU_CSR_FLTS_NUM_FIELDS        3
`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_FID 0
`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_SLC 40:32
`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_WIDTH       9
`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC     8:0
`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_POSITION    32
`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_FMASK       64'b0000000000000000000000011111111100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_HW_LD_MASK  64'b0000000000000000000000011111111100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_ENTRY_POR_VALUE   9'b000000000
`define FIRE_DLC_MMU_CSR_FLTS_TYPE_FID  1
`define FIRE_DLC_MMU_CSR_FLTS_TYPE_SLC  22:16
`define FIRE_DLC_MMU_CSR_FLTS_TYPE_WIDTH        7
`define FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC      6:0
`define FIRE_DLC_MMU_CSR_FLTS_TYPE_POSITION     16
`define FIRE_DLC_MMU_CSR_FLTS_TYPE_FMASK        64'b0000000000000000000000000000000000000000011111110000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_TYPE_HW_LD_MASK   64'b0000000000000000000000000000000000000000011111110000000000000000
`define FIRE_DLC_MMU_CSR_FLTS_TYPE_POR_VALUE    7'b0000000
`define FIRE_DLC_MMU_CSR_FLTS_ID_FID    2
`define FIRE_DLC_MMU_CSR_FLTS_ID_SLC    15:0
`define FIRE_DLC_MMU_CSR_FLTS_ID_WIDTH  16
`define FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC        15:0
`define FIRE_DLC_MMU_CSR_FLTS_ID_POSITION       0
`define FIRE_DLC_MMU_CSR_FLTS_ID_FMASK  64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_MMU_CSR_FLTS_ID_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_MMU_CSR_FLTS_ID_POR_VALUE      16'b0000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_prfc
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_PRFC_HW_ADDR 27'b000000011001000010000000000
`define FIRE_DLC_MMU_CSR_A_PRFC_ADDR    30'b000000011001000010000000000000
`define FIRE_DLC_MMU_CSR_B_PRFC_HW_ADDR 27'b000000011101000010000000000
`define FIRE_DLC_MMU_CSR_B_PRFC_ADDR    30'b000000011101000010000000000000

`define FIRE_DLC_MMU_CSR_PRFC_WIDTH     64
`define FIRE_DLC_MMU_CSR_PRFC_DEPTH     1
`define FIRE_DLC_MMU_CSR_PRFC_SLC       63:0
`define FIRE_DLC_MMU_CSR_PRFC_INT_SLC   63:0
`define FIRE_DLC_MMU_CSR_PRFC_POSITION  0
`define FIRE_DLC_MMU_CSR_PRFC_LOW_ADDR_WIDTH    0
`define FIRE_DLC_MMU_CSR_PRFC_ADDR_RANGE        26:0
`define FIRE_DLC_MMU_CSR_PRFC_READ_MASK 64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_MMU_CSR_PRFC_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_WRITE_MASK        64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_MMU_CSR_PRFC_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_RMASK     64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_MMU_CSR_PRFC_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111110000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_INTERNAL_REG      1
`define FIRE_DLC_MMU_CSR_PRFC_ZERO_TIME_OMNI    1
`define FIRE_DLC_MMU_CSR_PRFC_NUM_FIELDS        2
`define FIRE_DLC_MMU_CSR_PRFC_SEL1_FID  0
`define FIRE_DLC_MMU_CSR_PRFC_SEL1_SLC  15:8
`define FIRE_DLC_MMU_CSR_PRFC_SEL1_WIDTH        8
`define FIRE_DLC_MMU_CSR_PRFC_SEL1_INT_SLC      7:0
`define FIRE_DLC_MMU_CSR_PRFC_SEL1_POSITION     8
`define FIRE_DLC_MMU_CSR_PRFC_SEL1_FMASK        64'b0000000000000000000000000000000000000000000000001111111100000000
`define FIRE_DLC_MMU_CSR_PRFC_SEL1_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_SEL1_POR_VALUE    8'b00000000
`define FIRE_DLC_MMU_CSR_PRFC_SEL0_FID  1
`define FIRE_DLC_MMU_CSR_PRFC_SEL0_SLC  7:0
`define FIRE_DLC_MMU_CSR_PRFC_SEL0_WIDTH        8
`define FIRE_DLC_MMU_CSR_PRFC_SEL0_INT_SLC      7:0
`define FIRE_DLC_MMU_CSR_PRFC_SEL0_POSITION     0
`define FIRE_DLC_MMU_CSR_PRFC_SEL0_FMASK        64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_DLC_MMU_CSR_PRFC_SEL0_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRFC_SEL0_POR_VALUE    8'b00000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_prf0
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_PRF0_HW_ADDR 27'b000000011001000010000000001
`define FIRE_DLC_MMU_CSR_A_PRF0_ADDR    30'b000000011001000010000000001000
`define FIRE_DLC_MMU_CSR_B_PRF0_HW_ADDR 27'b000000011101000010000000001
`define FIRE_DLC_MMU_CSR_B_PRF0_ADDR    30'b000000011101000010000000001000

`define FIRE_DLC_MMU_CSR_PRF0_WIDTH     64
`define FIRE_DLC_MMU_CSR_PRF0_DEPTH     1
`define FIRE_DLC_MMU_CSR_PRF0_SLC       63:0
`define FIRE_DLC_MMU_CSR_PRF0_INT_SLC   63:0
`define FIRE_DLC_MMU_CSR_PRF0_POSITION  0
`define FIRE_DLC_MMU_CSR_PRF0_LOW_ADDR_WIDTH    0
`define FIRE_DLC_MMU_CSR_PRF0_ADDR_RANGE        26:0
`define FIRE_DLC_MMU_CSR_PRF0_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF0_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF0_WRITE_MASK        64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF0_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF0_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF0_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF0_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF0_RMASK     64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF0_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF0_HW_LD_MASK        64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF0_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF0_INTERNAL_REG      1
`define FIRE_DLC_MMU_CSR_PRF0_ZERO_TIME_OMNI    1
`define FIRE_DLC_MMU_CSR_PRF0_NUM_FIELDS        1
`define FIRE_DLC_MMU_CSR_PRF0_CNT_FID   0
`define FIRE_DLC_MMU_CSR_PRF0_CNT_SLC   63:0
`define FIRE_DLC_MMU_CSR_PRF0_CNT_WIDTH 64
`define FIRE_DLC_MMU_CSR_PRF0_CNT_INT_SLC       63:0
`define FIRE_DLC_MMU_CSR_PRF0_CNT_POSITION      0
`define FIRE_DLC_MMU_CSR_PRF0_CNT_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF0_CNT_HW_LD_MASK    64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF0_CNT_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_prf1
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_PRF1_HW_ADDR 27'b000000011001000010000000010
`define FIRE_DLC_MMU_CSR_A_PRF1_ADDR    30'b000000011001000010000000010000
`define FIRE_DLC_MMU_CSR_B_PRF1_HW_ADDR 27'b000000011101000010000000010
`define FIRE_DLC_MMU_CSR_B_PRF1_ADDR    30'b000000011101000010000000010000

`define FIRE_DLC_MMU_CSR_PRF1_WIDTH     64
`define FIRE_DLC_MMU_CSR_PRF1_DEPTH     1
`define FIRE_DLC_MMU_CSR_PRF1_SLC       63:0
`define FIRE_DLC_MMU_CSR_PRF1_INT_SLC   63:0
`define FIRE_DLC_MMU_CSR_PRF1_POSITION  0
`define FIRE_DLC_MMU_CSR_PRF1_LOW_ADDR_WIDTH    0
`define FIRE_DLC_MMU_CSR_PRF1_ADDR_RANGE        26:0
`define FIRE_DLC_MMU_CSR_PRF1_READ_MASK 64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF1_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF1_WRITE_MASK        64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF1_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF1_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF1_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF1_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF1_RMASK     64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF1_RESERVED_BIT_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF1_HW_LD_MASK        64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF1_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PRF1_INTERNAL_REG      1
`define FIRE_DLC_MMU_CSR_PRF1_ZERO_TIME_OMNI    1
`define FIRE_DLC_MMU_CSR_PRF1_NUM_FIELDS        1
`define FIRE_DLC_MMU_CSR_PRF1_CNT_FID   0
`define FIRE_DLC_MMU_CSR_PRF1_CNT_SLC   63:0
`define FIRE_DLC_MMU_CSR_PRF1_CNT_WIDTH 64
`define FIRE_DLC_MMU_CSR_PRF1_CNT_INT_SLC       63:0
`define FIRE_DLC_MMU_CSR_PRF1_CNT_POSITION      0
`define FIRE_DLC_MMU_CSR_PRF1_CNT_FMASK 64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF1_CNT_HW_LD_MASK    64'b1111111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_PRF1_CNT_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_vtb
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_VTB_HW_ADDR  27'b000000011001000110000000000
`define FIRE_DLC_MMU_CSR_A_VTB_ADDR     30'b000000011001000110000000000000
`define FIRE_DLC_MMU_CSR_B_VTB_HW_ADDR  27'b000000011101000110000000000
`define FIRE_DLC_MMU_CSR_B_VTB_ADDR     30'b000000011101000110000000000000

`define FIRE_DLC_MMU_CSR_VTB_WIDTH      64
`define FIRE_DLC_MMU_CSR_VTB_DEPTH      64
`define FIRE_DLC_MMU_CSR_VTB_SLC        63:0
`define FIRE_DLC_MMU_CSR_VTB_INT_SLC    63:0
`define FIRE_DLC_MMU_CSR_VTB_POSITION   0
`define FIRE_DLC_MMU_CSR_VTB_LOW_ADDR_WIDTH     6
`define FIRE_DLC_MMU_CSR_VTB_SEL_RANGE  5:0
`define FIRE_DLC_MMU_CSR_VTB_ADDR_RANGE 26:6
`define FIRE_DLC_MMU_CSR_VTB_READ_MASK  64'b0000000111111111111111111111111111111111111111111111100000000001
`define FIRE_DLC_MMU_CSR_VTB_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_VTB_WRITE_MASK 64'b0000000111111111111111111111111111111111111111111111100000000001
`define FIRE_DLC_MMU_CSR_VTB_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_VTB_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_VTB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_VTB_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_VTB_RMASK      64'b0000000111111111111111111111111111111111111111111111100000000001
`define FIRE_DLC_MMU_CSR_VTB_RESERVED_BIT_MASK  64'b1111111000000000000000000000000000000000000000000000011111111110
`define FIRE_DLC_MMU_CSR_VTB_HW_LD_MASK 64'b0000000111111111111111111111111111111111111111111111100000000001
`define FIRE_DLC_MMU_CSR_VTB_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_VTB_INTERNAL_REG       0
`define FIRE_DLC_MMU_CSR_VTB_EXTERNAL_DECODE_REG        0
`define FIRE_DLC_MMU_CSR_VTB_ZERO_TIME_OMNI     0
`define FIRE_DLC_MMU_CSR_VTB_NUM_FIELDS 4
`define FIRE_DLC_MMU_CSR_VTB_CNT_FID    0
`define FIRE_DLC_MMU_CSR_VTB_CNT_SLC    56:40
`define FIRE_DLC_MMU_CSR_VTB_CNT_WIDTH  17
`define FIRE_DLC_MMU_CSR_VTB_CNT_INT_SLC        16:0
`define FIRE_DLC_MMU_CSR_VTB_CNT_POSITION       40
`define FIRE_DLC_MMU_CSR_VTB_CNT_FMASK  64'b0000000111111111111111110000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_VTB_CNT_HW_LD_MASK     64'b0000000111111111111111110000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_VTB_CNT_POR_VALUE      17'b00000000000000000
`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_FID 1
`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_SLC 39:16
`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_WIDTH       24
`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_INT_SLC     23:0
`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_POSITION    16
`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_FMASK       64'b0000000000000000000000001111111111111111111111110000000000000000
`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_HW_LD_MASK  64'b0000000000000000000000001111111111111111111111110000000000000000
`define FIRE_DLC_MMU_CSR_VTB_VPN_OR_ADJ_VPN_POR_VALUE   24'b000000000000000000000000
`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_FID       2
`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_SLC       15:11
`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_WIDTH     5
`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_INT_SLC   4:0
`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_POSITION  11
`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_FMASK     64'b0000000000000000000000000000000000000000000000001111100000000000
`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000001111100000000000
`define FIRE_DLC_MMU_CSR_VTB_IOTSB_NO_POR_VALUE 5'b00000
`define FIRE_DLC_MMU_CSR_VTB_VLD_FID    3
`define FIRE_DLC_MMU_CSR_VTB_VLD_SLC    0:0
`define FIRE_DLC_MMU_CSR_VTB_VLD_WIDTH  1
`define FIRE_DLC_MMU_CSR_VTB_VLD_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_VTB_VLD_POSITION       0
`define FIRE_DLC_MMU_CSR_VTB_VLD_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_VTB_VLD_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_VTB_VLD_POR_VALUE      1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_ptb
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_PTB_HW_ADDR  27'b000000011001000111000000000
`define FIRE_DLC_MMU_CSR_A_PTB_ADDR     30'b000000011001000111000000000000
`define FIRE_DLC_MMU_CSR_B_PTB_HW_ADDR  27'b000000011101000111000000000
`define FIRE_DLC_MMU_CSR_B_PTB_ADDR     30'b000000011101000111000000000000

`define FIRE_DLC_MMU_CSR_PTB_WIDTH      64
`define FIRE_DLC_MMU_CSR_PTB_DEPTH      64
`define FIRE_DLC_MMU_CSR_PTB_SLC        63:0
`define FIRE_DLC_MMU_CSR_PTB_INT_SLC    63:0
`define FIRE_DLC_MMU_CSR_PTB_POSITION   0
`define FIRE_DLC_MMU_CSR_PTB_LOW_ADDR_WIDTH     6
`define FIRE_DLC_MMU_CSR_PTB_SEL_RANGE  5:0
`define FIRE_DLC_MMU_CSR_PTB_ADDR_RANGE 26:6
`define FIRE_DLC_MMU_CSR_PTB_READ_MASK  64'b0000000000000000000000000111111111111111111111111111111111000001
`define FIRE_DLC_MMU_CSR_PTB_READ_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PTB_WRITE_MASK 64'b0000000000000000000000000111111111111111111111111111111111000001
`define FIRE_DLC_MMU_CSR_PTB_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PTB_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PTB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PTB_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PTB_RMASK      64'b0000000000000000000000000111111111111111111111111111111111000001
`define FIRE_DLC_MMU_CSR_PTB_RESERVED_BIT_MASK  64'b1111111111111111111111111000000000000000000000000000000000111110
`define FIRE_DLC_MMU_CSR_PTB_HW_LD_MASK 64'b0000000000000000000000000111111111111111111111111111111111000001
`define FIRE_DLC_MMU_CSR_PTB_POR_VALUE  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PTB_INTERNAL_REG       0
`define FIRE_DLC_MMU_CSR_PTB_EXTERNAL_DECODE_REG        0
`define FIRE_DLC_MMU_CSR_PTB_ZERO_TIME_OMNI     0
`define FIRE_DLC_MMU_CSR_PTB_NUM_FIELDS 2
`define FIRE_DLC_MMU_CSR_PTB_TAG_FID    0
`define FIRE_DLC_MMU_CSR_PTB_TAG_SLC    38:6
`define FIRE_DLC_MMU_CSR_PTB_TAG_WIDTH  33
`define FIRE_DLC_MMU_CSR_PTB_TAG_INT_SLC        32:0
`define FIRE_DLC_MMU_CSR_PTB_TAG_POSITION       6
`define FIRE_DLC_MMU_CSR_PTB_TAG_FMASK  64'b0000000000000000000000000111111111111111111111111111111111000000
`define FIRE_DLC_MMU_CSR_PTB_TAG_HW_LD_MASK     64'b0000000000000000000000000111111111111111111111111111111111000000
`define FIRE_DLC_MMU_CSR_PTB_TAG_POR_VALUE      33'b000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_PTB_VLD_FID    1
`define FIRE_DLC_MMU_CSR_PTB_VLD_SLC    0:0
`define FIRE_DLC_MMU_CSR_PTB_VLD_WIDTH  1
`define FIRE_DLC_MMU_CSR_PTB_VLD_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_PTB_VLD_POSITION       0
`define FIRE_DLC_MMU_CSR_PTB_VLD_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_PTB_VLD_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_PTB_VLD_POR_VALUE      1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_tdb
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_TDB_HW_ADDR  27'b000000011001001000000000000
`define FIRE_DLC_MMU_CSR_A_TDB_ADDR     30'b000000011001001000000000000000
`define FIRE_DLC_MMU_CSR_B_TDB_HW_ADDR  27'b000000011101001000000000000
`define FIRE_DLC_MMU_CSR_B_TDB_ADDR     30'b000000011101001000000000000000

`define FIRE_DLC_MMU_CSR_TDB_WIDTH      64
`define FIRE_DLC_MMU_CSR_TDB_DEPTH      512
`define FIRE_DLC_MMU_CSR_TDB_SLC        63:0
`define FIRE_DLC_MMU_CSR_TDB_INT_SLC    63:0
`define FIRE_DLC_MMU_CSR_TDB_POSITION   0
`define FIRE_DLC_MMU_CSR_TDB_LOW_ADDR_WIDTH     9
`define FIRE_DLC_MMU_CSR_TDB_SEL_RANGE  8:0
`define FIRE_DLC_MMU_CSR_TDB_ADDR_RANGE 26:9
`define FIRE_DLC_MMU_CSR_TDB_READ_MASK  64'b1111111111111111111100000111111111111111111111111110000000111111
`define FIRE_DLC_MMU_CSR_TDB_READ_ONLY_MASK     64'b0000000000000000111100000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TDB_WRITE_MASK 64'b1111111111111111000000000111111111111111111111111110000000111111
`define FIRE_DLC_MMU_CSR_TDB_WRITE_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TDB_SET_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TDB_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TDB_TOGGLE_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TDB_RMASK      64'b1111111111111111111100000111111111111111111111111110000000111111
`define FIRE_DLC_MMU_CSR_TDB_RESERVED_BIT_MASK  64'b0000000000000000000011111000000000000000000000000001111111000000
`define FIRE_DLC_MMU_CSR_TDB_HW_LD_MASK 64'b1111111111111111111100000111111111111111111111111110000000111111
`define FIRE_DLC_MMU_CSR_TDB_POR_VALUE  64'bxxxxxxxxxxxxxxxxxxxx00000xxxxxxxxxxxxxxxxxxxxxxxxxx0000000xxxxxx
`define FIRE_DLC_MMU_CSR_TDB_INTERNAL_REG       0
`define FIRE_DLC_MMU_CSR_TDB_EXTERNAL_DECODE_REG        0
`define FIRE_DLC_MMU_CSR_TDB_ZERO_TIME_OMNI     0
`define FIRE_DLC_MMU_CSR_TDB_NUM_FIELDS 7
`define FIRE_DLC_MMU_CSR_TDB_KEY_FID    0
`define FIRE_DLC_MMU_CSR_TDB_KEY_SLC    63:48
`define FIRE_DLC_MMU_CSR_TDB_KEY_WIDTH  16
`define FIRE_DLC_MMU_CSR_TDB_KEY_INT_SLC        15:0
`define FIRE_DLC_MMU_CSR_TDB_KEY_POSITION       48
`define FIRE_DLC_MMU_CSR_TDB_KEY_FMASK  64'b1111111111111111000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TDB_KEY_HW_LD_MASK     64'b1111111111111111000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TDB_KEY_POR_VALUE      16'bxxxxxxxxxxxxxxxx
`define FIRE_DLC_MMU_CSR_TDB_PAR_FID    1
`define FIRE_DLC_MMU_CSR_TDB_PAR_SLC    47:44
`define FIRE_DLC_MMU_CSR_TDB_PAR_WIDTH  4
`define FIRE_DLC_MMU_CSR_TDB_PAR_INT_SLC        3:0
`define FIRE_DLC_MMU_CSR_TDB_PAR_POSITION       44
`define FIRE_DLC_MMU_CSR_TDB_PAR_FMASK  64'b0000000000000000111100000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TDB_PAR_HW_LD_MASK     64'b0000000000000000111100000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_TDB_PAR_POR_VALUE      4'bxxxx
`define FIRE_DLC_MMU_CSR_TDB_PPN_FID    2
`define FIRE_DLC_MMU_CSR_TDB_PPN_SLC    38:13
`define FIRE_DLC_MMU_CSR_TDB_PPN_WIDTH  26
`define FIRE_DLC_MMU_CSR_TDB_PPN_INT_SLC        25:0
`define FIRE_DLC_MMU_CSR_TDB_PPN_POSITION       13
`define FIRE_DLC_MMU_CSR_TDB_PPN_FMASK  64'b0000000000000000000000000111111111111111111111111110000000000000
`define FIRE_DLC_MMU_CSR_TDB_PPN_HW_LD_MASK     64'b0000000000000000000000000111111111111111111111111110000000000000
`define FIRE_DLC_MMU_CSR_TDB_PPN_POR_VALUE      26'bxxxxxxxxxxxxxxxxxxxxxxxxxx
`define FIRE_DLC_MMU_CSR_TDB_FNM_FID    3
`define FIRE_DLC_MMU_CSR_TDB_FNM_SLC    5:3
`define FIRE_DLC_MMU_CSR_TDB_FNM_WIDTH  3
`define FIRE_DLC_MMU_CSR_TDB_FNM_INT_SLC        2:0
`define FIRE_DLC_MMU_CSR_TDB_FNM_POSITION       3
`define FIRE_DLC_MMU_CSR_TDB_FNM_FMASK  64'b0000000000000000000000000000000000000000000000000000000000111000
`define FIRE_DLC_MMU_CSR_TDB_FNM_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000111000
`define FIRE_DLC_MMU_CSR_TDB_FNM_POR_VALUE      3'bxxx
`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_FID        4
`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_SLC        2:2
`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_WIDTH      1
`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_INT_SLC    0:0
`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_POSITION   2
`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_FMASK      64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_MMU_CSR_TDB_KEY_VLD_POR_VALUE  1'bx
`define FIRE_DLC_MMU_CSR_TDB_WRT_FID    5
`define FIRE_DLC_MMU_CSR_TDB_WRT_SLC    1:1
`define FIRE_DLC_MMU_CSR_TDB_WRT_WIDTH  1
`define FIRE_DLC_MMU_CSR_TDB_WRT_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_TDB_WRT_POSITION       1
`define FIRE_DLC_MMU_CSR_TDB_WRT_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_MMU_CSR_TDB_WRT_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_MMU_CSR_TDB_WRT_POR_VALUE      1'bx
`define FIRE_DLC_MMU_CSR_TDB_VLD_FID    6
`define FIRE_DLC_MMU_CSR_TDB_VLD_SLC    0:0
`define FIRE_DLC_MMU_CSR_TDB_VLD_WIDTH  1
`define FIRE_DLC_MMU_CSR_TDB_VLD_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_TDB_VLD_POSITION       0
`define FIRE_DLC_MMU_CSR_TDB_VLD_FMASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_TDB_VLD_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_MMU_CSR_TDB_VLD_POR_VALUE      1'bx

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_dev2iotsb
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_HW_ADDR    27'b000000011001001001000000000
`define FIRE_DLC_MMU_CSR_A_DEV2IOTSB_ADDR       30'b000000011001001001000000000000
`define FIRE_DLC_MMU_CSR_B_DEV2IOTSB_HW_ADDR    27'b000000011101001001000000000
`define FIRE_DLC_MMU_CSR_B_DEV2IOTSB_ADDR       30'b000000011101001001000000000000

`define FIRE_DLC_MMU_CSR_DEV2IOTSB_WIDTH        64
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_DEPTH        16
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_SLC  63:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_INT_SLC      63:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_POSITION     0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_LOW_ADDR_WIDTH       4
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_SEL_RANGE    3:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_ADDR_RANGE   26:4
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_READ_MASK    64'b0001111100011111000111110001111100011111000111110001111100011111
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_WRITE_MASK   64'b0001111100011111000111110001111100011111000111110001111100011111
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_RMASK        64'b0001111100011111000111110001111100011111000111110001111100011111
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_RESERVED_BIT_MASK    64'b1110000011100000111000001110000011100000111000001110000011100000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_INTERNAL_REG 0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_EXTERNAL_DECODE_REG  0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_ZERO_TIME_OMNI       0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_NUM_FIELDS   8
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_FID       0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_SLC       60:56
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_WIDTH     5
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_INT_SLC   4:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_POSITION  56
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_FMASK     64'b0001111100000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_0_POR_VALUE 5'b00000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_FID       1
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_SLC       52:48
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_WIDTH     5
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_INT_SLC   4:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_POSITION  48
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_FMASK     64'b0000000000011111000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_1_POR_VALUE 5'b00000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_FID       2
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_SLC       44:40
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_WIDTH     5
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_INT_SLC   4:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_POSITION  40
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_FMASK     64'b0000000000000000000111110000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_2_POR_VALUE 5'b00000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_FID       3
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_SLC       36:32
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_WIDTH     5
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_INT_SLC   4:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_POSITION  32
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_FMASK     64'b0000000000000000000000000001111100000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_3_POR_VALUE 5'b00000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_FID       4
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_SLC       28:24
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_WIDTH     5
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_INT_SLC   4:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_POSITION  24
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_FMASK     64'b0000000000000000000000000000000000011111000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_4_POR_VALUE 5'b00000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_FID       5
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_SLC       20:16
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_WIDTH     5
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_INT_SLC   4:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_POSITION  16
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_FMASK     64'b0000000000000000000000000000000000000000000111110000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_5_POR_VALUE 5'b00000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_FID       6
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_SLC       12:8
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_WIDTH     5
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_INT_SLC   4:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_POSITION  8
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_FMASK     64'b0000000000000000000000000000000000000000000000000001111100000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_6_POR_VALUE 5'b00000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_FID       7
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_SLC       4:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_WIDTH     5
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_INT_SLC   4:0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_POSITION  0
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_FMASK     64'b0000000000000000000000000000000000000000000000000000000000011111
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_DEV2IOTSB_IOTSB_NO_7_POR_VALUE 5'b00000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_mmu_csr_IotsbDesc
//-------------------------------------------------------

`define FIRE_DLC_MMU_CSR_A_IOTSBDESC_HW_ADDR    27'b000000011001001001000100000
`define FIRE_DLC_MMU_CSR_A_IOTSBDESC_ADDR       30'b000000011001001001000100000000
`define FIRE_DLC_MMU_CSR_B_IOTSBDESC_HW_ADDR    27'b000000011101001001000100000
`define FIRE_DLC_MMU_CSR_B_IOTSBDESC_ADDR       30'b000000011101001001000100000000

`define FIRE_DLC_MMU_CSR_IOTSBDESC_WIDTH        64
`define FIRE_DLC_MMU_CSR_IOTSBDESC_DEPTH        32
`define FIRE_DLC_MMU_CSR_IOTSBDESC_SLC  63:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_INT_SLC      63:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_POSITION     0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_LOW_ADDR_WIDTH       5
`define FIRE_DLC_MMU_CSR_IOTSBDESC_SEL_RANGE    4:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_ADDR_RANGE   26:5
`define FIRE_DLC_MMU_CSR_IOTSBDESC_READ_MASK    64'b1110111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_IOTSBDESC_READ_ONLY_MASK       64'b0110000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_WRITE_MASK   64'b1000111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_IOTSBDESC_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_RMASK        64'b1110111111111111111111111111111111111111111111111111111111111111
`define FIRE_DLC_MMU_CSR_IOTSBDESC_RESERVED_BIT_MASK    64'b0001000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_HW_LD_MASK   64'b0110000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_INTERNAL_REG 0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_EXTERNAL_DECODE_REG  0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_ZERO_TIME_OMNI       0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_FIELDS   6
`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_FID    0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_SLC    63:63
`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_WIDTH  1
`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_INT_SLC        0:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_POSITION       63
`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_FMASK  64'b1000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_VALID_POR_VALUE      1'b0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_FID      1
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_SLC      62:61
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_WIDTH    2
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_INT_SLC  1:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_POSITION 61
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_FMASK    64'b0110000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_HW_LD_MASK       64'b0110000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAR_POR_VALUE        2'b00
`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_FID  2
`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_SLC  59:34
`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_WIDTH        26
`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_INT_SLC      25:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_POSITION     34
`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_FMASK        64'b0000111111111111111111111111110000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_BASE_PA_POR_VALUE    26'b00000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_FID   3
`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_SLC   33:7
`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_WIDTH 27
`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_INT_SLC       26:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_POSITION      7
`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_FMASK 64'b0000000000000000000000000000001111111111111111111111111110000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_OFFSET_POR_VALUE     27'b000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_FID        4
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_SLC        6:4
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_WIDTH      3
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_INT_SLC    2:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_POSITION   4
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_FMASK      64'b0000000000000000000000000000000000000000000000000000000001110000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_PAGE_SIZE_POR_VALUE  3'b000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_FID        5
`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_SLC        3:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_WIDTH      4
`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_INT_SLC    3:0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_POSITION   0
`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_FMASK      64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_MMU_CSR_IOTSBDESC_NUM_PAGES_POR_VALUE  4'b0000


`endif